From patchwork Mon Nov 12 17:08:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150871 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3411145ljp; Mon, 12 Nov 2018 09:33:53 -0800 (PST) X-Google-Smtp-Source: AJdET5ciPtt39WTwuY6dioJ7E9v+vs5vybPGyt7YQKwdSDqDo8lOU32SRrv+5qU7jD0mV4yFx8p8 X-Received: by 2002:a0c:a1c6:: with SMTP id e64mr1876463qva.196.1542044033794; Mon, 12 Nov 2018 09:33:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542044033; cv=none; d=google.com; s=arc-20160816; b=aCslcKmMo5j8jcx/sgChtKpYKNwFuccNxvuP6jfq0r61/XhwJX2Dl2/ALcs4LdYO5l WL02AxY4nOD5W8Nd8D5xfr0wqu7ePAdBPVAX1+fQwQoHdbkuTRJcR4FNspc/HBXXv9p4 nuEs9/ljzrl/gvLRr+jLlXl8klnCcu9JEH9wRndKB8hVjYfm3J6t//GG3Ap6d+bz+sJP oXvl5Ko+vs4ZxB+Iv/lnKcSbLR7a7iyHJxNmxP0S/tnds+W2wwdeKf8N8eWy4CDbdNe4 7Sf808XrPz9LFhLaiQ3HpOgl+SBP6Odbx2nLjhpicrZfOHWgzQNc43rP1Ge2ZzESzgBh JDrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=oKNxg0lGDeN/qBICoXobW8GG3NPMPhB1oa+d8XeRF3k=; b=KUYT6s2zGxjPcyRFd002MhF6DPParLiPqwcFXuxo8NmuE32gd8q4/vZwj21nfDsMFK yO0887Upk7/3Z+d11nFXXiHduK8eFhlKbSqSwyJfvdFxoj8kxxh/6ANtJCaqGX4RM0di ca8w1cwByqscZj6jcWh6oVY/6NG+Vzc+39lkG+ckRLFnoa8AuHfjE2VDZw94HbGThON4 7fe911/BuutzEXz4OqrBVugzqmGe1/VykQ0GVPf5MycqxrwQIVDOaPN2/GdyzlVvrz7o H/kMI0cgdzlSV+wtcQFL/05rXPlHne2ERsxxAZ/ybHTlBOjVZztMpfpMMoqkELZ9nT60 2P8g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q125-v6si434984qkd.35.2018.11.12.09.33.53 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:33:53 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49901 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG5x-0005j4-3b for patch@linaro.org; Mon, 12 Nov 2018 12:33:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60843) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFih-0004p9-Ne for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFid-0001J7-Vl for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:51 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFiY-0008MG-Ez for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:45 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhF-0005qq-DX for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:21 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:01 +0000 Message-Id: <20181112170816.500-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/16] target/arm: Remove workaround for small SAU regions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Before we supported direct execution from MMIO regions, we implemented workarounds in commit 720424359917887c926a33d2 which let us avoid doing so, even if the SAU or MPU region was less than page-sized. Once we implemented execute-from-MMIO, we removed part of those workarounds in commit d4b6275df320cee76; but we forgot the one in get_phys_addr_pmsav8() which suppressed use of small SAU regions in executable regions. Remove that workaround now. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20181106163801.14474-1-peter.maydell@linaro.org --- target/arm/helper.c | 12 ------------ 1 file changed, 12 deletions(-) -- 2.19.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 96301930cc8..ec56becc394 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10560,18 +10560,6 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, txattrs, prot, &mpu_is_subpage, fi, NULL); - /* - * TODO: this is a temporary hack to ignore the fact that the SAU region - * is smaller than a page if this is an executable region. We never - * supported small MPU regions, but we did (accidentally) allow small - * SAU regions, and if we now made small SAU regions not be executable - * then this would break previously working guest code. We can't - * remove this until/unless we implement support for execution from - * small regions. - */ - if (*prot & PAGE_EXEC) { - sattrs.subpage = false; - } *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; return ret; } From patchwork Mon Nov 12 17:08:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150868 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3405324ljp; Mon, 12 Nov 2018 09:28:18 -0800 (PST) X-Google-Smtp-Source: AJdET5eIeJdGgbfEtw1CmT3A/syAr5m0AjuJsAGeQ5ly/I8RJ9z1J8dWZ4UqQtUh3zgty6tn+TXM X-Received: by 2002:ae9:eb4c:: with SMTP id b73mr1708513qkg.88.1542043698341; Mon, 12 Nov 2018 09:28:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043698; cv=none; d=google.com; s=arc-20160816; b=YelhpB1q+4OOwmdMYvbcZYyFjaqGCY8m5DWTk6cmT2n1igP/0r5SX+r4AayIztCTi0 SlS58VOqczXY0/wLIzjtAE63kGQiEJSpIo4W8GBEQBX4e6avpIyGxMn+72cAp9PkFvcM rfh24PkspNaN0RTE9GTjgNBEhe7ZH+Tp0QPWSoVqhfVBu4s60nyXMZjsu+3b0c0ZHvkv vaf7rdMyKKf93C7vNtXEy06sSbu9on3rx2A4TaDcvtGfj9HWe8wB3RdgnivNMlvJYWXy nk1UXx0msownxPVvsjOIx1MPIwCVoK0jiRm5joGbo+Mwwqd62jHXGjcMrUR9zfExcKyK lxBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=4vKO4TTGE2X0bGDIQlJ4zwwwtnxIUT60Td5tDYJqeOA=; b=sxVzIRIDKqxqBpflnU/QX9/vwkt0lnk9q8+F1VuNPQ4eI0ux3c19LSnSreql5eHm/3 60AQtyG5zwapWZKFc6AZD18d3tKVedY/bxcdGPg+NDbwmBSl4LRU7PnHk52FOgcajC3Q XHN9/1uXoAv8RXqlezZzN9SKFohTychpXcVjYEM6zbVaW1WiPwHfytfp/ueUb9qE3gr8 HceoqluNgyoYcicD6puTcBe1M1XpLdJXXjH+vEh048nfXRiMDVSDf6kmtHOH27cYzirm wxKycmGLsT01ADUQSXujE5f0sWjxXwE/rU+dU0sdp+pLuLNDz80+lJQU+QweoFDo22Vu mBaA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i64si3470276qtb.225.2018.11.12.09.28.17 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:28:18 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49872 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG0X-0003cT-Go for patch@linaro.org; Mon, 12 Nov 2018 12:28:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFiJ-0004V6-UH for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFiJ-0001C1-Aj for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:27 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFiJ-0008MG-3g for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:27 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhG-0005r5-9Y for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:22 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:02 +0000 Message-Id: <20181112170816.500-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/16] target/arm: Remove antique TODO comment X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove a TODO comment about implementing the vectored interrupt controller. We have had an implementation of that for a decade; it's in hw/intc/pl190.c. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181106164118.16184-1-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- target/arm/helper.c | 1 - 1 file changed, 1 deletion(-) -- 2.19.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index ec56becc394..851ea9aa977 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8378,7 +8378,6 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) return; } - /* TODO: Vectored interrupt controller. */ switch (cs->exception_index) { case EXCP_UDEF: new_mode = ARM_CPU_MODE_UND; From patchwork Mon Nov 12 17:08:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150866 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3404932ljp; Mon, 12 Nov 2018 09:27:53 -0800 (PST) X-Google-Smtp-Source: AJdET5e2nVRxkRzcRS36qEZFoOoNtDToiGuPkjslxZ2VG33tTPuhE57zBaL/KswGEWYI2D6vfeMs X-Received: by 2002:ac8:2c79:: with SMTP id e54mr1799122qta.17.1542043673725; Mon, 12 Nov 2018 09:27:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043673; cv=none; d=google.com; s=arc-20160816; b=UcSLSGPeh2xGIP2ChpxDDR4xkdl+ptd8jRSS+7gJ23lOGgFs7ttAz1MIeGp8AtHhFg yk0BLXhlulRuIa+8xbLuxWxBnvC5VX40INTZ6zh3hyCgqK/0DMbA9tiK8rYTem95RcGP KsgHAs4IvurFTZWUrQ/366C/b9x5D6bw/4ncoktDp/PD2lnODHASnNYecb3cTD6oOiKE Yq6VnE3XfgdrFlhYfd6XMYZNMr9qC+Tr40yx6jjvTOr4GzXOwHsZUSr0lAmpIOG7S0vk pZWfleHVdZNZQLsBmTIobwQYPlyX+ibmWQfzyvrkEbs9Eo4bxlTrWNwBv00LSOJtXprn uiGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=4u5EcLGvngv1ySVoBqSVIk/pVpsdO3hdDgOPTEE7uXE=; b=ORBF5mjPvOX1yIM+/Ssw8BSd39xtb69ixw9LYlg/pLgjENbpSC3byyrJ84MkuupStS wJiMU3CTbv1efKp2AWUypIdft90iP97JVcrvWgMEtpRL0W4PaQyODih+pzcHLeqjPmYm MB4Kb26tzWbY45CVTA3SF4t3ZAjOumiuKv/xKa31Nh18Iv9YnSzXZMmQhmCo/POBEff5 H3HtiNQ7Bf3iqIACtlMXOzSXqXVT4JKi4WR1wrHH42GBVL1C+m5DEDaeuHEQm5VhUeEX D2dGMlBCojlGpxfNKTGOiHsOPB6EpVt4uu7qm59bZW9sizsuXdXH9oTDXT4sKZJ2CrlU jbsA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p18si8503991qvj.89.2018.11.12.09.27.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:27:53 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49871 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG07-0003ZP-QP for patch@linaro.org; Mon, 12 Nov 2018 12:27:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFiJ-0004UN-46 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFiI-0001BD-D8 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:27 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFiI-0008MG-4Z for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:26 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhH-0005rJ-5w for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:23 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:03 +0000 Message-Id: <20181112170816.500-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/16] MAINTAINERS: Add an entry for the 'collie' machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Thomas Huth There is no active maintainer, but since Peter is picking up patches via qemu-arm@nongnu.org, I think we could at least use "Odd Fixes" as status here. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-id: 1541528230-31817-1-git-send-email-thuth@redhat.com [PMM: Also add myself as an M: contact] Signed-off-by: Peter Maydell --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.19.1 diff --git a/MAINTAINERS b/MAINTAINERS index c076758b3d6..4b8db618f51 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -591,6 +591,13 @@ F: hw/*/pxa2xx* F: hw/misc/mst_fpga.c F: include/hw/arm/pxa.h +Sharp SL-5500 (Collie) PDA +M: Peter Maydell +L: qemu-arm@nongnu.org +S: Odd Fixes +F: hw/arm/collie.c +F: hw/arm/strongarm* + Stellaris M: Peter Maydell L: qemu-arm@nongnu.org From patchwork Mon Nov 12 17:08:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150862 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3402756ljp; Mon, 12 Nov 2018 09:25:31 -0800 (PST) X-Google-Smtp-Source: AJdET5fjBwmQy7GKkJ8pe8UexGo5JcF2Zka5nyGjbS7Dl+6L2o0CcCZzYkARWhg3vQ70/QNd0RIL X-Received: by 2002:a0c:96c9:: with SMTP id b9mr1762091qvd.238.1542043530702; Mon, 12 Nov 2018 09:25:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043530; cv=none; d=google.com; s=arc-20160816; b=ZEMhJ1nbimpcLMWkBUBDL2ABiQPX25ksXDLjIDQ7ayVMGWGqQa9d9xQgxZ+0y5o+YQ MJAjrBsvf5/uXAZmIeF5W0wkSWMw/9ABG1tNsLvo1LUzpOKWL3K+wjEejU6KWQWx69gk PTh3VBclcSExH9YT7cMOZEzLENZ+nCyv0pobZKqcsNsnxsaxiU7DeY9OoFLWIzOftDny gQJOGx1MXuSXdrE3vmnV2e7joUvFZ/sI5H3d0aPGsRVIVGLMYWM6UzzMciDYRD+gu5J9 pT2kCxZYEmqVm631PjQJm6aWNv90QYkAHCJRPL3axtBw1Ux16Gjg/Sstwwhsp9gm3P9w as+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=IshGFwrJET8V4Acw+SsBmnXbYA44sXQyt7w+plI86EE=; b=G0cHaq+MAzisrK7/rIfdf8Ow5jaPoX8mqOKMpd8MRBMGjM4LScc31VywOHeDanowH4 EeII/Ox4/SKBUqsPVzK1wTr/fjekYgk5RGdO+QObqKM3+Sp+5QznCxOBjwMvTJ23ZBGc /pa6ZxZmHFhnyOEz2jNYlsUHL9Rcto4ev0ZW4mcr3PYbW9y3MuMA98j24EuOfVDmA2Uz +no7XQowIteFY+ocwZ2921LSkLhSU+j3lmSXtbl5CsQLQftbJF9oKJN6P+80DX3UYFkN fTNITSra5VYG8Nt/r5vUv1aHQXmQIz/8AF5nObM5X/SB8QMP7bvhVHBPonYVro760hdG +SXA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id j1si6975222qkj.111.2018.11.12.09.25.30 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:25:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49862 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFxp-000199-Us for patch@linaro.org; Mon, 12 Nov 2018 12:25:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60722) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFi8-0004KL-5s for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFi7-0000sQ-AF for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:16 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFi7-0008MG-1G for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:15 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhI-0005rX-2z for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:24 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:04 +0000 Message-Id: <20181112170816.500-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/16] hw/arm/sysbus-fdt: Only call match_fn callback if the type matches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger Commit af7d64ede0b9 (hw/arm/sysbus-fdt: Allow device matching with DT compatible value) introduced a match_fn callback which gets called for each registered combo to check whether a sysbus device can be dynamically instantiated. However the callback gets called even if the device type does not match the binding combo typename field. This causes an assert when passing "-device ramfb" to the qemu command line as vfio_platform_match() gets called on a non vfio-platform device. To fix this regression, let's change the add_fdt_node() logic so that we first check the type and if the match_fn callback is defined, then we also call it. Binding combos only requesting a type check do not define the match_fn callback. Fixes: af7d64ede0b9 (hw/arm/sysbus-fdt: Allow device matching with DT compatible value) Signed-off-by: Eric Auger Reported-by: Thomas Huth Reviewed-by: Alex Williamson Tested-by: Geert Uytterhoeven Message-id: 20181106184212.29377-1-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/sysbus-fdt.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.19.1 diff --git a/hw/arm/sysbus-fdt.c b/hw/arm/sysbus-fdt.c index 0e24c803a1c..ad698d4832c 100644 --- a/hw/arm/sysbus-fdt.c +++ b/hw/arm/sysbus-fdt.c @@ -449,7 +449,7 @@ static bool type_match(SysBusDevice *sbdev, const BindingEntry *entry) return !strcmp(object_get_typename(OBJECT(sbdev)), entry->typename); } -#define TYPE_BINDING(type, add_fn) {(type), NULL, (add_fn), type_match} +#define TYPE_BINDING(type, add_fn) {(type), NULL, (add_fn), NULL} /* list of supported dynamic sysbus bindings */ static const BindingEntry bindings[] = { @@ -481,10 +481,12 @@ static void add_fdt_node(SysBusDevice *sbdev, void *opaque) for (i = 0; i < ARRAY_SIZE(bindings); i++) { const BindingEntry *iter = &bindings[i]; - if (iter->match_fn(sbdev, iter)) { - ret = iter->add_fn(sbdev, opaque); - assert(!ret); - return; + if (type_match(sbdev, iter)) { + if (!iter->match_fn || iter->match_fn(sbdev, iter)) { + ret = iter->add_fn(sbdev, opaque); + assert(!ret); + return; + } } } error_report("Device %s can not be dynamically instantiated", From patchwork Mon Nov 12 17:08:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150872 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3411265ljp; Mon, 12 Nov 2018 09:34:00 -0800 (PST) X-Google-Smtp-Source: AJdET5fnmLzuvnc+XYNXpYvMz7zTYQG9HmbyJ2uH39aaT7ylEwd4mxqi90SyFw2j+evbZXp0GyIT X-Received: by 2002:a0c:94e5:: with SMTP id k34mr1898385qvk.215.1542044039963; Mon, 12 Nov 2018 09:33:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542044039; cv=none; d=google.com; s=arc-20160816; b=PMczybZIdZjUnWHVH9o1QJ+GdMa58cGyZXRIYIA/m3NtsV2pf+rlptGxGr4kKw461B /fUwLmeK5dxibWWbAgDHioUFBOCZCc25o+9rSeEL6OP1+zk/1ahkAn9vCJznfb3NAWGE W5t4O8XHUgCiorgD3xTJhT5pyFSi+SPIeJT0NrK4SJhU24TuhUhf3n6l+oJdRv8LwdZt Jn9JPHta/QTb61FyZwkoCaRDVU6SBVlqRZPi9nX0vjnTj1YmD+Y2i3h2M4NUOlVi33QM 9nPAGpp6dTulXqsBV11m4iMCNgWMLQH4V1cbf27SkSas0GBG6n5kCAKmzSLR5Tdf5zQv yVWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=SrsNwKPVhJaAXO9CO2POh6oCnh9z8oFr8c1xkUBmKCc=; b=IhsYrGrJ408id542M+1Fd6Wy5qMSjxgh+SUcloNWJYLn5fg2y/yjly2BoUa+V62Bdz 7EqrmmzPNIiH8Y+yU5W8aVOFwcSfnZdkwbbwLE9NkPTezWdcUXutEvP/07WNdfIoKdLv zeBls/hqAiC7YXuwHH7NLW8RqvETVpRqC8JV1Vgfw8q+U/toIOOeBrXQ0fe4RFXt4ZT+ zig6kzsx48azrUd3Dg3G5wFWmiljnpx7YmYJv511GH48yZibWYMFl4FBYL8g11I+JXcL 4aY9uGJ8o1EzeEvUF30zq+AUarI1O5HD2ixMytuEap3tcuBp/LL3nd/oT8Bhen6uCybL m8pQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o41si1083qve.31.2018.11.12.09.33.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:33:59 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49903 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG63-00070n-BT for patch@linaro.org; Mon, 12 Nov 2018 12:33:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60703) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFi6-0004Iq-Kv for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFi5-0000qr-Q5 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:14 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFi5-0008MG-G2 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:13 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhI-0005rl-Vt for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:24 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:05 +0000 Message-Id: <20181112170816.500-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/16] target/arm: Fix typo in tlbi_aa64_vmalle1_write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This would cause an infinite recursion or loop. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20181110121711.15257-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.19.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 851ea9aa977..d167bc5deff 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3155,7 +3155,7 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, CPUState *cs = ENV_GET_CPU(env); if (tlb_force_broadcast(env)) { - tlbi_aa64_vmalle1_write(env, NULL, value); + tlbi_aa64_vmalle1is_write(env, NULL, value); return; } From patchwork Mon Nov 12 17:08:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150857 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3395488ljp; Mon, 12 Nov 2018 09:18:27 -0800 (PST) X-Google-Smtp-Source: AJdET5f7NBJceXn0oG2897UB5m6GJwSm5RUX3A6Airy/X+1K9zzhT7vO415pBekrVYiNd/7P7N4N X-Received: by 2002:ac8:7518:: with SMTP id u24mr1777156qtq.75.1542043107805; Mon, 12 Nov 2018 09:18:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043107; cv=none; d=google.com; s=arc-20160816; b=Y807gowqtKWGSGQ9i1eIrAqXM4bnPzyJCdFMDhFFDx91/DycHaOaSUnsAqykVdGOKP t7oX1gYKzYf1JE8AlC0kVErm2fqgBtzETo6RILm0ZqQeXjkx68c9FHCVF4TF8nnABEyW naHsF8bF4fav7YZe4gDaLaJQVV5t8WJ8rxFyjZmi1ctHwq+DYjA0huRrU/vgXChy1oTM iMXxDuI9bzJ5mvzJRl1XwM/pLI0xpnUR2oAbyeQje3jkhAKIhJvXyY7+gMjmfa49CEh3 smnS77JJPNPC/rURW4uTkv92oKJTCpNFsGginDY1YyqU2roOU6DTGenySOIInMjVJ5Pg QpdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=UhLRZ2/GAu2P1FVUAx1uPdxHeyqpHqQ0y2ebf0aeam8=; b=E9Ksi+dubmWHF4AU3amT3NZ9pkJWL5KKpHq3MEDeTB/GULgtw1qMPZNe9D3MOe5CgS qWpMRXGo/27yxBPG3uOhVbcrHA6ZtjD/dg+a6PP7v7VdybvaZIt8lRKQXMcljZPiGt3V MrfQ+EWRNkp+F/oIeajd3eaopR2k3PTfash+WblcnVW8R37s9FOk0yfaLCJEGBLfO+ri UrCGIrfYMar7vhr3rdiw7fhz1Zc3EcL9w08IrzVhNTJBzoJ9kj4mW8xJd90eQiv8/6zL tRCtXmuTScsDhoxlveAI2TlprV2w6hIQprZPOaF2s2W25rgyu76DRhzEIRz7mACsA4nx 8yiw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id y11si4483178qtm.124.2018.11.12.09.18.27 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:18:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49813 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFr0-0003pj-BF for patch@linaro.org; Mon, 12 Nov 2018 12:18:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhv-00048t-1Q for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhu-0000gz-99 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:03 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFht-0008MG-Vh for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:02 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhK-0005rz-Kl for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:06 +0000 Message-Id: <20181112170816.500-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/16] target/arm64: properly handle DBGVR RESS bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée This only fails with some (broken) versions of gdb but we should treat the top bits of DBGBVR as RESS. Properly sign extend QEMU's reference copy of dbgbvr and also update the register descriptions in the comment. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) -- 2.19.1 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5de8ff0ac57..6351a54b287 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -103,7 +103,7 @@ static void kvm_arm_init_debug(CPUState *cs) * capable of fancier matching but that will require exposing that * fanciness to GDB's interface * - * D7.3.2 DBGBCR_EL1, Debug Breakpoint Control Registers + * DBGBCR_EL1, Debug Breakpoint Control Registers * * 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0 * +------+------+-------+-----+----+------+-----+------+-----+---+ @@ -115,12 +115,25 @@ static void kvm_arm_init_debug(CPUState *cs) * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12) * BAS: Byte Address Select (RES1 for AArch64) * E: Enable bit + * + * DBGBVR_EL1, Debug Breakpoint Value Registers + * + * 63 53 52 49 48 2 1 0 + * +------+-----------+----------+-----+ + * | RESS | VA[52:49] | VA[48:2] | 0 0 | + * +------+-----------+----------+-----+ + * + * Depending on the addressing mode bits the top bits of the register + * are a sign extension of the highest applicable VA bit. Some + * versions of GDB don't do it correctly so we ensure they are correct + * here so future PC comparisons will work properly. */ + static int insert_hw_breakpoint(target_ulong addr) { HWBreakpoint brk = { .bcr = 0x1, /* BCR E=1, enable */ - .bvr = addr + .bvr = sextract64(addr, 0, 53) }; if (cur_hw_bps >= max_hw_bps) { From patchwork Mon Nov 12 17:08:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150869 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3408032ljp; Mon, 12 Nov 2018 09:30:55 -0800 (PST) X-Google-Smtp-Source: AJdET5fk8WPslRd1mnKddxkd9zPZVwjt2ke6n6iIZaShHqodqheuvCzYyNLP3hAhaNOgik5WUkyG X-Received: by 2002:a0c:b301:: with SMTP id s1mr1843282qve.132.1542043855827; Mon, 12 Nov 2018 09:30:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043855; cv=none; d=google.com; s=arc-20160816; b=emuOoS+LmnMrTYy/++TfO24Bi8Zo9Yt7lzOS2g4izSOsyY56f1Y18/JxfZjVr/XAXu NPym1xW6BxJ5t7RrGa/ATNotcO8WIBW5MzkWr7wZuLFsRUeAC2l5QWmW1cGhD1pX+lY5 WKxWSYJfX5q2b5RJ0EKSSsQ2l6ML9QapDpgYiYIuJg6KdY5xLkFuldIdfgWgpPlTeizb gJ9QHvF7QFQ1ucbVf/5ZP0JNLDMCxXJZp2SAwh8VueJsfWde4qXjqwAwjtEp4Vm8K0eD Scmvg+AfzVc3rCEVM84ICSUcgxC3UfZA9hlSivc3ophcUO8KFezXng5St3L9Fq2kgKQu 4nZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=dQAqO3OMs8P26SQGjfMJbs1sGay5R8covpkN/9JAo6E=; b=jnAgLc9luN+j0BiVhAZrUp6U2deRz2xxwkkEt1KP6wCNKiAiqD62gXzJ3ylnaRsawK LQT2o0M5TRsMEtp6mLUSifiXu4zTr30vwyEAhrmq4ilABf1Dyjvv5bjbs6GjhkfUo7GD noKiUZFmVihrxIWof4RCIy7E/J7diO+A7PAS8cZPbrYnq6675XqgWwGDWEBshrhRZwec nSP6IKE7glLBMC6TLZcc+IMWTFAnn9Q09zV9t7yorRU/f6fvmYBKTLu+HBhLU6NgvPZd eA13BvlMJ7fD2wsbhj6KbEW2ox1ExtzbPfGVNDWSPx7ZQxr4WYbA0644iVHd2HUBU7L+ jWhQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r13si9900695qtr.290.2018.11.12.09.30.55 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:30:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49891 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG34-0006Ax-UK for patch@linaro.org; Mon, 12 Nov 2018 12:30:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFht-00046J-Rx for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFht-0000ge-92 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:01 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFht-0008MG-1V for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:01 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhL-0005sD-H1 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:27 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:07 +0000 Message-Id: <20181112170816.500-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/16] target/arm64: hold BQL when calling do_interrupt() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Fix the assertion failure when running interrupts. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-3-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.19.1 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6351a54b287..c39150e5e18 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1000,7 +1000,9 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) cs->exception_index = EXCP_BKPT; env->exception.syndrome = debug_exit->hsr; env->exception.vaddress = debug_exit->far; + qemu_mutex_lock_iothread(); cc->do_interrupt(cs); + qemu_mutex_unlock_iothread(); return false; } From patchwork Mon Nov 12 17:08:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150873 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3411574ljp; Mon, 12 Nov 2018 09:34:18 -0800 (PST) X-Google-Smtp-Source: AJdET5ezLzAKP4dE8WWkd69JmubWnwnoVYLSh4Jw/jkbjbS0scvC98H/NRJPrNRf1lTAirPTfLAx X-Received: by 2002:aed:2801:: with SMTP id r1mr1763242qtd.169.1542044057900; Mon, 12 Nov 2018 09:34:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542044057; cv=none; d=google.com; s=arc-20160816; b=NQa7DU2L0KPYdY0niWs69WXTs8aR8N7F/5ArUBZbpGgiFDTDcOyWDn7tBSgRD1hdLg TsJh2v0EB7Tms8y8+Sq18lB6lTVI4uVfA8S5NHceRncPAlwKfDdWX6y2n6O+LAWCUymi 2AQqhfjVi9a+vjunU8M+Y31uGR7YLKJN+vp0yYkaS4HS6dfUbn4iZ8Dj99vFZaPtDXxd bz63m7WEkQCugxaqJ21a4YtPEh3pk4SSYsmbg76jKRwvv615eeWKRS+46wmeZN1vUc9s sORuhMuC0gYPLsy6e+SC+1KxXJWo8EClZc6iiaCVmN2/I6xNWC10FlQBqvt26e/iNZIf CdUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=PKMNeH7ZdLeTIZIuperGae8ZZlFWKwJgs0RbwuSDUdE=; b=vkwJ7IFaPCY8zsADnHLWpOTjfF92aydNd/R5+EYeKKNiIVit40ZHJIvV/GdmiI0a5f ds4cjwpMHnJbNQVNk/xxK9yiCqDqIXyu+dsfKEBtWu7PmKKAJMIc/fdThNR+cy6OU/K8 GM/oVeo5Ae82eUNSzKyutVIAYvDqPorM/q3NSMijIsRYiP5U7fY53EMJnkOvFyaYjikP Qxwt2yxWNDULpMgvZmxyns8qNvulBQS9k84XFRa3rdDUWCY/KUGzmi/L4Y1r12lsWj67 gAA3ssPFznF+6glnJF3uUfK9QzCe4fgUMzUY3tmQ0j6iAkpbyRsQfJM20eSU1MpUoMel zLGw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s7si298392qvr.49.2018.11.12.09.34.17 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:34:17 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49906 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG6L-0007HQ-AU for patch@linaro.org; Mon, 12 Nov 2018 12:34:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60616) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhs-00045B-Va for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhs-0000gI-9r for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:00 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhs-0008MG-2e for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:00 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhM-0005sR-DH for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:28 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:08 +0000 Message-Id: <20181112170816.500-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/16] target/arm64: kvm debug set target_el when passing exception to guest X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée When we are debugging the guest all exceptions come our way but might be for the guest's own debug exceptions. We use the ->do_interrupt() infrastructure to inject the exception into the guest. However, we are missing a full setup of the exception structure, causing an assert later down the line. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-4-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 1 + 1 file changed, 1 insertion(+) -- 2.19.1 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index c39150e5e18..46fbe6d8ff6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1000,6 +1000,7 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) cs->exception_index = EXCP_BKPT; env->exception.syndrome = debug_exit->hsr; env->exception.vaddress = debug_exit->far; + env->exception.target_el = 1; qemu_mutex_lock_iothread(); cc->do_interrupt(cs); qemu_mutex_unlock_iothread(); From patchwork Mon Nov 12 17:08:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150867 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3405210ljp; Mon, 12 Nov 2018 09:28:11 -0800 (PST) X-Google-Smtp-Source: AJdET5cvP+bSYWX7A8MEu1r8XVZMvPIP3htot8eQJXFWYljJ1BdxeFaGmwAK1U6S4B8YGhfH5kRk X-Received: by 2002:a37:2d82:: with SMTP id t124mr1784029qkh.122.1542043690998; Mon, 12 Nov 2018 09:28:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043690; cv=none; d=google.com; s=arc-20160816; b=bNXbIcxD+tOQ4QgNWkJXp1etm0hO5iVBg8MYog7zPEMDkhrsfs804buQwKGjwPFlOC fjixr/CqxN+EOsBy9cYISFL7jyM6+L8cczEKEHbSyMRw266SYo00PoZSVotZ+w+xb6e7 UqI9rOLRR7WzILYoIKiGNHnn9QoFYnCV+8WwzI1O6fegasyPwy649Wt2Xivg30NngFPn ie0Fu1n7Zna0H1//qS6rybxm4VPjh/CVKB7JaM9TO5ziyn8+Y58oUwgXHu5FIliuQPon YNDuBX+iOWqlEkrk+PrLW7X6ADrrPW5WUw7Vp2IUqUcuJfItWkYMsafMhiZDUKnwKb2n 0F9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=4GWIjlg5B71KMTRHn9Neaws8vjSYENXONZXrAOEfGnY=; b=eRcFcb5nlCrm4gJVoJwPdlf/QmfJrMyobVCW8gmX+BPEPPw7LWJCaFGcsaZVwSesLN h8qQTXZPo96DL7JXZ70PdDsiCLIepLxFIBM49G1OngeLnS9ls+cTC2x639jQ+pySXMj5 eFk/SVa2ZMJZlVy806SUi7XfWRoHkofjpT22rOFNUl2eSoMID884nA3CtXvhAuZpIDeF +1tApwUAykPvbrppo2kOE5lfNIRV+FsDNYiJXXLS487na9HWc0ouyBUzr4jyLx5lx06E u5pcwVz8Fkn6EO0LP/KZJCzgtGUuksoICGOQtY2y8Ch8PUErP4RHk9UBowrS6DO/IFOs SsDg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id t14si4049182qvm.157.2018.11.12.09.28.10 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:28:10 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49873 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMG0Q-0003mK-8g for patch@linaro.org; Mon, 12 Nov 2018 12:28:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhs-00043J-1m for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhr-0000fu-AM for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:59 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhr-0008MG-2O for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:59 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhN-0005sf-9Y for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:29 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:09 +0000 Message-Id: <20181112170816.500-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/16] tests/guest-debug: fix scoping of failcount X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée You should declare you are using a global version of a variable before you attempt to modify it in a function. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-5-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- tests/guest-debug/test-gdbstub.py | 1 + 1 file changed, 1 insertion(+) -- 2.19.1 diff --git a/tests/guest-debug/test-gdbstub.py b/tests/guest-debug/test-gdbstub.py index 0e4ac014260..c7e3986a249 100644 --- a/tests/guest-debug/test-gdbstub.py +++ b/tests/guest-debug/test-gdbstub.py @@ -16,6 +16,7 @@ def report(cond, msg): print ("PASS: %s" % (msg)) else: print ("FAIL: %s" % (msg)) + global failcount failcount += 1 From patchwork Mon Nov 12 17:08:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150870 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3408446ljp; Mon, 12 Nov 2018 09:31:16 -0800 (PST) X-Google-Smtp-Source: AJdET5e9CSq1z0RaZV2npbLoHREDZcHpQAHLYzcpHmy1EBcMEWelxTM/f4wUxFW8/HPBdP17S+69 X-Received: by 2002:ac8:474e:: with SMTP id k14mr1817426qtp.117.1542043876538; Mon, 12 Nov 2018 09:31:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043876; cv=none; d=google.com; s=arc-20160816; b=x1ENXbbgVeveaDtzeGM3z4lDfGIfhRdFzO5JajnWLsymD1X5/iMFLr03pVI/w4wGEA dq3Om8kM+7qCQ0hWgApKPEE2raWDse+LCR6oePyhidPZJWaOynIRHywLCKr0qIqr2gnk rLKzaT8BYKAS3CHJI5kXDN77OBMr7Nvlq5zyX8EO1miM9VBNKY5ynq+x7uQl5dqmYfSr 0fnHeTvQGhuFUclyFryEF83Ep63rIjLtWETzCZcRiKdw5QMapEBVanyson5R2PugXLSy fjxGzB86IVNQLXdtMQ16N9xmZpl+X03LVvdsU5Aj/JTmBmXa8+/8boqp7CWa2Tlg0Czx LIuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=CKxBjm4cr46eF9gVvy8NqTvkqz9wUfeOK8kUa6pVViE=; b=bvpziyPE5sOFo0dgcO7ayB7hxNqk6u3LEgq041vqetkBF7k0W0kTVZQcLmrcLDtcP8 cTMGdg4vGHakpOayULQ4fkYi+aibi697rTrlOQqWtfW9IzePwKhTMi9AE7l6b4M5+JbO +i1ee5jqLtIkgbDMSxdiyHvMlRnemftcvDdaBBKaNHhjsOGPQydVkEmbemEX18KO99UR dqEREaVWMFbvgkoJefNLEtiC2oeqhElIGGZSm2qBuuq+rny+0aB69xL5bT+ot6niYcEh HeXlwvfrann1VV0loxBp9VNnv7y228ka6GLa26wnKbwfD35VeM5waQslbrgMBlXl+hv6 L5Jg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/16] arm: use symbolic MDCR_TDE in arm_debug_target_el X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée We already have this symbol defined so lets use it. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-7-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.19.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b5eff79f73b..1efff21a18d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2743,7 +2743,7 @@ static inline int arm_debug_target_el(CPUARMState *env) if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || - env->cp15.mdcr_el2 & (1 << 8); + env->cp15.mdcr_el2 & MDCR_TDE; } if (route_to_el2) { From patchwork Mon Nov 12 17:08:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150864 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3403557ljp; Mon, 12 Nov 2018 09:26:25 -0800 (PST) X-Google-Smtp-Source: AJdET5c6fA6GW/WahINBOkSoYMhlGmnPa8UHFD2voj+iIBMu2vav2cmhgP+CmwgPzZZ3Yi3RfdZW X-Received: by 2002:aed:3263:: with SMTP id y90mr1716219qtd.269.1542043585481; Mon, 12 Nov 2018 09:26:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043585; cv=none; d=google.com; s=arc-20160816; b=DC4d+iGTDJIbCkDguzD5xKU/JlqUt+jOLRzG9rQtgM+UZaMGM6MBFXkTczjBdcEWEq i8Wg70VH8Yzw5GRYVg6CSTSlKJOOahtyvV7vUH1ScqFhWLAI5/iNOk8wpIx06wgay8AZ dEbNvIhZlgAjUB1LaAWJBmniGNzSwGEpgYpKx5Ewc97JAmg/QgMuRrnLgJPcSBEbPDMv BZinxJMRzlbweyPUsbA9uir2KNQz4dgl5jOIzTcX7IvoV0PdzAVtdF+EbjDgVJurBaaI iyBhc5J33Gv5XT7qNUF2wuO1H3PYh9hfw5tFtfqZEEckEi8H9wKohh6qm1TgwVWn+Fqg Yhew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=E5M4utaQdSPOK7d/ONkJSdW7WQYb7VHB3kTyOrltaCk=; b=cTinJ/6s+Qw6jY2NapB2sj66JEe0Bw2SO/yUAAIdhYV+3r8vMDyqmtv52WjMyrwbDt orbgj5lHkM1MbhOqPOl9ILAYzfOXN4OC60PumUjjRy1v0V/FoFlG5EjEiLqi/J+FpU1m 46C+hfRInoPUQSwFOpYTAg9Wk+ZKSP5roUDXaeUVTOZ5PIWPXGqvXi8yCx53oKawtoyh 5LWUP/SMlrRdD5Yi5mqM2KVqWkmQkrDcw/yzYvXrVQWkiemgto/wDWvUCSEB4CV6H3hh 7AP0/2nilaNBBCOSkJQXdBDXxlUq2rIZFUGs5/+DjrQqAgcdkHPE84ARvjSz6mnkEKMR Gk0w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m7si10076739qvq.39.2018.11.12.09.26.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:26:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49866 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFyi-0001ZY-J0 for patch@linaro.org; Mon, 12 Nov 2018 12:26:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhq-00041G-9k for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhp-0000ew-8E for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:58 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFho-0008MG-Sl for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:57 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhP-0005t7-2b for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:31 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:11 +0000 Message-Id: <20181112170816.500-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/16] arm: fix aa64_generate_debug_exceptions to work with EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée The test was incomplete and incorrectly caused debug exceptions to be generated when returning to EL2 after a failed attempt to single-step an EL1 instruction. Fix this while cleaning up the function a little. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-8-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) -- 2.19.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1efff21a18d..814ff69bc22 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2764,23 +2764,35 @@ static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; } +/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ static inline bool aa64_generate_debug_exceptions(CPUARMState *env) { - if (arm_is_secure(env)) { - /* MDCR_EL3.SDD disables debug events from Secure state */ - if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 - || arm_current_el(env) == 3) { - return false; - } + int cur_el = arm_current_el(env); + int debug_el; + + if (cur_el == 3) { + return false; } - if (arm_current_el(env) == arm_debug_target_el(env)) { - if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) - || (env->daif & PSTATE_D)) { - return false; - } + /* MDCR_EL3.SDD disables debug events from Secure state */ + if (arm_is_secure_below_el3(env) + && extract32(env->cp15.mdcr_el3, 16, 1)) { + return false; } - return true; + + /* + * Same EL to same EL debug exceptions need MDSCR_KDE enabled + * while not masking the (D)ebug bit in DAIF. + */ + debug_el = arm_debug_target_el(env); + + if (cur_el == debug_el) { + return extract32(env->cp15.mdscr_el1, 13, 1) + && !(env->daif & PSTATE_D); + } + + /* Otherwise the debug target needs to be a higher EL */ + return debug_el > cur_el; } static inline bool aa32_generate_debug_exceptions(CPUARMState *env) @@ -2833,9 +2845,6 @@ static inline bool aa32_generate_debug_exceptions(CPUARMState *env) * since the pseudocode has it at all callsites except for the one in * CheckSoftwareStep(), where it is elided because both branches would * always return the same value. - * - * Parts of the pseudocode relating to EL2 and EL3 are omitted because we - * don't yet implement those exception levels or their associated trap bits. */ static inline bool arm_generate_debug_exceptions(CPUARMState *env) { From patchwork Mon Nov 12 17:08:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150859 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3400030ljp; Mon, 12 Nov 2018 09:22:43 -0800 (PST) X-Google-Smtp-Source: AJdET5cVctLOW/5Z0bXjKY5DWNC6e2d68aJrLe5lwPN/X7SVrnbRT1n7t5lUlg+J51VKI8M7BmV7 X-Received: by 2002:ac8:3a64:: with SMTP id w91mr1799914qte.70.1542043363836; Mon, 12 Nov 2018 09:22:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043363; cv=none; d=google.com; s=arc-20160816; b=duc87Q6vhtia6cZCNHcjBirelFGMEAhovEH+cRuW39OCI/0mBaMFzK4GXIE+QFJi8B NougFg05cx8IE2zSb6X8FZVGshGp6z+AK1sQMNHOuhIiq4pIyuGyJstugFNUL7sZ59Am 4I6UpXnPntR6ErgOAmhTpy2Y9NuKDGrWT481MBsmYAWuf7xlQV0rlMCBecA9T5w8Y2AJ emCMSWmCbLH0QwqDxwDco46spyDji3s+rVsqQYeKVaEJ7w1pH3tN4rlt6BjgPp/CYpRs lGg5Q9ud2ZpMlJjrYCL8Zj3MxZ2D1nirBEwAQhThgGWEdnq8brHaHaoVP1VhKbPiJGCh Otlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=Nye1PZYWVGS3twGt3MvIwbd3aYIVQ2uk4O8Jfcx8NeY=; b=ditnz75RvsDBhKRe5M5mIOeddfTCBzS4JXtaFpWlSVcXgL1nFUfUv1JgkMN0DlHWvd sdN6ywMRe6kr9vKY9EkXSRWDDR97IwIwACBjpJZLag+MQMgdkb4KqvNwBEgdHwv+ZWH7 g1yewWqNZdcSAGDAkpWPbGDzSQaIQpBholZm4SUuDCRG4eOJDCWjI64SWk7IcFkfKxrb cJZzMQIO0d3zaNp9zZo9hr84BxnPiuHO/eGEJbWrBtunvbOZfx6tdr4KuOpFglG6RgZk YPN9LNsd0Z0MJ2tPum6vf0jkS+C8YpjeAjzKL4qe8B4Rrw5MWmNFSk+RVUO4mwmPqM7E i2jA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id v20si833456qvc.134.2018.11.12.09.22.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:22:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49841 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFv6-00079G-LD for patch@linaro.org; Mon, 12 Nov 2018 12:22:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhp-00040C-Al for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFho-0000e4-4w for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:57 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhn-0008MG-S4 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:56 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhP-0005tL-Vc for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:31 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:12 +0000 Message-Id: <20181112170816.500-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/16] Revert "target/arm: Implement HCR.VI and VF" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This reverts commit 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f. The implementation of HCR.VI and VF in that commit is not correct -- they do not track the overall "is there a pending VIRQ or VFIQ" status, but whether there is a pending interrupt due to "this mechanism", ie the hypervisor having set the VI/VF bits. The overall pending state for VIRQ and VFIQ is effectively the logical OR of the inbound lines from the GIC with the VI and VF bits. Commit 8a0fc3a29fc231 would result in pending VIRQ/VFIQ possibly being lost when the hypervisor wrote to HCR. As a preliminary to implementing the HCR.VI/VF feature properly, revert the broken one entirely. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20181109134731.11605-2-peter.maydell@linaro.org --- target/arm/helper.c | 47 ++++----------------------------------------- 1 file changed, 4 insertions(+), 43 deletions(-) -- 2.19.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index d167bc5deff..3c0c485a3a3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3931,7 +3931,6 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = ENV_GET_CPU(env); uint64_t valid_mask = HCR_MASK; if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -3950,28 +3949,6 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* Clear RES0 bits. */ value &= valid_mask; - /* - * VI and VF are kept in cs->interrupt_request. Modifying that - * requires that we have the iothread lock, which is done by - * marking the reginfo structs as ARM_CP_IO. - * Note that if a write to HCR pends a VIRQ or VFIQ it is never - * possible for it to be taken immediately, because VIRQ and - * VFIQ are masked unless running at EL0 or EL1, and HCR - * can only be written at EL2. - */ - g_assert(qemu_mutex_iothread_locked()); - if (value & HCR_VI) { - cs->interrupt_request |= CPU_INTERRUPT_VIRQ; - } else { - cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; - } - if (value & HCR_VF) { - cs->interrupt_request |= CPU_INTERRUPT_VFIQ; - } else { - cs->interrupt_request &= ~CPU_INTERRUPT_VFIQ; - } - value &= ~(HCR_VI | HCR_VF); - /* These bits change the MMU setup: * HCR_VM enables stage 2 translation * HCR_PTW forbids certain page-table setups @@ -3999,32 +3976,16 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, hcr_write(env, NULL, value); } -static uint64_t hcr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* The VI and VF bits live in cs->interrupt_request */ - uint64_t ret = env->cp15.hcr_el2 & ~(HCR_VI | HCR_VF); - CPUState *cs = ENV_GET_CPU(env); - - if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { - ret |= HCR_VI; - } - if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { - ret |= HCR_VF; - } - return ret; -} - static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, - .type = ARM_CP_IO, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_write, .readfn = hcr_read }, + .writefn = hcr_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_writelow, .readfn = hcr_read }, + .writefn = hcr_writelow }, { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, @@ -4261,7 +4222,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { static const ARMCPRegInfo el2_v8_cp_reginfo[] = { { .name = "HCR2", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, .access = PL2_RW, .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), From patchwork Mon Nov 12 17:08:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150863 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3402989ljp; Mon, 12 Nov 2018 09:25:47 -0800 (PST) X-Google-Smtp-Source: AJdET5ezYHG0OgKBb/ucNLnvJOsTaNXSNLsdBxO/4gokY21GgS1LmFVnkUGmKE0nFk0MS9pEAeyb X-Received: by 2002:ac8:c84:: with SMTP id n4-v6mr1766324qti.192.1542043547126; Mon, 12 Nov 2018 09:25:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043547; cv=none; d=google.com; s=arc-20160816; b=yBjEp8esBDrZS8zZ3i8lVG1w+I7rYcAUNCFxCqfEWkfYO7HH/Zk0YURJE3jO9M30iD 89+BcyK5fxYmS0giZC5FxgXcirwMviShmTwh+aAZtHoyf6qybYFm5to9AXeGf06kEzoT l1SNzCSpIXkqZpefz4j/2eXa841/rkNotMwBqFwZ3Q/tW8V/7qiRr8XkIoevjX72rJ0n AHIPJcOg1/eQR0jC5yGoQbSrdCOF4t8a4liVs+TkHE8jPhkvL4ao8mRsC161Kd1sgqqU oIuS/7giX1vP65DI+nl2KkEq27G/bz1BtM8d3HpqKWTJsl2PNUJCSyeJxYrC/cmzdZdz JlkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=bvP8R5MAoL/+E5kadJCpP8Euy+atui48kXpGC+1xQBE=; b=eiIcudut7CSczVmgegx7WVcwJyI7Y13rwmbPCEjNjeKLIRc9LMBbVzNjCv5vlzwk8y vGi56nXTgBubtggSJ1D2gP3e8DC+c5xaLrvm/s77ryNe/cWQXJ/spaHyNe7lpaH0WAJv 2ti59po6faCKkOoPM93q29HXae6Gq53lNt6AP1OeYw07tO1OVJjamPoboFA9PlbDE0VG Hs/ht/Ke6LkSzYYIUi3E+8KgQAJ3WADyO39XvsngD6TvbELOsPC5uZSHXATIrSnVX2Dd K9aY4DWWEWQSxNscHScnvnM03WSxE/UFPqLhQXS+zJkDzfv2O9+h3Ka3yAQTlLTjFnvU BItg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id u28si2267288qtj.69.2018.11.12.09.25.46 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:25:47 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49864 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFy6-0001KC-CD for patch@linaro.org; Mon, 12 Nov 2018 12:25:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60529) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFho-0003zP-K5 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhn-0000dH-4l for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:56 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhm-0008MG-R8 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:55 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhQ-0005tZ-SI for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:32 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:13 +0000 Message-Id: <20181112170816.500-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/16] target/arm: Track the state of our irq lines from the GIC explicitly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently we track the state of the four irq lines from the GIC only via the cs->interrupt_request or KVM irq state. That means that we assume that an interrupt is asserted if and only if the external line is set. This assumption is incorrect for VIRQ and VFIQ, because the HCR_EL2.{VI,VF} bits allow assertion of VIRQ and VFIQ separately from the state of the external line. To handle this, start tracking the state of the external lines explicitly in a CPU state struct field, as is common practice for devices. The complicated part of this is dealing with inbound migration from an older QEMU which didn't have this state. We assume in that case that the older QEMU did not implement the HCR_EL2.{VI,VF} bits as generating interrupts, and so the line state matches the current state in cs->interrupt_request. (This is not quite true between commit 8a0fc3a29fc2315325400c7 and its revert, but that commit is broken and never made it into any released QEMU version.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20181109134731.11605-3-peter.maydell@linaro.org --- target/arm/cpu.h | 3 +++ target/arm/cpu.c | 16 ++++++++++++++ target/arm/machine.c | 51 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) -- 2.19.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 814ff69bc22..2a73fed9a01 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -538,6 +538,9 @@ typedef struct CPUARMState { uint64_t esr; } serror; + /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ + uint32_t irq_line_state; + /* Thumb-2 EE state. */ uint32_t teecr; uint32_t teehbr; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 784a4c2dfcc..45c16ae90ba 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -449,6 +449,12 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ }; + if (level) { + env->irq_line_state |= mask[irq]; + } else { + env->irq_line_state &= ~mask[irq]; + } + switch (irq) { case ARM_CPU_VIRQ: case ARM_CPU_VFIQ: @@ -473,17 +479,27 @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) ARMCPU *cpu = opaque; CPUState *cs = CPU(cpu); int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; + uint32_t linestate_bit; switch (irq) { case ARM_CPU_IRQ: kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; + linestate_bit = CPU_INTERRUPT_HARD; break; case ARM_CPU_FIQ: kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; + linestate_bit = CPU_INTERRUPT_FIQ; break; default: g_assert_not_reached(); } + + if (level) { + env->irq_line_state |= linestate_bit; + } else { + env->irq_line_state &= ~linestate_bit; + } + kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); #endif diff --git a/target/arm/machine.c b/target/arm/machine.c index 239fe4e84d1..2033816a64e 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -192,6 +192,22 @@ static const VMStateDescription vmstate_serror = { } }; +static bool irq_line_state_needed(void *opaque) +{ + return true; +} + +static const VMStateDescription vmstate_irq_line_state = { + .name = "cpu/irq-line-state", + .version_id = 1, + .minimum_version_id = 1, + .needed = irq_line_state_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.irq_line_state, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static bool m_needed(void *opaque) { ARMCPU *cpu = opaque; @@ -625,11 +641,44 @@ static int cpu_pre_save(void *opaque) return 0; } +static int cpu_pre_load(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + /* + * Pre-initialize irq_line_state to a value that's never valid as + * real data, so cpu_post_load() can tell whether we've seen the + * irq-line-state subsection in the incoming migration state. + */ + env->irq_line_state = UINT32_MAX; + + return 0; +} + static int cpu_post_load(void *opaque, int version_id) { ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; int i, v; + /* + * Handle migration compatibility from old QEMU which didn't + * send the irq-line-state subsection. A QEMU without it did not + * implement the HCR_EL2.{VI,VF} bits as generating interrupts, + * so for TCG the line state matches the bits set in cs->interrupt_request. + * For KVM the line state is not stored in cs->interrupt_request + * and so this will leave irq_line_state as 0, but this is OK because + * we only need to care about it for TCG. + */ + if (env->irq_line_state == UINT32_MAX) { + CPUState *cs = CPU(cpu); + + env->irq_line_state = cs->interrupt_request & + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ | + CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VFIQ); + } + /* Update the values list from the incoming migration data. * Anything in the incoming data which we don't know about is * a migration failure; anything we know about but the incoming @@ -680,6 +729,7 @@ const VMStateDescription vmstate_arm_cpu = { .version_id = 22, .minimum_version_id = 22, .pre_save = cpu_pre_save, + .pre_load = cpu_pre_load, .post_load = cpu_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), @@ -747,6 +797,7 @@ const VMStateDescription vmstate_arm_cpu = { &vmstate_sve, #endif &vmstate_serror, + &vmstate_irq_line_state, NULL } }; From patchwork Mon Nov 12 17:08:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150858 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3399489ljp; Mon, 12 Nov 2018 09:22:13 -0800 (PST) X-Google-Smtp-Source: AJdET5eprC4F9ovCQBiLBNH7JdLJcbFGHS7JnzlxQZ2IT25B9jvKr0e3IMVKmVJgca+YyjEom0Ir X-Received: by 2002:a37:6d44:: with SMTP id i65mr1691296qkc.73.1542043333724; Mon, 12 Nov 2018 09:22:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043333; cv=none; d=google.com; s=arc-20160816; b=0/EZPM9vBXCZUriKHOLEyMS2AYu+2VdbkJRhJ1msomX5zO8T7IwJNx3PWDnktKZJGa oZZBA2iFjGguj+HRCycLZM6Vv2GuHthNlgi78dcw2Nc8uEgIBiy7/8emFI4xIGu6Vj/L MdtoGHW4fhEi/LwO+qimuKvx2Cn2nDUBPUn96/oh/XclTlcUN+3IWZn1d7nIKu1eV75k FWYvJfvV3sHOiIUE0o1PfzDuPiGLUEvL/BjuNaeS3QSwObo22HIjfqXk2XFVmIMpEj/6 aismZ4QQhglSiK8GInUljUNGOEi5pyTDy1r2mAxxkWkf0jG6KgJCRPVHS0ZDSygT1UhC 5WDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=gbsNsL+WA5EGVXIySWXONbvKNPoVU3Tm0OM5F7J61O4=; b=RQrWY0jY9bYCXAnrPX4wNEw23+XkEOtHpnj14cTh4p7UNJr6GrF/RfLJ3cuA4FHaTL 6dAkzfzo+957XhZbsh0AgtplFdXJvsOmT+pOmtNsM33DU0ifUx0dtJijVTOYvr/uPXnf nQcrIyzSxpgD1Ic/0yhJisJKtW697/VnxseQBdZqU3Ydfggak6r0zD+0PVDw6ifGPtVE MDbuEM+K8ZLvzAn3BrTrtUjheLoO/Hr17ltmHJ1m2gdIw4JjCXGBqN6G40aAbnrYDXnE ag97tf5cFryJq4Zv10QxZLu6UhNjKk6HslrMa1uMRKLcNCGMfX3W5lMG9PiDKH6HL2mM F+kw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o14si8182872qtr.110.2018.11.12.09.22.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:22:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49840 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFuf-00074y-0g for patch@linaro.org; Mon, 12 Nov 2018 12:22:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhn-0003xw-6A for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhm-0000cY-3N for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:55 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhl-0008MG-Qg for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:54 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhR-0005tn-Of for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:33 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:14 +0000 Message-Id: <20181112170816.500-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/16] target/arm: Correctly implement handling of HCR_EL2.{VI, VF} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In commit 8a0fc3a29fc2315325400 we tried to implement HCR_EL2.{VI,VF}, but we got it wrong and had to revert it. In that commit we implemented them as simply tracking whether there is a pending virtual IRQ or virtual FIQ. This is not correct -- these bits cause a software-generated VIRQ/VFIQ, which is distinct from whether there is a hardware-generated VIRQ/VFIQ caused by the external interrupt controller. So we need to track separately the HCR_EL2 bit state and the external virq/vfiq line state, and OR the two together to get the actual pending VIRQ/VFIQ state. Fixes: 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181109134731.11605-4-peter.maydell@linaro.org --- target/arm/internals.h | 18 ++++++++++++++++ target/arm/cpu.c | 48 +++++++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 20 ++++++++++++++++-- 3 files changed, 83 insertions(+), 3 deletions(-) -- 2.19.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c2bb2deebd..a32d359dd03 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -871,4 +871,22 @@ static inline const char *aarch32_mode_name(uint32_t psr) return cpu_mode_names[psr & 0xf]; } +/** + * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request + * + * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following + * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. + * Must be called with the iothread lock held. + */ +void arm_cpu_update_virq(ARMCPU *cpu); + +/** + * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request + * + * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following + * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. + * Must be called with the iothread lock held. + */ +void arm_cpu_update_vfiq(ARMCPU *cpu); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 45c16ae90ba..6fbea4dc88c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -436,6 +436,48 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } #endif +void arm_cpu_update_virq(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VIRQ, which is the logical OR of + * the HCR_EL2.VI bit and the input line level from the GIC. + */ + CPUARMState *env = &cpu->env; + CPUState *cs = CPU(cpu); + + bool new_state = (env->cp15.hcr_el2 & HCR_VI) || + (env->irq_line_state & CPU_INTERRUPT_VIRQ); + + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); + } + } +} + +void arm_cpu_update_vfiq(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VFIQ, which is the logical OR of + * the HCR_EL2.VF bit and the input line level from the GIC. + */ + CPUARMState *env = &cpu->env; + CPUState *cs = CPU(cpu); + + bool new_state = (env->cp15.hcr_el2 & HCR_VF) || + (env->irq_line_state & CPU_INTERRUPT_VFIQ); + + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); + } + } +} + #ifndef CONFIG_USER_ONLY static void arm_cpu_set_irq(void *opaque, int irq, int level) { @@ -457,9 +499,13 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) switch (irq) { case ARM_CPU_VIRQ: + assert(arm_feature(env, ARM_FEATURE_EL2)); + arm_cpu_update_virq(cpu); + break; case ARM_CPU_VFIQ: assert(arm_feature(env, ARM_FEATURE_EL2)); - /* fall through */ + arm_cpu_update_vfiq(cpu); + break; case ARM_CPU_IRQ: case ARM_CPU_FIQ: if (level) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 3c0c485a3a3..0ebe4d1b4ad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3958,6 +3958,21 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) tlb_flush(CPU(cpu)); } env->cp15.hcr_el2 = value; + + /* + * Updates to VI and VF require us to update the status of + * virtual interrupts, which are the logical OR of these bits + * and the state of the input lines from the GIC. (This requires + * that we have the iothread lock, which is done by marking the + * reginfo structs as ARM_CP_IO.) + * Note that if a write to HCR pends a VIRQ or VFIQ it is never + * possible for it to be taken immediately, because VIRQ and + * VFIQ are masked unless running at EL0 or EL1, and HCR + * can only be written at EL2. + */ + g_assert(qemu_mutex_iothread_locked()); + arm_cpu_update_virq(cpu); + arm_cpu_update_vfiq(cpu); } static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3978,11 +3993,12 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_IO, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), .writefn = hcr_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS, + .type = ARM_CP_ALIAS | ARM_CP_IO, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), .writefn = hcr_writelow }, @@ -4222,7 +4238,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { static const ARMCPRegInfo el2_v8_cp_reginfo[] = { { .name = "HCR2", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS, + .type = ARM_CP_ALIAS | ARM_CP_IO, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, .access = PL2_RW, .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), From patchwork Mon Nov 12 17:08:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150861 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3400273ljp; Mon, 12 Nov 2018 09:23:00 -0800 (PST) X-Google-Smtp-Source: AJdET5dBua3Kv7cqKh+IDyw5YFaZGH6als1MGmHroBdeZb7vYUkz75I0FQLyZ0ZKnWXEkHsjWsC7 X-Received: by 2002:a0c:dd81:: with SMTP id v1mr1862416qvk.71.1542043380774; Mon, 12 Nov 2018 09:23:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043380; cv=none; d=google.com; s=arc-20160816; b=fpEBVmrCRYfoPXLYEuGJslfbtq7iwSO288WHLs0cj3Ipop6vayzNvjbP2FYkJQEnkd JCrfAnBb3yMenFZTSUNozqetht25ZRQwkNkL2iqrQdxvjVi97owV5NxWGQBm2afeQUF8 oleeVHS8TFkM57AIEN9ofsjkTOAui2cVKNsVP5h/57AJLfAIYm/ciqsawg6Nl2Be98/c o8d1B5dxllpN+GNGNcr4GaneKQLfdQymE9gUMPqy83uBOgMkoRNVWzqWtNTz7n0dNQVI W2qmpjYNtR49wRxoy12Sl+zT0wqtI/wMvnK7+zqMTfAQT7HjIFrmI2Am8M1dj+FlJmZ7 /I6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=H3BaPJjIlIpjHmEbpTFHtiJq7U1ZwVP+n8dXNKtUmco=; b=VLcMUoDZw8Qj5zz/UJeZAji6v4BzrBz80o6XVKKH+9AcsMUv0KIy9j6sR1f7d7P1IM bujYsQeJaRENFoTdxB5Diqec5SDvLJpOS9T66GoOP0Zd8x+8SVZFeZzM8feDaAyKN/CU i7gZ6yKZ2vfNw1AGAwPkofusbfwwdKuH0w9qBwKfo2dX7ouvnrLRckoQdimo8RTZ+8sK QvzbEgboJ08bXy/c4ZgiLQ5kV9iZQQioOUmrpmOVwXGypfDRxoJ/SG80gYdezWTeKbsV GXvGreldXEq1ag+5sdNWhuXu2hfOJalbKb/Ju90FV+Kwy/YbPpmTPhOvDdYt1i79TgOv 3uHw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id y13si5439761qti.151.2018.11.12.09.23.00 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:23:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49845 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFvP-0007cg-IN for patch@linaro.org; Mon, 12 Nov 2018 12:22:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60483) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhm-0003xW-Mq for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhl-0000bc-49 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:54 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhk-0008MG-Od for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:53 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhS-0005u1-L4 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:34 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:15 +0000 Message-Id: <20181112170816.500-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/16] target/arm: Hyp mode R14 is shared with User and System X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hyp mode is an exception to the general rule that each AArch32 mode has its own r13, r14 and SPSR -- it has a banked r13 and SPSR but shares its r14 with User and System mode. We were incorrectly implementing it as banked, which meant that on entry to Hyp mode r14 was 0 rather than the USR/SYS r14. We provide a new function r14_bank_number() which is like the existing bank_number() but provides the index into env->banked_r14[]; bank_number() provides the index to use for env->banked_r13[] and env->banked_cpsr[]. All the points in the code that were using bank_number() to index into env->banked_r14[] are updated for consintency: * switch_mode() -- this is the only place where we fix an actual bug * aarch64_sync_32_to_64() and aarch64_sync_64_to_32(): no behavioural change as we already special-cased Hyp R14 * kvm32.c: no behavioural change since the guest can't ever be in Hyp mode, but conceptually the right thing to do * msr_banked()/mrs_banked(): we can never get to the case that accesses banked_r14[] with tgtmode == ARM_CPU_MODE_HYP, so no behavioural change Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée Message-id: 20181109173553.22341-2-peter.maydell@linaro.org --- target/arm/internals.h | 16 ++++++++++++++++ target/arm/helper.c | 29 +++++++++++++++-------------- target/arm/kvm32.c | 4 ++-- target/arm/op_helper.c | 4 ++-- 4 files changed, 35 insertions(+), 18 deletions(-) -- 2.19.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index a32d359dd03..d208b70a64f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -145,6 +145,22 @@ static inline int bank_number(int mode) g_assert_not_reached(); } +/** + * r14_bank_number: Map CPU mode onto register bank for r14 + * + * Given an AArch32 CPU mode, return the index into the saved register + * banks to use for the R14 (LR) in that mode. This is the same as + * bank_number(), except for the special case of Hyp mode, where + * R14 is shared with USR and SYS, unlike its R13 and SPSR. + * This should be used as the index into env->banked_r14[], and + * bank_number() used for the index into env->banked_r13[] and + * env->banked_spsr[]. + */ +static inline int r14_bank_number(int mode) +{ + return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); +} + void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ebe4d1b4ad..0da1424f72d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6432,13 +6432,14 @@ static void switch_mode(CPUARMState *env, int mode) i = bank_number(old_mode); env->banked_r13[i] = env->regs[13]; - env->banked_r14[i] = env->regs[14]; env->banked_spsr[i] = env->spsr; i = bank_number(mode); env->regs[13] = env->banked_r13[i]; - env->regs[14] = env->banked_r14[i]; env->spsr = env->banked_spsr[i]; + + env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; + env->regs[14] = env->banked_r14[r14_bank_number(mode)]; } /* Physical Interrupt Target EL Lookup Table @@ -8017,7 +8018,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) if (mode == ARM_CPU_MODE_HYP) { env->xregs[14] = env->regs[14]; } else { - env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; + env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; } } @@ -8031,7 +8032,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[16] = env->regs[14]; env->xregs[17] = env->regs[13]; } else { - env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; + env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; } @@ -8039,7 +8040,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[18] = env->regs[14]; env->xregs[19] = env->regs[13]; } else { - env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; + env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; } @@ -8047,7 +8048,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[20] = env->regs[14]; env->xregs[21] = env->regs[13]; } else { - env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; + env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; } @@ -8055,7 +8056,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[22] = env->regs[14]; env->xregs[23] = env->regs[13]; } else { - env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; + env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; } @@ -8072,7 +8073,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[i] = env->fiq_regs[i - 24]; } env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; - env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; + env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; } env->pc = env->regs[15]; @@ -8122,7 +8123,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) if (mode == ARM_CPU_MODE_HYP) { env->regs[14] = env->xregs[14]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; } } @@ -8136,7 +8137,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] = env->xregs[16]; env->regs[13] = env->xregs[17]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; } @@ -8144,7 +8145,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] = env->xregs[18]; env->regs[13] = env->xregs[19]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; } @@ -8152,7 +8153,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] = env->xregs[20]; env->regs[13] = env->xregs[21]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; } @@ -8160,7 +8161,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] = env->xregs[22]; env->regs[13] = env->xregs[23]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; } @@ -8177,7 +8178,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->fiq_regs[i - 24] = env->xregs[i]; } env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; - env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; } env->regs[15] = env->pc; diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 0f1e94c7b5e..cb3fb73a961 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -318,8 +318,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); } env->banked_r13[bn] = env->regs[13]; - env->banked_r14[bn] = env->regs[14]; env->banked_spsr[bn] = env->spsr; + env->banked_r14[r14_bank_number(mode)] = env->regs[14]; /* Now we can safely copy stuff down to the kernel */ for (i = 0; i < ARRAY_SIZE(regs); i++) { @@ -430,8 +430,8 @@ int kvm_arch_get_registers(CPUState *cs) memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); } env->regs[13] = env->banked_r13[bn]; - env->regs[14] = env->banked_r14[bn]; env->spsr = env->banked_spsr[bn]; + env->regs[14] = env->banked_r14[r14_bank_number(mode)]; /* VFP registers */ r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 90741f6331d..eb6fb82fb81 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -694,7 +694,7 @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode, env->banked_r13[bank_number(tgtmode)] = value; break; case 14: - env->banked_r14[bank_number(tgtmode)] = value; + env->banked_r14[r14_bank_number(tgtmode)] = value; break; case 8 ... 12: switch (tgtmode) { @@ -725,7 +725,7 @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno) case 13: return env->banked_r13[bank_number(tgtmode)]; case 14: - return env->banked_r14[bank_number(tgtmode)]; + return env->banked_r14[r14_bank_number(tgtmode)]; case 8 ... 12: switch (tgtmode) { case ARM_CPU_MODE_USR: From patchwork Mon Nov 12 17:08:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150856 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3394796ljp; Mon, 12 Nov 2018 09:17:52 -0800 (PST) X-Google-Smtp-Source: AJdET5dCCvK4Mv+7wOB2ArRCCGvZelvRZXtqnMUluiA9MOF53KTCTzwOukP4KkbOdsS2YQAJlE8I X-Received: by 2002:aed:35c5:: with SMTP id d5mr1737051qte.212.1542043072209; Mon, 12 Nov 2018 09:17:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542043072; cv=none; d=google.com; s=arc-20160816; b=zUv3jrlqYBDmmKnpEllhh1iqca4m76dGJZ8EOKhB0Pp5LGy9oX7SPXnF3W3Yz2AuGv gkKVTMWb2VrVmcvkSSIOOH6y27IBlW0De6kvxbAWRWlsYkn9KW97sZPkNfmkGjP4A7Gn c5cxIhFqD71s63DgBClYYVU03RKVpxvEJQl63FGG/yXjbwO19FML6GA2sYGpCqKJZoEW TauLAvaLzUwF/2a45PULnR+FPKAbdvjO2JC0SQnPHW9C8j7MjW7xHeo+QFcMBKB/E5ey iqTWFatD4+ooX7O+wC19oDUTqNbLNZyKvrxG+FEVZvEFkH2rdfjEpPjoennv6Yd441aE 6c4g== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id z64si1935929qkd.17.2018.11.12.09.17.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Nov 2018 09:17:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49812 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFqR-0003lJ-Ga for patch@linaro.org; Mon, 12 Nov 2018 12:17:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60449) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhk-0003vW-My for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhj-0000a4-Vd for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:52 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFhj-0008MG-NB for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:08:51 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhT-0005uF-HP for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:35 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:16 +0000 Message-Id: <20181112170816.500-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/16] target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The Cortex-A15 and Cortex-A7 both have EL2; now we've implemented it properly we can enable the feature bit. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Message-id: 20181109173553.22341-3-peter.maydell@linaro.org --- target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.19.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6fbea4dc88c..f4efda0a00c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1649,6 +1649,7 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; cpu->midr = 0x410fc075; @@ -1695,6 +1696,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1;