From patchwork Sat Dec 18 14:02:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 525537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBE3BC433F5 for ; Sat, 18 Dec 2021 14:02:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233298AbhLROCd (ORCPT ); Sat, 18 Dec 2021 09:02:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233289AbhLROCd (ORCPT ); Sat, 18 Dec 2021 09:02:33 -0500 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9644CC061574 for ; Sat, 18 Dec 2021 06:02:32 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id p8so7875545ljo.5 for ; Sat, 18 Dec 2021 06:02:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lLa+tzwx7XxWdZm29gsG4pz/a1KbS3NQdHtzFc2AAO8=; b=rfLR9UhoD1kXauMze2WNNbu2j1vP5gugfjxcky6mdIP0EhZ3QPAonQQ2Rys9Wgrg85 l9pc+U+3kVP1SECQjhKHLUFE51jt1kdvuOh8KdMdXA/JThHGto7NRKNBiGwuUf6emzFm RH1L6Bu14O0J24zWHyEYLOTaQcqNuBDD3er5Boe9sVDEiuhauD/poy9hFcHRT9o2I8AX P0DiC1DXzvlBkqO3ShC+nBWQqIhZsu+4UtfPXXY9qDny+5EeKQ3/lNX/6ckhxos1ep9o 2cOPcykVt2Z/js1MmVB+pFiS3cOmojS5rCsOl5ishpJ4AUEAffnC6mznNxoh2972y4Ox C0Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lLa+tzwx7XxWdZm29gsG4pz/a1KbS3NQdHtzFc2AAO8=; b=HYwVB5a4/71bfGeDuXSZqtrJqFCtuzWutsW+OAY+iqeC88Zu1snQ89GBIJvMZARJU1 Ggcif7M5DzJ3FLka7rtWYpiaYOpr3GoPqQGeCp3cpGeFc7QJtumyFTcHaEqaFSDhhEMf MvQq4IwHu36cews9jl8uGgZWk10ddcR1cfLGDrw9Gew6ri18oBNXcRo+brmL3A7gycKW wkwEDCSAM/WTZ9RHU0Ba4LQb0UkpbF49TmgISv/E3vVZPdOW4Q9+IUJq7cK/UDFps0Se EtBrKrQieGxxiFMBML+4hps4m1nEuzk3eRlSZ5eyiCfgP+HLgKuMMOiXzACTquqNG3Tr 6TAw== X-Gm-Message-State: AOAM5314VEgvqwoA723x1VWRj6j9iSoELspk08IeVW0bFBOcH5ffesXW JhuFWLAQwuTfCEsxnWE+JuTmpg== X-Google-Smtp-Source: ABdhPJwym51zI53iwb5vIFxBsrnJAt0jWjaxaX6WkGLt41QOKPSZhc10vTJQiGwMV4+t6eF+dkDlIg== X-Received: by 2002:a05:651c:1987:: with SMTP id bx7mr6534651ljb.35.1639836150862; Sat, 18 Dec 2021 06:02:30 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id s15sm2023979ljj.14.2021.12.18.06.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Dec 2021 06:02:30 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Prasad Malisetty , Stephen Boyd Subject: [PATCH 1/3] PCI: qcom: Balance pm_runtime_foo() calls Date: Sat, 18 Dec 2021 17:02:21 +0300 Message-Id: <20211218140223.500390-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211218140223.500390-1-dmitry.baryshkov@linaro.org> References: <20211218140223.500390-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fix the error path in qcom_pcie_probe(): remove extra calls to pm_runtime_disable() (which will be called at the end of error path anyway). Replace a call to pm_runtime_get_sync() with pm_runtime_resume_and_get() to end up with cleaner code. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 1c3d1116bb60..3a0f126db5a3 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1543,9 +1543,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) return -ENOMEM; pm_runtime_enable(dev); - ret = pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); if (ret < 0) - goto err_pm_runtime_put; + goto err_pm_runtime_disable; pci->dev = dev; pci->ops = &dw_pcie_ops; @@ -1594,7 +1594,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) ret = phy_init(pcie->phy); if (ret) { - pm_runtime_disable(&pdev->dev); goto err_pm_runtime_put; } @@ -1603,7 +1602,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "cannot initialize host\n"); - pm_runtime_disable(&pdev->dev); goto err_pm_runtime_put; } @@ -1611,6 +1609,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) err_pm_runtime_put: pm_runtime_put(dev); +err_pm_runtime_disable: pm_runtime_disable(dev); return ret; From patchwork Sat Dec 18 14:02:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 525891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD106C43217 for ; Sat, 18 Dec 2021 14:02:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233302AbhLROCf (ORCPT ); Sat, 18 Dec 2021 09:02:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233288AbhLROCe (ORCPT ); Sat, 18 Dec 2021 09:02:34 -0500 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3083CC06173E for ; Sat, 18 Dec 2021 06:02:34 -0800 (PST) Received: by mail-lj1-x235.google.com with SMTP id k23so7905754lje.1 for ; Sat, 18 Dec 2021 06:02:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BUWOn5eKNvIwdyRJd4jzvmP+6dWkUCLvqOM8SxqkIyM=; b=tsAp9EC4yt0icJA1vkMGVuP0WwlhcOGskpBLiqd5jsetUctRDyBv+EHetdKdxtiXcv dybTcGCaYAeyv7mpk4JDYebPy12AUpPuzM9M7QthQCLRjhfkKsPmiLDp5abtognPG/tZ Op45u9mX4MsIQh9XSpZoYxvIM0uHOnSNodRFDiPhH6Btll2lfrgnWujQO952g5LAhgaM hGIPjj+mAuhcc7t9lmOjnro5k+fUrQRUs4OlBt9qHdwXP7UofOxmM/PYGQUkN41K2Cea xUb67LshATUebszpZfvvEB+jeZUMTwURJlMZoeR/FPOCVvHLoIE+Yc1hY6GqJUBOH7wA YXgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BUWOn5eKNvIwdyRJd4jzvmP+6dWkUCLvqOM8SxqkIyM=; b=X/tS+D5ECV+6shTIZsaC07AUpHewIS7/G0fcXb5G1U9eZSAAMTjY4VX0fTtGKwt6GA sBLdlUkjUV3Y63pGGdMHcjjum6EiC94ybXj3ClEQqdjxn6Q8ySQX4fC1SXOreZceadlA BMuXYDo4sP5yZY22b/Fp5V+0nRtEuFVP2XS+fbceRn2RaSVRh1u4+3lsZ5U6zLRGjsVA WHaRShGi9evbpNtExaFrP3UtNPMpyEPaO+ECR7pbZoJSL0DFr/9OdUkIfkGNTu/6HVcv PJ8V68eUABLL0FqMiE/OuqG2Fk7XZc3gg+ZrjElzCCrGcVjtnNSxc652Ae3RPPhBNzt8 1APQ== X-Gm-Message-State: AOAM5331O3ao3jI64mrgAp6uODozb4/gDsN74LuO4O7auppZYRIPQU27 IUb1KDy5yXq4qkKZdMjiLjrlP38S+68fXkLH X-Google-Smtp-Source: ABdhPJxa5Y86yQUN2Fufipjz0vjbyEDIcX5po2nVTgtoD41RSKvE6mdoGMQFOGk1yxOXdgaTipZLEg== X-Received: by 2002:a2e:a361:: with SMTP id i1mr6921365ljn.32.1639836152452; Sat, 18 Dec 2021 06:02:32 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id s15sm2023979ljj.14.2021.12.18.06.02.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Dec 2021 06:02:32 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Prasad Malisetty , Stephen Boyd Subject: [PATCH 2/3] PCI: qcom: Fix pipe_clk_src reparenting Date: Sat, 18 Dec 2021 17:02:22 +0300 Message-Id: <20211218140223.500390-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211218140223.500390-1-dmitry.baryshkov@linaro.org> References: <20211218140223.500390-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The hardware requires that pipe_clk_src is fed from TCXO when GDSC is disabled. It can be fed from PHY's pipe_clk once GDSC is enabled (which is what is done by the downstream driver). Currently code does all clk_set_parent() calls after the pm_runtime_get(), so the GDSC is already enabled. Implement these requirements by moving pm_runtime_*() calls after get_resources (so that get_resources() can ensure that the pipe clock parent is TCXO). Fixes: aa9c0df98c29 ("PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280") Cc: Prasad Malisetty Cc: Stephen Boyd Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 52 ++++++++++++-------------- 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 3a0f126db5a3..fbaae6f4eb18 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1188,6 +1188,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->ref_clk_src = devm_clk_get(dev, "ref"); if (IS_ERR(res->ref_clk_src)) return PTR_ERR(res->ref_clk_src); + + /* Ensure that the TCXO is a clock source for pcie_pipe_clk_src */ + clk_set_parent(res->pipe_clk_src, res->ref_clk_src); } res->pipe_clk = devm_clk_get(dev, "pipe"); @@ -1208,9 +1211,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - /* Set TCXO as clock source for pcie_pipe_clk_src */ + /* Set pipe clock as clock source for pcie_pipe_clk_src */ if (pcie->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->ref_clk_src); + clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) @@ -1276,6 +1279,11 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; clk_bulk_disable_unprepare(res->num_clks, res->clks); + + /* Set TCXO as clock source for pcie_pipe_clk_src */ + if (pcie->pipe_clk_need_muxing) + clk_set_parent(res->pipe_clk_src, res->ref_clk_src); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -1283,10 +1291,6 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - /* Set pipe clock as clock source for pcie_pipe_clk_src */ - if (pcie->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); - return clk_prepare_enable(res->pipe_clk); } @@ -1542,11 +1546,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) if (!pci) return -ENOMEM; - pm_runtime_enable(dev); - ret = pm_runtime_resume_and_get(dev); - if (ret < 0) - goto err_pm_runtime_disable; - pci->dev = dev; pci->ops = &dw_pcie_ops; pp = &pci->pp; @@ -1563,32 +1562,29 @@ static int qcom_pcie_probe(struct platform_device *pdev) pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing; pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); - if (IS_ERR(pcie->reset)) { - ret = PTR_ERR(pcie->reset); - goto err_pm_runtime_put; - } + if (IS_ERR(pcie->reset)) + return PTR_ERR(pcie->reset); pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); - if (IS_ERR(pcie->parf)) { - ret = PTR_ERR(pcie->parf); - goto err_pm_runtime_put; - } + if (IS_ERR(pcie->parf)) + return PTR_ERR(pcie->parf); pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); - if (IS_ERR(pcie->elbi)) { - ret = PTR_ERR(pcie->elbi); - goto err_pm_runtime_put; - } + if (IS_ERR(pcie->elbi)) + return PTR_ERR(pcie->elbi); pcie->phy = devm_phy_optional_get(dev, "pciephy"); - if (IS_ERR(pcie->phy)) { - ret = PTR_ERR(pcie->phy); - goto err_pm_runtime_put; - } + if (IS_ERR(pcie->phy)) + return PTR_ERR(pcie->phy); ret = pcie->ops->get_resources(pcie); if (ret) - goto err_pm_runtime_put; + return ret; + + pm_runtime_enable(dev); + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) + goto err_pm_runtime_disable; pp->ops = &qcom_pcie_dw_ops; From patchwork Sat Dec 18 14:02:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 525536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08862C433EF for ; Sat, 18 Dec 2021 14:02:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233308AbhLROCg (ORCPT ); Sat, 18 Dec 2021 09:02:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233288AbhLROCg (ORCPT ); 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Sat, 18 Dec 2021 06:02:33 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Prasad Malisetty , Stephen Boyd Subject: [PATCH 3/3] PCI: qcom: Remove unnecessary pipe_clk handling Date: Sat, 18 Dec 2021 17:02:23 +0300 Message-Id: <20211218140223.500390-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211218140223.500390-1-dmitry.baryshkov@linaro.org> References: <20211218140223.500390-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org QMP PHY driver already does clk_prepare_enable()/_disable() pipe_clk. Remove extra calls to enable/disable this clock from the PCIe driver, so that the PHY driver can manage the clock on its own. Fixes: aa9c0df98c29 ("PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280") Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 71 +------------------------- 1 file changed, 2 insertions(+), 69 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index fbaae6f4eb18..4e668da96ef4 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -128,7 +128,6 @@ struct qcom_pcie_resources_2_3_2 { struct clk *master_clk; struct clk *slave_clk; struct clk *cfg_clk; - struct clk *pipe_clk; struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; @@ -165,7 +164,6 @@ struct qcom_pcie_resources_2_7_0 { int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; - struct clk *pipe_clk; struct clk *pipe_clk_src; struct clk *phy_pipe_clk; struct clk *ref_clk_src; @@ -185,9 +183,7 @@ struct qcom_pcie; struct qcom_pcie_ops { int (*get_resources)(struct qcom_pcie *pcie); int (*init)(struct qcom_pcie *pcie); - int (*post_init)(struct qcom_pcie *pcie); void (*deinit)(struct qcom_pcie *pcie); - void (*post_deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); int (*config_sid)(struct qcom_pcie *pcie); }; @@ -591,11 +587,7 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) return PTR_ERR(res->master_clk); res->slave_clk = devm_clk_get(dev, "bus_slave"); - if (IS_ERR(res->slave_clk)) - return PTR_ERR(res->slave_clk); - - res->pipe_clk = devm_clk_get(dev, "pipe"); - return PTR_ERR_OR_ZERO(res->pipe_clk); + return PTR_ERR_OR_ZERO(res->slave_clk); } static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) @@ -610,13 +602,6 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } -static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - - clk_disable_unprepare(res->pipe_clk); -} - static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; @@ -691,22 +676,6 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) return ret; } -static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - struct dw_pcie *pci = pcie->pci; - struct device *dev = pci->dev; - int ret; - - ret = clk_prepare_enable(res->pipe_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable pipe clock\n"); - return ret; - } - - return 0; -} - static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; @@ -1193,8 +1162,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) clk_set_parent(res->pipe_clk_src, res->ref_clk_src); } - res->pipe_clk = devm_clk_get(dev, "pipe"); - return PTR_ERR_OR_ZERO(res->pipe_clk); + return 0; } static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) @@ -1233,12 +1201,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) goto err_disable_clocks; } - ret = clk_prepare_enable(res->pipe_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable pipe clock\n"); - goto err_disable_clocks; - } - /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); @@ -1287,20 +1249,6 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } -static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - - return clk_prepare_enable(res->pipe_clk); -} - -static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - - clk_disable_unprepare(res->pipe_clk); -} - static int qcom_pcie_link_up(struct dw_pcie *pci) { u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -1396,12 +1344,6 @@ static int qcom_pcie_host_init(struct pcie_port *pp) if (ret) goto err_deinit; - if (pcie->ops->post_init) { - ret = pcie->ops->post_init(pcie); - if (ret) - goto err_disable_phy; - } - qcom_ep_reset_deassert(pcie); if (pcie->ops->config_sid) { @@ -1414,9 +1356,6 @@ static int qcom_pcie_host_init(struct pcie_port *pp) err: qcom_ep_reset_assert(pcie); - if (pcie->ops->post_deinit) - pcie->ops->post_deinit(pcie); -err_disable_phy: phy_power_off(pcie->phy); err_deinit: pcie->ops->deinit(pcie); @@ -1448,9 +1387,7 @@ static const struct qcom_pcie_ops ops_1_0_0 = { static const struct qcom_pcie_ops ops_2_3_2 = { .get_resources = qcom_pcie_get_resources_2_3_2, .init = qcom_pcie_init_2_3_2, - .post_init = qcom_pcie_post_init_2_3_2, .deinit = qcom_pcie_deinit_2_3_2, - .post_deinit = qcom_pcie_post_deinit_2_3_2, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; @@ -1476,8 +1413,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, - .post_deinit = qcom_pcie_post_deinit_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1486,8 +1421,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, - .post_deinit = qcom_pcie_post_deinit_2_7_0, .config_sid = qcom_pcie_config_sid_sm8250, };