From patchwork Sat Dec 18 08:58:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaosheng Cui X-Patchwork-Id: 526241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42735C433FE for ; Sat, 18 Dec 2021 08:57:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232425AbhLRI5s (ORCPT ); Sat, 18 Dec 2021 03:57:48 -0500 Received: from szxga08-in.huawei.com ([45.249.212.255]:29139 "EHLO szxga08-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232382AbhLRI5r (ORCPT ); Sat, 18 Dec 2021 03:57:47 -0500 Received: from dggeme762-chm.china.huawei.com (unknown [172.30.72.54]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4JGKRP17jQz1DK5N; Sat, 18 Dec 2021 16:54:41 +0800 (CST) Received: from ubuntu1804.huawei.com (10.67.174.44) by dggeme762-chm.china.huawei.com (10.3.19.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.20; Sat, 18 Dec 2021 16:57:44 +0800 From: Gaosheng Cui To: , , , , , , , , , , CC: , , , , Subject: [PATCH -next 1/3] arm-soc: exynos: replace open coded VA->PA conversions Date: Sat, 18 Dec 2021 16:58:41 +0800 Message-ID: <20211218085843.212497-2-cuigaosheng1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20211218085843.212497-1-cuigaosheng1@huawei.com> References: <20211218085843.212497-1-cuigaosheng1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.174.44] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggeme762-chm.china.huawei.com (10.3.19.108) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Ard Biesheuvel This replaces a couple of open coded calculations to obtain the physical address of a far symbol with calls to the new adr_l etc macros. Signed-off-by: Ard Biesheuvel Signed-off-by: Gaosheng Cui --- arch/arm/mach-exynos/headsmp.S | 9 +-------- arch/arm/mach-exynos/sleep.S | 26 +++++--------------------- 2 files changed, 6 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S index 0ac2cb9a7355..be7cd0eebe1d 100644 --- a/arch/arm/mach-exynos/headsmp.S +++ b/arch/arm/mach-exynos/headsmp.S @@ -19,10 +19,7 @@ ENTRY(exynos4_secondary_startup) ARM_BE8(setend be) mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 + adr_l r6, exynos_pen_release pen: ldr r7, [r6] cmp r7, r0 bne pen @@ -33,7 +30,3 @@ pen: ldr r7, [r6] */ b secondary_startup ENDPROC(exynos4_secondary_startup) - - .align 2 -1: .long . - .long exynos_pen_release diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index ed93f91853b8..ed27515a4458 100644 --- a/arch/arm/mach-exynos/sleep.S +++ b/arch/arm/mach-exynos/sleep.S @@ -8,6 +8,7 @@ #include #include +#include #include #include "smc.h" @@ -54,19 +55,13 @@ ENTRY(exynos_cpu_resume_ns) cmp r0, r1 bne skip_cp15 - adr r0, _cp15_save_power - ldr r1, [r0] - ldr r1, [r0, r1] - adr r0, _cp15_save_diag - ldr r2, [r0] - ldr r2, [r0, r2] + ldr_l r1, cp15_save_power + ldr_l r2, cp15_save_diag mov r0, #SMC_CMD_C15RESUME dsb smc #0 #ifdef CONFIG_CACHE_L2X0 - adr r0, 1f - ldr r2, [r0] - add r0, r2, r0 + adr_l r0, l2x0_saved_regs /* Check that the address has been initialised. */ ldr r1, [r0, #L2X0_R_PHY_BASE] @@ -85,9 +80,7 @@ ENTRY(exynos_cpu_resume_ns) smc #0 /* Reload saved regs pointer because smc corrupts registers. */ - adr r0, 1f - ldr r2, [r0] - add r0, r2, r0 + adr_l r0, l2x0_saved_regs ldr r1, [r0, #L2X0_R_PWR_CTRL] ldr r2, [r0, #L2X0_R_AUX_CTRL] @@ -106,15 +99,6 @@ skip_cp15: b cpu_resume ENDPROC(exynos_cpu_resume_ns) - .align -_cp15_save_power: - .long cp15_save_power - . -_cp15_save_diag: - .long cp15_save_diag - . -#ifdef CONFIG_CACHE_L2X0 -1: .long l2x0_saved_regs - . -#endif /* CONFIG_CACHE_L2X0 */ - .data .align 2 .globl cp15_save_diag From patchwork Sat Dec 18 08:58:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaosheng Cui X-Patchwork-Id: 525757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1708C433F5 for ; Sat, 18 Dec 2021 08:57:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232401AbhLRI5r (ORCPT ); Sat, 18 Dec 2021 03:57:47 -0500 Received: from szxga02-in.huawei.com ([45.249.212.188]:28328 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232378AbhLRI5q (ORCPT ); Sat, 18 Dec 2021 03:57:46 -0500 Received: from dggeme762-chm.china.huawei.com (unknown [172.30.72.54]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4JGKVX3K2JzbjGm; Sat, 18 Dec 2021 16:57:24 +0800 (CST) Received: from ubuntu1804.huawei.com (10.67.174.44) by dggeme762-chm.china.huawei.com (10.3.19.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.20; Sat, 18 Dec 2021 16:57:44 +0800 From: Gaosheng Cui To: , , , , , , , , , , CC: , , , , Subject: [PATCH -next 2/3] arm-soc: mvebu: replace open coded VA->PA conversion Date: Sat, 18 Dec 2021 16:58:42 +0800 Message-ID: <20211218085843.212497-3-cuigaosheng1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20211218085843.212497-1-cuigaosheng1@huawei.com> References: <20211218085843.212497-1-cuigaosheng1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.174.44] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggeme762-chm.china.huawei.com (10.3.19.108) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Ard Biesheuvel This replaces an open coded calculation to obtain the physical address of a far symbol with a call to the new ldr_l etc macro. Signed-off-by: Ard Biesheuvel Signed-off-by: Gaosheng Cui --- arch/arm/mach-mvebu/coherency_ll.S | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S index a3a64bf97250..9ae65b1e9745 100644 --- a/arch/arm/mach-mvebu/coherency_ll.S +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -37,9 +37,7 @@ ENTRY(ll_get_coherency_base) * MMU is disabled, use the physical address of the coherency * base address, (or 0x0 if the coherency fabric is not mapped) */ - adr r1, 3f - ldr r3, [r1] - ldr r1, [r1, r3] + ldr_l r1, coherency_phys_base b 2f 1: /* @@ -155,7 +153,3 @@ ENTRY(ll_disable_coherency) dsb ret lr ENDPROC(ll_disable_coherency) - - .align 2 -3: - .long coherency_phys_base - . From patchwork Sat Dec 18 08:58:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaosheng Cui X-Patchwork-Id: 525756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 556AEC43217 for ; Sat, 18 Dec 2021 08:57:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232081AbhLRI5r (ORCPT ); Sat, 18 Dec 2021 03:57:47 -0500 Received: from szxga08-in.huawei.com ([45.249.212.255]:29140 "EHLO szxga08-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232389AbhLRI5q (ORCPT ); Sat, 18 Dec 2021 03:57:46 -0500 Received: from dggeme762-chm.china.huawei.com (unknown [172.30.72.57]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4JGKRP3lzxz1DK67; Sat, 18 Dec 2021 16:54:41 +0800 (CST) Received: from ubuntu1804.huawei.com (10.67.174.44) by dggeme762-chm.china.huawei.com (10.3.19.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.20; Sat, 18 Dec 2021 16:57:44 +0800 From: Gaosheng Cui To: , , , , , , , , , , CC: , , , , Subject: [PATCH -next 3/3] arm-soc: various: replace open coded VA->PA calculation Date: Sat, 18 Dec 2021 16:58:43 +0800 Message-ID: <20211218085843.212497-4-cuigaosheng1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20211218085843.212497-1-cuigaosheng1@huawei.com> References: <20211218085843.212497-1-cuigaosheng1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.174.44] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggeme762-chm.china.huawei.com (10.3.19.108) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Ard Biesheuvel This replaces a few copies of the open coded calculations of the physical address in the secondary startup code of a couple of platforms. This ensures these quantities are invariant under runtime relocation. Cc: Russell King Signed-off-by: Ard Biesheuvel Signed-off-by: Gaosheng Cui --- arch/arm/mach-spear/headsmp.S | 11 +++-------- arch/arm/plat-versatile/headsmp.S | 9 +-------- 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-spear/headsmp.S b/arch/arm/mach-spear/headsmp.S index 96f89436ccf6..32ffc75ff332 100644 --- a/arch/arm/mach-spear/headsmp.S +++ b/arch/arm/mach-spear/headsmp.S @@ -10,6 +10,8 @@ #include #include +#include + __INIT /* @@ -20,10 +22,7 @@ ENTRY(spear13xx_secondary_startup) mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 + adr_l r6, spear_pen_release pen: ldr r7, [r6] cmp r7, r0 bne pen @@ -37,8 +36,4 @@ pen: ldr r7, [r6] * should now contain the SVC stack for this core */ b secondary_startup - - .align -1: .long . - .long spear_pen_release ENDPROC(spear13xx_secondary_startup) diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S index 09d9fc30c8ca..cec71853b0b3 100644 --- a/arch/arm/plat-versatile/headsmp.S +++ b/arch/arm/plat-versatile/headsmp.S @@ -18,10 +18,7 @@ ENTRY(versatile_secondary_startup) ARM_BE8(setend be) mrc p15, 0, r0, c0, c0, 5 bic r0, #0xff000000 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 + adr_l r6, versatile_cpu_release pen: ldr r7, [r6] cmp r7, r0 bne pen @@ -31,8 +28,4 @@ pen: ldr r7, [r6] * should now contain the SVC stack for this core */ b secondary_startup - - .align -1: .long . - .long versatile_cpu_release ENDPROC(versatile_secondary_startup)