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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id l13sm3341748wrs.73.2022.01.08.18.47.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Jan 2022 18:47:02 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, mchehab@kernel.org, hverkuil@xs4all.nl, robert.foss@linaro.org Cc: jonathan@marek.ca, andrey.konovalov@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, jgrahsl@snap.com, hfink@snap.com, vladimir.zapolskiy@linaro.org, dmitry.baryshkov@linaro.org, bryan.odonoghue@linaro.org, devicetree@vger.kernel.org, robh@kernel.org Subject: [PATCH v2 1/8] media: dt-bindings: media: camss: Fixup vdda regulator descriptions sdm845 Date: Sun, 9 Jan 2022 02:49:03 +0000 Message-Id: <20220109024910.2041763-2-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220109024910.2041763-1-bryan.odonoghue@linaro.org> References: <20220109024910.2041763-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If we review the schematic for RB3 Thundercomm document Turbox-845 we see that the CAMSS CSI PHY has the same basic power-rail layout as UFS, PCIe and USB PHYs. We should therefore have two regulator declarations as is the case for UFS, PCIe and USB. Cc: devicetree@vger.kernel.org Cc: robh@kernel.org Signed-off-by: Bryan O'Donoghue --- .../bindings/media/qcom,sdm845-camss.yaml | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml index 9ca5dfa7f2260..ae0642b9ae5ec 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml @@ -203,9 +203,13 @@ properties: - const: vfe1 - const: vfe_lite - vdda-supply: + vdda-phy-supply: description: - Definition of the regulator used as analog power supply. + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. required: - clock-names @@ -217,7 +221,8 @@ required: - power-domains - reg - reg-names - - vdda-supply + - vdda-phy-supply + - vdda-pll-supply additionalProperties: false @@ -361,7 +366,8 @@ examples: "vfe1", "vfe_lite"; - vdda-supply = <®_2v8>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; ports { #address-cells = <1>;