From patchwork Mon Nov 19 01:01:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151440 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2057509ljp; Sun, 18 Nov 2018 17:00:33 -0800 (PST) X-Google-Smtp-Source: AJdET5dAt8l2yqBlS5Tqpn6mt/yTl7jICPptz01VJQejJRIhmmYdn0zcCCDxoVvCVSGbr5oytrc0 X-Received: by 2002:a17:902:8bca:: with SMTP id r10-v6mr19813823plo.199.1542589233122; Sun, 18 Nov 2018 17:00:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589233; cv=none; d=google.com; s=arc-20160816; b=EYBv0TMkOosKQXxhRhSPTirDo5QOywCDV5a9H7p3bFbKwAHGt9jtI5An8G1OiYE9ow /z3vzHB/x67R5iaKEooWbdy2Qauv6qO+gYRVoN41CldH+Tum2Ccwcf7T1d4HmLqfi9Sb RuoSi5CV6L1+uMbS+JMuTv3YFfDq/VaUxdix4exnswx0pJy5sZLikz0HglfQLy3GazLn eWkHSLDrsSfutYb2twO+aK7desIJx3uqLgyQHsn3WJdtLmzBQkfJiQamNrQuCfeUMXIF YKqWzOasDbBBUkkIC0RG6sdUj1R2wYqHn6brGvSqmLgHjM2fwzbaTRLyUb5kUKmOxqhP RvBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=KJ9mUbKUtWzbumUALTFbZ+i8QeNryRmGa91nVup+JbQ=; b=dQtDwsq348Wkyy9ZJqej5l3XZUJyB/IGskupXUvoIZVzGV+tZAD7Qbn2twukqvXVwV 3BztW/mkT4o93QsOMjZ+VvxIeR5sA+hKpodYVNmAh7MiZBa7NYZ+gY4tCsd0A635nC4V I57Uw+J2fFtc+EOqp269rccEJOI8cKQoM/N3qDWcBMW+Ij8qJtAmrNl7TUsuDqjOUFJQ mVPQJpRHdEsTqInaQda8EtJHME6xeRkfzP0wLy/aymbL7RsYfRM3DHdYaxxCq/eGZWli P8yqcdruSlyW6e9CfKFfeDkE1xtHsKK5mVjxNCu5lVeR55OEQ9MTLp5wq/nAI872U04t 0rQA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u129si1447881pfu.117.2018.11.18.17.00.32; Sun, 18 Nov 2018 17:00:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725947AbeKSLWZ (ORCPT + 2 others); Mon, 19 Nov 2018 06:22:25 -0500 Received: from mx.socionext.com ([202.248.49.38]:40664 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725881AbeKSLWZ (ORCPT ); Mon, 19 Nov 2018 06:22:25 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:29 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 8570F60062; Mon, 19 Nov 2018 10:00:29 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:29 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 1743D40387; Mon, 19 Nov 2018 10:00:29 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id EAC35120455; Mon, 19 Nov 2018 10:00:28 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 01/14] ARM: milbeaut: Add basic support for Milbeaut m10v SoC Date: Mon, 19 Nov 2018 10:01:06 +0900 Message-Id: <1542589274-13878-2-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org This adds the basic M10V SoC support under arch/arm. Since all cores are activated in the custom bootloader before booting linux, it is necessary to wait for sub-cores using the trampoline area. Signed-off-by: Sugaya Taichi --- arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-milbeaut/Kconfig | 28 +++++++ arch/arm/mach-milbeaut/Makefile | 3 + arch/arm/mach-milbeaut/m10v_evb.c | 31 ++++++++ arch/arm/mach-milbeaut/platsmp.c | 157 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 222 insertions(+) create mode 100644 arch/arm/mach-milbeaut/Kconfig create mode 100644 arch/arm/mach-milbeaut/Makefile create mode 100644 arch/arm/mach-milbeaut/m10v_evb.c create mode 100644 arch/arm/mach-milbeaut/platsmp.c -- 1.9.1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 91be74d..0b8a1af 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -767,6 +767,8 @@ source "arch/arm/mach-mediatek/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-milbeaut/Kconfig" + source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-moxart/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 05a91d8..627853c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek +machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut machine-$(CONFIG_ARCH_MXS) += mxs machine-$(CONFIG_ARCH_NETX) += netx machine-$(CONFIG_ARCH_NOMADIK) += nomadik diff --git a/arch/arm/mach-milbeaut/Kconfig b/arch/arm/mach-milbeaut/Kconfig new file mode 100644 index 0000000..63b6f69 --- /dev/null +++ b/arch/arm/mach-milbeaut/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0 +menuconfig ARCH_MILBEAUT + bool "Socionext Milbeaut SoCs" + depends on ARCH_MULTI_V7 + select ARM_GIC + select CLKDEV_LOOKUP + select GENERIC_CLOCKEVENTS + select CLKSRC_MMIO + select ZONE_DMA + help + This enables support for Socionext Milbeaut SoCs + +if ARCH_MILBEAUT + +config ARCH_MILBEAUT_M10V + bool "Milbeaut SC2000/M10V platform" + select ARM_ARCH_TIMER + select M10V_TIMER + select PINCTRL + select PINCTRL_M10V + help + Support for Socionext's MILBEAUT M10V based systems + +config MACH_M10V_EVB + bool "Support for Milbeaut Evaluation boards" + default y + +endif diff --git a/arch/arm/mach-milbeaut/Makefile b/arch/arm/mach-milbeaut/Makefile new file mode 100644 index 0000000..64f6f52 --- /dev/null +++ b/arch/arm/mach-milbeaut/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_SMP) += platsmp.o +obj-$(CONFIG_MACH_M10V_EVB) += m10v_evb.o + diff --git a/arch/arm/mach-milbeaut/m10v_evb.c b/arch/arm/mach-milbeaut/m10v_evb.c new file mode 100644 index 0000000..a1fa7c3 --- /dev/null +++ b/arch/arm/mach-milbeaut/m10v_evb.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + * Copyright: (C) 2015 Linaro Ltd. + */ + +#include +#include + +#include +#include + +static struct map_desc m10v_io_desc[] __initdata = { +}; + +void __init m10v_map_io(void) +{ + debug_ll_io_init(); + iotable_init(m10v_io_desc, ARRAY_SIZE(m10v_io_desc)); +} + +static const char * const m10v_compat[] = { + "socionext,milbeaut-m10v-evb", + NULL, +}; + +DT_MACHINE_START(M10V_REB, "Socionext Milbeaut") + .dt_compat = m10v_compat, + .l2c_aux_mask = 0xffffffff, + .map_io = m10v_map_io, +MACHINE_END diff --git a/arch/arm/mach-milbeaut/platsmp.c b/arch/arm/mach-milbeaut/platsmp.c new file mode 100644 index 0000000..b706851 --- /dev/null +++ b/arch/arm/mach-milbeaut/platsmp.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + * Copyright: (C) 2015 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define M10V_MAX_CPU 4 + +#define KERNEL_UNBOOT_FLAG 0x12345678 +#define CPU_FINISH_SUSPEND_FLAG 0x56784321 + +static void __iomem *trampoline; + +static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle) +{ + unsigned int mpidr, cpu, cluster; + + mpidr = cpu_logical_map(l_cpu); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + if (cpu >= M10V_MAX_CPU) + return -EINVAL; + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + + writel(virt_to_phys(secondary_startup), trampoline + cpu * 4); + arch_send_wakeup_ipi_mask(cpumask_of(l_cpu)); + + return 0; +} + +static void m10v_cpu_die(unsigned int l_cpu) +{ + gic_cpu_if_down(0); + + v7_exit_coherency_flush(louis); + + /* Now we are prepared for power-down, do it: */ + wfi(); +} + +static int m10v_cpu_kill(unsigned int l_cpu) +{ + unsigned int mpidr, cpu; + + mpidr = cpu_logical_map(l_cpu); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + + writel(KERNEL_UNBOOT_FLAG, trampoline + cpu * 4); + + return 1; +} + +static struct smp_operations m10v_smp_ops __initdata = { + .smp_boot_secondary = m10v_boot_secondary, + .cpu_die = m10v_cpu_die, + .cpu_kill = m10v_cpu_kill, +}; + +static int __init m10v_smp_init(void) +{ + unsigned int mpidr, cpu, cluster; + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-m10v-evb"); + if (!np || !of_device_is_available(np)) + return -ENODEV; + of_node_put(np); + + np = of_find_compatible_node(NULL, NULL, "socionext,smp-trampoline"); + if (!np) + return -ENODEV; + + trampoline = of_iomap(np, 0); + if (!trampoline) + return -ENODEV; + of_node_put(np); + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster); + + for (cpu = 0; cpu < M10V_MAX_CPU; cpu++) + writel(KERNEL_UNBOOT_FLAG, trampoline + cpu * 4); + + smp_set_ops(&m10v_smp_ops); + + return 0; +} +early_initcall(m10v_smp_init); + +static int m10v_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM); +} + +typedef void (*phys_reset_t)(unsigned long); +static phys_reset_t phys_reset; + +static int m10v_die(unsigned long arg) +{ + setup_mm_for_reboot(); + asm("wfi"); + /* Boot just like a secondary */ + phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset); + phys_reset(virt_to_phys(cpu_resume)); + + return 0; +} + +static int m10v_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + pr_err("STANDBY\n"); + asm("wfi"); + break; + case PM_SUSPEND_MEM: + pr_err("SUSPEND\n"); + cpu_pm_enter(); + cpu_suspend(0, m10v_die); + cpu_pm_exit(); + break; + } + return 0; +} + +static const struct platform_suspend_ops m10v_pm_ops = { + .valid = m10v_pm_valid, + .enter = m10v_pm_enter, +}; + +struct clk *m10v_clclk_register(struct device *cpu_dev); + +static int __init m10v_pm_init(void) +{ + suspend_set_ops(&m10v_pm_ops); + + return 0; +} +late_initcall(m10v_pm_init); From patchwork Mon Nov 19 01:01:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151443 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2057652ljp; Sun, 18 Nov 2018 17:00:41 -0800 (PST) X-Google-Smtp-Source: AFSGD/WuUa8sg5O3eRO3wFnhfHqnmZo2gH7G9ix1fq5OAkjiQae22zsrVfCTy2wLN1bxCwgeQlqg X-Received: by 2002:a17:902:e08b:: with SMTP id cb11mr2644572plb.263.1542589241411; Sun, 18 Nov 2018 17:00:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589241; cv=none; d=google.com; s=arc-20160816; b=BDOpCfUWdyr2QL77dIQjcnzxnZuJe96BAsXQjGIygL5K3VdRO7kp5h7xfzxKCAj9hu eHNauSGXucZ71yddrn/tGoN4W2531wvoz3PvWfT/mMv1+w2TkpNGAAGKO8SYmtg1A6pe fjIlZ1/AEjUs9lzQW0P74Vn82sxrWJLB+MkwTMgML7KVR/uSbSPzAget7C7ZA9jGrU9h k65I0Gqd27Eb64lu1ohINoqATkrWSa199ThapDEVj7fFTtSkTk0fcicf+Y0nX4T+oWJW nrh5pzkTdR+55kb9bmq4kAylEGWJR1WI+kDQ1YDNcXfEEKPWc0u6OL8Kd//+C158JZ6n DhVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=uXLWHVp/y37ie671/NagHHDDnJVvo5ePlQqB5dSS4VA=; b=U9VwpK7f1OeQ6TmzQ6oUmKhNUrNQgeXL39qG1DTvTCdjpCwWYAIo+/1w3AQoJi6G1a 0DpmOFjWGybf5pWROQd5WQZNWg0eB6GgB+SZVY9rBmc6hXudMnzR64RaXq7OH5bQl3Xl /y9WelidC1vgkY6QyhYZzpHb7F2eHqsrHMO1YMQvvQdD4ODnwCmrA71vi10CV2RFtc4f GRBisVMzhdj0QfQSyze0eXsmTWXm8sPk3HqdiN1FyQIh0zDNBB3ht0+3g2ayq0I7MyXD 083dcILqCttO9VVCj4vq3qWiVuCtYWp6+YWoXbtUr3ibO0HpdwiUX9ubUuhangCxUxje skFw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 37-v6si40400258ple.389.2018.11.18.17.00.41; Sun, 18 Nov 2018 17:00:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727767AbeKSLWc (ORCPT + 2 others); Mon, 19 Nov 2018 06:22:32 -0500 Received: from mx.socionext.com ([202.248.49.38]:40685 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727503AbeKSLWb (ORCPT ); Mon, 19 Nov 2018 06:22:31 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:35 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id D9125180111; Mon, 19 Nov 2018 10:00:35 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:35 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 3620E40387; Mon, 19 Nov 2018 10:00:35 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 15805120455; Mon, 19 Nov 2018 10:00:35 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 04/14] dt-bindings: timer: Add Milbeaut M10V timer description Date: Mon, 19 Nov 2018 10:01:09 +0900 Message-Id: <1542589274-13878-5-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add DT bindings document for Milbeaut M10V timer. Signed-off-by: Sugaya Taichi --- .../bindings/timer/socionext,milbeaut-timer.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt new file mode 100644 index 0000000..ddb1b31 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt @@ -0,0 +1,17 @@ +Milbeaut SoCs Timer Controller + +Required properties: + +- compatible : should be "socionext,milbeaut-m10v-timer" +- reg : Specifies base physical address and size of the registers. +- interrupts : The interrupt of the first timer +- clocks: should be "rclk" + +Example: + +timer { + compatible = "socionext,milbeaut-m10v-timer"; + reg = <0x1e000050 0x10>, <0x1e000060 0x10>; + interrupts = <0 91 4>; + clocks = <&rclk>; +}; From patchwork Mon Nov 19 01:01:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151445 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2057692ljp; Sun, 18 Nov 2018 17:00:43 -0800 (PST) X-Google-Smtp-Source: AJdET5ccgsSTcC05jgR+lch+oH2L9/b5zoSZdH4YySJvkBfJoqdt/aIy/vA5zVqBG8QvnhGo5pW0 X-Received: by 2002:a62:509b:: with SMTP id g27mr20935345pfj.48.1542589243639; Sun, 18 Nov 2018 17:00:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589243; cv=none; d=google.com; s=arc-20160816; b=LFn/U0GFKoH7h6/7TZiJMHuEU3HIpBazCaM8nC1GXeyqi+t0EDvJ3TMma8QjSGw9jS SOmycuKjTKjaevINTl8alKGjTMUYxKBsSGDzznOghcRQJDj5D0NN1QnoIOLnPg4gS0jw 37IgcshzfvI1Xutwz9V/jVrIlK3sSRsQdsIcUY8Pa44qgIIM4or1OIXPZ6nh2xKl3rpG /jAVVke4H2XqlF6eFyVni3DYW56Tl6g4l59w7obY3Ei9fpCki5ftw4gv9hbaN2SuGgrD XzcTk7SojRK0XqW8VlHnFGr9CxZzSNM1VwyHCLgPhntsdBMj8p5qbvm7PYjEE7fmysc1 Nbxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=JouPLC06FOWZWuUsChfnCzdJ+bw3u+mXud3PSOh0bAc=; b=kuj7swnvlIA2Vpv1jmTqbL31URwWxpShpXSAhMNSnzm0sCaFA92eHSJ9OnIHgVFhgi oNJSQvmSuWTeHNuC3jhBqnMTKGVmQXSH2Al+qZGcdxQbuqbZ23vzhEndJ+XAkMFYcJrr oRac68T3V3Nu3WlF2tanWS7z3JxceLMPjjOnx3en/pMSd6sT3bOaOQHHHwoyUyPiNYiH 42Wqyk+pYmcfUzEZ3WSk/bOOC9yc2TmC4WyheA/F/4zCSSRqHIPns6tK3y/v0wIGnNaE 0WKeRdIN4iZ1bBxjmIDYVN0hegmZ0uYjszac5jB3Mlm94fESKHWpSXglqeeD0W1Zn0Sq o62w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u8-v6si35184988pgj.409.2018.11.18.17.00.43; Sun, 18 Nov 2018 17:00:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727959AbeKSLWf (ORCPT + 2 others); Mon, 19 Nov 2018 06:22:35 -0500 Received: from mx.socionext.com ([202.248.49.38]:40700 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725904AbeKSLWe (ORCPT ); Mon, 19 Nov 2018 06:22:34 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:39 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id EFBE2180111; Mon, 19 Nov 2018 10:00:38 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:38 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 6644E403AB; Mon, 19 Nov 2018 10:00:38 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 46B75120455; Mon, 19 Nov 2018 10:00:38 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 08/14] dt-bindings: serial: Add Milbeaut M10V serial description Date: Mon, 19 Nov 2018 10:01:13 +0900 Message-Id: <1542589274-13878-9-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add DT bindings document for Milbeaut M10V serial. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/serial/milbeaut-uart.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt new file mode 100644 index 0000000..19d1480 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt @@ -0,0 +1,23 @@ +Socionext Milbeaut UART controller + +Required properties: +- index: must be 0 +- compatible: should be "socionext,milbeaut-m10v-usio-uart". +- reg: offset and length of the register set for the device. +- interrupts: two interrupts specifier. +- clocks: phandle to the input clock. +- interrupt-names: should be "rx", "tx". + +Optional properties: +- uart-flow-enable: flow control enable. + +Example: + usio1: usio_uart@1e700010 { + index = <0>; + compatible = "socionext,milbeaut-m10v-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&hclk>; + uart-flow-enable; + };