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Deprecate it, and encourage users to provide a clock instead. This also restricts the minimum and maximum to the values documented in the register reference [1]. [1] https://www.xilinx.com/html_docs/registers/ug1087/usb3_xhci___guctl.html Signed-off-by: Sean Anderson --- (no changes since v1) Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index d29ffcd27472..4f2b0913ad9f 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -263,8 +263,11 @@ properties: Value for REFCLKPER field of GUCTL register for reference clock period in nanoseconds, when the hardware set default does not match the actual clock. - minimum: 1 - maximum: 0x3ff + + This binding is deprecated. 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When we have a legacy snps,ref-clock-period-ns property and no reference clock, use it instead. Fractional clocks are not currently supported, and will be dealt with in the next commit. Signed-off-by: Sean Anderson Reviewed-by: Robert Hancock Tested-by: Robert Hancock --- (no changes since v1) drivers/usb/dwc3/core.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 699ab9abdc47..5214daceda86 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -348,13 +348,22 @@ static void dwc3_frame_length_adjustment(struct dwc3 *dwc) static void dwc3_ref_clk_period(struct dwc3 *dwc) { u32 reg; + unsigned long rate, period; - if (dwc->ref_clk_per == 0) + if (dwc->ref_clk) { + rate = clk_get_rate(dwc->ref_clk); + if (!rate) + return; + period = NSEC_PER_SEC / rate; + } else if (dwc->ref_clk_per) { + period = dwc->ref_clk_per; + } else { return; + } reg = dwc3_readl(dwc->regs, DWC3_GUCTL); reg &= ~DWC3_GUCTL_REFCLKPER_MASK; - reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, dwc->ref_clk_per); + reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 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It is not documented under dt-bindings, since it is not intended for use on DT-based systems. DT-based systems should use the clocks property instead. Frequency is preferred over period since it has greater precision when used in calculations. Signed-off-by: Sean Anderson --- Changes in v2: - New drivers/usb/dwc3/core.c | 6 ++++-- drivers/usb/dwc3/core.h | 4 +++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 883e119377f0..5f3dc5f6cbcb 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -350,8 +350,8 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc) u32 reg; unsigned long decr, fladj, rate, period; - if (dwc->ref_clk) { - rate = clk_get_rate(dwc->ref_clk); + if (dwc->ref_clk || dwc->ref_clk_freq) { + rate = clk_get_rate(dwc->ref_clk) ?: dwc->ref_clk_freq; if (!rate) return; period = NSEC_PER_SEC / rate; @@ -1492,6 +1492,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) &dwc->fladj); device_property_read_u32(dev, "snps,ref-clock-period-ns", &dwc->ref_clk_per); + device_property_read_u32(dev, "snps,ref-clock-frequency-hz", + &dwc->ref_clk_freq); dwc->dis_metastability_quirk = device_property_read_bool(dev, "snps,dis_metastability_quirk"); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index eb9c1efced05..00a792459fec 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -988,7 +988,8 @@ struct dwc3_scratchpad_array { * @regs: base address for our registers * @regs_size: address space size * @fladj: frame length adjustment - * @ref_clk_per: reference clock period configuration + * @ref_clk_per: reference clock period; deprecated in favor of @ref_clk_freq + * @ref_clk_freq: reference clock frequency to use if @ref_clk is missing * @irq_gadget: peripheral controller's IRQ number * @otg_irq: IRQ number for OTG IRQs * @current_otg_role: current role of operation while using the OTG block @@ -1171,6 +1172,7 @@ struct dwc3 { u32 fladj; u32 ref_clk_per; + u32 ref_clk_freq; u32 irq_gadget; u32 otg_irq; u32 current_otg_role; From patchwork Wed Jan 19 00:24:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 533447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EFE6C433FE for ; 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I haven't reviewed this board's schematics, so please let me know if this is the wrong 24MHz clock to use. Signed-off-by: Sean Anderson --- (no changes since v1) arch/arm64/boot/dts/qcom/ipq6018.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 66ec5615651d..a614b9f73e2c 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -743,12 +743,13 @@ dwc_0: usb@8A00000 { interrupts = ; phys = <&qusb_phy_0>, <&usb0_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + clocks = <&xo>; + clock-names = "ref"; tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; - snps,ref-clock-period-ns = <0x32>; dr_mode = "host"; }; };