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[209.132.180.131]) by mx.google.com with ESMTPS id v23-v6si44624919pff.103.2018.11.20.02.49.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 02:49:27 -0800 (PST) Received-SPF: pass (google.com: domain of libc-alpha-return-97368-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=OS73Xhwb; dkim=pass header.i=@linaro.org header.s=google header.b="EJNtA/dS"; spf=pass (google.com: domain of libc-alpha-return-97368-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="libc-alpha-return-97368-patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :cc:content-type; q=dns; s=default; b=H6JyO5nlFPVZk2rCUzsNiOCqaG 30jnGAedijGW4FqbMhJ/nxh6JQXUneaYAMjpI7/IeLGjTMS28tx3HdGbC8CciXAo r1HbKGrjQKw0EeWrx2AvDK9IzDnb9rQJzcV4kECgKV20B8dQAAMRhSKC8pLAcn8k jR37MMvx0cKSPEPZ8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :cc:content-type; s=default; bh=DF7xHyYwUdmOI6+B4eRKvQriosg=; b= OS73XhwbWSQn4NhwWTErm7zGMkfU2kQHqSZMTqYuBWrfCw06h27ilMTe9kfkAhL7 A80nWBrlgzFzB8uaG6AjvaLSlntd0w/PNA7gPVxrkLQPaK0YnjmnENu7EG+X8tfD 4oCTncgtoxfa6uhaLjxOUSmtc3etjidbS/RhQ5cyI4Y= Received: (qmail 24894 invoked by alias); 20 Nov 2018 10:49:06 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 24706 invoked by uid 89); 20 Nov 2018 10:49:01 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SEM_URI, SEM_URIRED, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-ot1-f47.google.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:from:date:message-id:subject:to:cc; bh=hPfdLDZrFF5aXsQCfXLGZ7r3KF2zcTgVsuXeL/pN4M0=; b=EJNtA/dSwlNWqyNe+A7TbCEL27f/zQ7jLbV8KhTbEYGi6MXgBvgW79+HYBuyowcpkJ U3tBuGVOFGK2zuKolYa0IBvd722wCh2kS1s61Sw2GhhAuAJQyirZSTEzHwOwf1HHBZ43 TC7ReVWmY6iMJscQjr/HgHVVqBMjRr0jrBho8= MIME-Version: 1.0 From: Sameera Deshpande Date: Tue, 20 Nov 2018 16:18:47 +0530 Message-ID: Subject: AARCH64: Adding Saphira core detection using MIDR. To: libc-alpha@sourceware.org Cc: Siddhesh Poyarekar , szabolcs.nagy@arm.com Hi! Please find attached the patch for CPU detection using MIDR code for Qualcomm's Saphira processor, and use Falkor specific memset routine for Saphira. Ok for trunk? -- - Thanks and regards, Sameera D. diff --git a/sysdeps/aarch64/multiarch/memset.c b/sysdeps/aarch64/multiarch/memset.c index d74ed3a..351b957 100644 --- a/sysdeps/aarch64/multiarch/memset.c +++ b/sysdeps/aarch64/multiarch/memset.c @@ -32,7 +32,7 @@ extern __typeof (__redirect_memset) __memset_falkor attribute_hidden; extern __typeof (__redirect_memset) __memset_generic attribute_hidden; libc_ifunc (__libc_memset, - ((IS_FALKOR (midr) || IS_PHECDA (midr)) && zva_size == 64 + ((AVOID_SLOW_MRS (midr)) && zva_size == 64 ? __memset_falkor : __memset_generic)); diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c index 39eba01..266e972 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c @@ -31,6 +31,7 @@ struct cpu_list }; static struct cpu_list cpu_list[] = { + {"saphira", 0x510FC010}, {"falkor", 0x510FC000}, {"thunderxt88", 0x430F0A10}, {"thunderx2t99", 0x431F0AF0}, diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h index eb35adf..80ae39a 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h @@ -52,6 +52,13 @@ #define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \ && MIDR_PARTNUM(midr) == 0x000) +#define IS_SAPHIRA(midr) (MIDR_IMPLEMENTOR(midr) == 'Q' \ + && MIDR_PARTNUM(midr) == 0xc01) + +#define AVOID_SLOW_MRS(midr) (IS_FALKOR (midr) \ + || IS_SAPHIRA (midr) \ + || IS_PHECDA (midr)) + struct cpu_features { uint64_t midr_el1;