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If the bit is set, the driver can skip downloading the firmware again during system resume or runtime resume. Bump the ABI version to 3.19 to make it aligned with FW side. Reviewed-by: Ranjani Sridharan Reviewed-by: Péter Ujfalusi Signed-off-by: Keyon Jie Signed-off-by: Pierre-Louis Bossart --- include/sound/sof/info.h | 1 + include/uapi/sound/sof/abi.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/sound/sof/info.h b/include/sound/sof/info.h index 0b7101aef596..65e86e4e9fd8 100644 --- a/include/sound/sof/info.h +++ b/include/sound/sof/info.h @@ -25,6 +25,7 @@ #define SOF_IPC_INFO_LOCKS BIT(1) #define SOF_IPC_INFO_LOCKSV BIT(2) #define SOF_IPC_INFO_GDB BIT(3) +#define SOF_IPC_INFO_D3_PERSISTENT BIT(4) /* extended data types that can be appended onto end of sof_ipc_fw_ready */ enum sof_ipc_ext_data { diff --git a/include/uapi/sound/sof/abi.h b/include/uapi/sound/sof/abi.h index fe2cfae94b45..f4232d289a22 100644 --- a/include/uapi/sound/sof/abi.h +++ b/include/uapi/sound/sof/abi.h @@ -26,7 +26,7 @@ /* SOF ABI version major, minor and patch numbers */ #define SOF_ABI_MAJOR 3 -#define SOF_ABI_MINOR 18 +#define SOF_ABI_MINOR 19 #define SOF_ABI_PATCH 0 /* SOF ABI version number. Format within 32bit word is MMmmmppp */ From patchwork Thu Jan 20 23:15:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pierre-Louis Bossart X-Patchwork-Id: 533600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6A45C433EF for ; Thu, 20 Jan 2022 23:17:17 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id EE1F92DC7; Fri, 21 Jan 2022 00:16:25 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz EE1F92DC7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1642720636; bh=YzwhIx/BcLqW8OrP/DLYnVD9dmojhpOJVFWQweeBL0g=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=BiM4bUrYsgsK1vAkwvsxBYkfTxAqXBakAKBUPaNi1TVUHLps2QYObheRmgYeS6M1H YF1JBNFwA00G+AXkRw3EEOVGN4A3AfNOdc9ls/m0k9Sax+hCL4Cwfd4Go95wSqOVCf bidMVlED9lOQzrlC/aj6RSBW3NPydVNxbUIijieI= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id A332DF80423; Fri, 21 Jan 2022 00:15:55 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 95CE5F8050F; Fri, 21 Jan 2022 00:15:54 +0100 (CET) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id D3A44F800F2 for ; Fri, 21 Jan 2022 00:15:47 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz D3A44F800F2 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MUxI/+e7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1642720549; x=1674256549; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YzwhIx/BcLqW8OrP/DLYnVD9dmojhpOJVFWQweeBL0g=; b=MUxI/+e7Mo7PKP5/2FFcKR9/dnVFgfU77EERWS9j0vard43gRxhsI5Uy 7bY8+iBe1UsTITmnx6KhZ6ac0DRAGmOtsY54aAtueJufeCulBRO+3foaW ITDnONU/q9MZNUggQWwUwcUauArITZGf2aS2G44eC/IJMEmUKpQv0cBii lzTDIzkBwdRbotVhNhxxFBbRMJsewiwvnzbsUmBQj4s+RR8reL3TbLEwx vNXstoFwTcsLx0mY8TDM90hdXRQmW2QY5G24clA3iHd3SFmNbaPML8DY3 EhO9oAxQfiSFOCp6rsR1XkzzDhfmzx7Ibi9Y27Hgk5jXG320LIH7WwpSj w==; X-IronPort-AV: E=McAfee;i="6200,9189,10233"; a="245721376" X-IronPort-AV: E=Sophos;i="5.88,303,1635231600"; d="scan'208";a="245721376" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2022 15:15:44 -0800 X-IronPort-AV: E=Sophos;i="5.88,303,1635231600"; d="scan'208";a="672741386" Received: from sthambit-mobl1.amr.corp.intel.com (HELO pbossart-mobl3.intel.com) ([10.212.64.44]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2022 15:15:41 -0800 From: Pierre-Louis Bossart To: alsa-devel@alsa-project.org Subject: [PATCH 2/5] ASoC: SOF: Intel: use inclusive language for SSP clocks Date: Thu, 20 Jan 2022 17:15:29 -0600 Message-Id: <20220120231532.196926-3-pierre-louis.bossart@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120231532.196926-1-pierre-louis.bossart@linux.intel.com> References: <20220120231532.196926-1-pierre-louis.bossart@linux.intel.com> MIME-Version: 1.0 Cc: tiwai@suse.de, Keyon Jie , Pierre-Louis Bossart , Ranjani Sridharan , broonie@kernel.org, =?utf-8?q?P=C3=A9ter_Ujfalusi?= X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" We introduced provider/consumer terms, and CBP_CFP acronyms for codec drivers, let's use them as well in SOF. Reviewed-by: Ranjani Sridharan Reviewed-by: Péter Ujfalusi Reviewed-by: Keyon Jie Signed-off-by: Pierre-Louis Bossart --- sound/soc/sof/intel/hda-loader.c | 6 +++--- sound/soc/sof/intel/hda.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c index 33306d2023a7..43de6f1d62a9 100644 --- a/sound/soc/sof/intel/hda-loader.c +++ b/sound/soc/sof/intel/hda-loader.c @@ -101,14 +101,14 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag) goto err; } - /* DSP is powered up, set all SSPs to slave mode */ + /* DSP is powered up, set all SSPs to clock consumer/codec provider mode */ for (i = 0; i < chip->ssp_count; i++) { snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, chip->ssp_base_offset + i * SSP_DEV_MEM_SIZE + SSP_SSC1_OFFSET, - SSP_SET_SLAVE, - SSP_SET_SLAVE); + SSP_SET_CBP_CFP, + SSP_SET_CBP_CFP); } /* step 2: purge FW request */ diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h index 03a6bb7a165c..7838a998ea95 100644 --- a/sound/soc/sof/intel/hda.h +++ b/sound/soc/sof/intel/hda.h @@ -383,9 +383,9 @@ /* SSP Registers */ #define SSP_SSC1_OFFSET 0x4 -#define SSP_SET_SCLK_SLAVE BIT(25) -#define SSP_SET_SFRM_SLAVE BIT(24) -#define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE) +#define SSP_SET_SCLK_CONSUMER BIT(25) +#define SSP_SET_SFRM_CONSUMER BIT(24) +#define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) #define HDA_IDISP_ADDR 2 #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) From patchwork Thu Jan 20 23:15:30 2022 Content-Type: text/plain; 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20 Jan 2022 15:15:42 -0800 From: Pierre-Louis Bossart To: alsa-devel@alsa-project.org Subject: [PATCH 3/5] ASoC: SOF: Intel: hda-loader: add SSP helper Date: Thu, 20 Jan 2022 17:15:30 -0600 Message-Id: <20220120231532.196926-4-pierre-louis.bossart@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120231532.196926-1-pierre-louis.bossart@linux.intel.com> References: <20220120231532.196926-1-pierre-louis.bossart@linux.intel.com> MIME-Version: 1.0 Cc: tiwai@suse.de, Keyon Jie , Ranjani Sridharan , Pierre-Louis Bossart , broonie@kernel.org, =?utf-8?q?P=C3=A9ter_Ujfalusi?= X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Keyon Jie Move the SSP clock configuration to the hda_set_ssp_cbp_cfp() helper, to be used in follow-up patches Reviewed-by: Ranjani Sridharan Reviewed-by: Péter Ujfalusi Signed-off-by: Keyon Jie Signed-off-by: Pierre-Louis Bossart --- sound/soc/sof/intel/hda-loader.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c index 43de6f1d62a9..7f1b1d0f2422 100644 --- a/sound/soc/sof/intel/hda-loader.c +++ b/sound/soc/sof/intel/hda-loader.c @@ -25,6 +25,23 @@ #define HDA_CL_STREAM_FORMAT 0x40 +static void hda_ssp_set_cbp_cfp(struct snd_sof_dev *sdev) +{ + struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; + const struct sof_intel_dsp_desc *chip = hda->desc; + int i; + + /* DSP is powered up, set all SSPs to clock consumer/codec provider mode */ + for (i = 0; i < chip->ssp_count; i++) { + snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, + chip->ssp_base_offset + + i * SSP_DEV_MEM_SIZE + + SSP_SSC1_OFFSET, + SSP_SET_CBP_CFP, + SSP_SET_CBP_CFP); + } +} + static struct hdac_ext_stream *cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, unsigned int size, struct snd_dma_buffer *dmab, int direction) @@ -91,7 +108,6 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag) char *dump_msg; u32 flags, j; int ret; - int i; /* step 1: power up corex */ ret = hda_dsp_enable_core(sdev, chip->host_managed_cores_mask); @@ -101,15 +117,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag) goto err; } - /* DSP is powered up, set all SSPs to clock consumer/codec provider mode */ - for (i = 0; i < chip->ssp_count; i++) { - snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, - chip->ssp_base_offset - + i * SSP_DEV_MEM_SIZE - + SSP_SSC1_OFFSET, - SSP_SET_CBP_CFP, - SSP_SET_CBP_CFP); - } + hda_ssp_set_cbp_cfp(sdev); /* step 2: purge FW request */ snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, From patchwork Thu Jan 20 23:15:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pierre-Louis Bossart X-Patchwork-Id: 533599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37096C433EF for ; Thu, 20 Jan 2022 23:17:49 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 303CD2DC4; Fri, 21 Jan 2022 00:16:57 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 303CD2DC4 DKIM-Signature: v=1; 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d="scan'208";a="672741396" Received: from sthambit-mobl1.amr.corp.intel.com (HELO pbossart-mobl3.intel.com) ([10.212.64.44]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2022 15:15:42 -0800 From: Pierre-Louis Bossart To: alsa-devel@alsa-project.org Subject: [PATCH 4/5] ASoC: SOF: Intel: hda-loader: add IMR restore support Date: Thu, 20 Jan 2022 17:15:31 -0600 Message-Id: <20220120231532.196926-5-pierre-louis.bossart@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120231532.196926-1-pierre-louis.bossart@linux.intel.com> References: <20220120231532.196926-1-pierre-louis.bossart@linux.intel.com> MIME-Version: 1.0 Cc: tiwai@suse.de, Keyon Jie , Ranjani Sridharan , Pierre-Louis Bossart , broonie@kernel.org, =?utf-8?q?P=C3=A9ter_Ujfalusi?= X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Keyon Jie If the firmware declares the IMR restore feature, we only need to do a simple powering up to resume from D3, no firmware re-downloading needed - the context is saved/restored to/from IMR without needing driver support. Add a hda_dsp_boot_imr() helper for this simple DSP reboot, and use it when it is available. Reviewed-by: Ranjani Sridharan Reviewed-by: Péter Ujfalusi Signed-off-by: Keyon Jie Signed-off-by: Pierre-Louis Bossart --- sound/soc/sof/intel/hda-loader.c | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c index 7f1b1d0f2422..baf2ff146f50 100644 --- a/sound/soc/sof/intel/hda-loader.c +++ b/sound/soc/sof/intel/hda-loader.c @@ -353,6 +353,38 @@ int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev) return ret; } +static int hda_dsp_boot_imr(struct snd_sof_dev *sdev) +{ + struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; + const struct sof_intel_dsp_desc *chip = hda->desc; + unsigned long mask; + u32 j; + int ret; + + /* power up & unstall/run the cores to run the firmware */ + ret = hda_dsp_enable_core(sdev, chip->init_core_mask); + if (ret < 0) { + dev_err(sdev->dev, "dsp core start failed %d\n", ret); + return -EIO; + } + + /* set enabled cores mask and increment ref count for cores in init_core_mask */ + sdev->enabled_cores_mask |= chip->init_core_mask; + mask = sdev->enabled_cores_mask; + for_each_set_bit(j, &mask, SOF_MAX_DSP_NUM_CORES) + sdev->dsp_core_ref_count[j]++; + + hda_ssp_set_cbp_cfp(sdev); + + /* enable IPC interrupts */ + hda_dsp_ipc_int_enable(sdev); + + /* process wakes */ + hda_sdw_process_wakeen(sdev); + + return ret; +} + int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev) { struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; @@ -363,6 +395,12 @@ int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev) struct firmware stripped_firmware; int ret, ret1, i; + if ((sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT) && + !sdev->first_boot) { + dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n"); + return hda_dsp_boot_imr(sdev); + } + chip_info = desc->chip_info; if (plat_data->fw->size <= plat_data->fw_offset) { From patchwork Thu Jan 20 23:15:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pierre-Louis Bossart X-Patchwork-Id: 533598 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08739C433EF for ; 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X-IronPort-AV: E=McAfee;i="6200,9189,10233"; a="245721379" X-IronPort-AV: E=Sophos;i="5.88,303,1635231600"; d="scan'208";a="245721379" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2022 15:15:44 -0800 X-IronPort-AV: E=Sophos;i="5.88,303,1635231600"; d="scan'208";a="672741402" Received: from sthambit-mobl1.amr.corp.intel.com (HELO pbossart-mobl3.intel.com) ([10.212.64.44]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2022 15:15:43 -0800 From: Pierre-Louis Bossart To: alsa-devel@alsa-project.org Subject: [PATCH 5/5] ASoC: SOF: add flag to disable IMR restore to sof_debug Date: Thu, 20 Jan 2022 17:15:32 -0600 Message-Id: <20220120231532.196926-6-pierre-louis.bossart@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120231532.196926-1-pierre-louis.bossart@linux.intel.com> References: <20220120231532.196926-1-pierre-louis.bossart@linux.intel.com> MIME-Version: 1.0 Cc: tiwai@suse.de, Keyon Jie , Ranjani Sridharan , Pierre-Louis Bossart , broonie@kernel.org, =?utf-8?q?P=C3=A9ter_Ujfalusi?= X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Keyon Jie Add flag _IGNORE_D3_PERSISTENT to disable IMR restore feature to the sof_debug module parameter. The IMR restore feature will be enabled for all Intel cAVS platforms by default, but setting the flag _IGNORE_D3_PERSISTENT can help to disable the feature for debug purpose, to rule out any possible regression introduced by the change of not re-downloading firmware to the DSP at resuming from suspended state. Reviewed-by: Ranjani Sridharan Reviewed-by: Péter Ujfalusi Signed-off-by: Keyon Jie Signed-off-by: Pierre-Louis Bossart --- sound/soc/sof/intel/hda-loader.c | 2 ++ sound/soc/sof/sof-priv.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c index baf2ff146f50..6af3325b7e40 100644 --- a/sound/soc/sof/intel/hda-loader.c +++ b/sound/soc/sof/intel/hda-loader.c @@ -21,6 +21,7 @@ #include #include "ext_manifest.h" #include "../ops.h" +#include "../sof-priv.h" #include "hda.h" #define HDA_CL_STREAM_FORMAT 0x40 @@ -396,6 +397,7 @@ int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev) int ret, ret1, i; if ((sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT) && + !(sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) && !sdev->first_boot) { dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n"); return hda_dsp_boot_imr(sdev); diff --git a/sound/soc/sof/sof-priv.h b/sound/soc/sof/sof-priv.h index 087935192ce8..29bb56b7267a 100644 --- a/sound/soc/sof/sof-priv.h +++ b/sound/soc/sof/sof-priv.h @@ -34,6 +34,9 @@ * on primary core */ #define SOF_DBG_PRINT_ALL_DUMPS BIT(6) /* Print all ipc and dsp dumps */ +#define SOF_DBG_IGNORE_D3_PERSISTENT BIT(7) /* ignore the DSP D3 persistent capability + * and always download firmware upon D3 exit + */ /* Flag definitions used for controlling the DSP dump behavior */ #define SOF_DBG_DUMP_REGS BIT(0)