From patchwork Sun Jan 23 18:35:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Srba X-Patchwork-Id: 534280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C108C43219 for ; Sun, 23 Jan 2022 18:38:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239549AbiAWSiq (ORCPT ); Sun, 23 Jan 2022 13:38:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239550AbiAWSip (ORCPT ); Sun, 23 Jan 2022 13:38:45 -0500 Received: from mxd2.seznam.cz (mxd2.seznam.cz [IPv6:2a02:598:2::210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDA54C061401; Sun, 23 Jan 2022 10:38:44 -0800 (PST) Received: from email.seznam.cz by email-smtpc20a.ng.seznam.cz (email-smtpc20a.ng.seznam.cz [10.23.18.24]) id 0f9f5bb354910fda0e3697ed; Sun, 23 Jan 2022 19:38:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=seznam.cz; s=beta; t=1642963097; bh=6ysqmf+DLqMybDzlOK9bJTtYwpKDptcXhR/vcXoyaoU=; h=Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:MIME-Version: Content-Transfer-Encoding:X-szn-frgn:X-szn-frgc; b=TGKVAGXM02QVJsFasv9lfPW7ep8LR+FqDM/ICIhA3eWBhZpWK44f6gbcjX+P4Eg4B 7ItPk+xJYUB7lu693fk1wXZHi9SsWhIT2sasXp0ntj+cKlJWem+uz4EVzOdI7D/f19 nab6VXpo3RydT4gYC6SQGY3R+QmQxKvlhRYOPd2c= Received: from localhost.localdomain (ip-244-214.dynamic.ccinternet.cz [185.148.214.244]) by email-relay19.ng.seznam.cz (Seznam SMTPD 1.3.136) with ESMTP; Sun, 23 Jan 2022 19:38:12 +0100 (CET) From: michael.srba@seznam.cz To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Philipp Zabel Cc: Linus Walleij , Florian Fainelli , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Michael Srba Subject: [PATCH v2 1/5] dt-bindings: clock: gcc-msm8998: Add definitions of SSC-related clocks Date: Sun, 23 Jan 2022 19:35:43 +0100 Message-Id: <20220123183547.15830-1-michael.srba@seznam.cz> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-szn-frgn: <430424e6-bf1c-422e-abaa-55831a8b1b02> X-szn-frgc: <0> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Michael Srba This patch adds definitions of four clocks which need to be manipulated in order to initialize the AHB bus which exposes the SCC block in the global address space. Signed-off-by: Michael Srba --- CHANGES: - v2: none --- include/dt-bindings/clock/qcom,gcc-msm8998.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 72c99e486d86..1badb4f9c58f 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -186,6 +186,10 @@ #define UFS_UNIPRO_CORE_CLK_SRC 177 #define GCC_MMSS_GPLL0_CLK 178 #define HMSS_GPLL0_CLK_SRC 179 +#define GCC_IM_SLEEP 180 +#define AGGRE2_SNOC_NORTH_AXI 181 +#define SSC_XO 182 +#define SSC_CNOC_AHBS_CLK 183 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 From patchwork Sun Jan 23 18:35:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Srba X-Patchwork-Id: 534281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18A66C433F5 for ; Sun, 23 Jan 2022 18:38:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239539AbiAWSim (ORCPT ); Sun, 23 Jan 2022 13:38:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239319AbiAWSim (ORCPT ); Sun, 23 Jan 2022 13:38:42 -0500 Received: from mxd2.seznam.cz (mxd2.seznam.cz [IPv6:2a02:598:2::210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EC1EC06173B; Sun, 23 Jan 2022 10:38:41 -0800 (PST) Received: from email.seznam.cz by email-smtpc4b.ng.seznam.cz (email-smtpc4b.ng.seznam.cz [10.23.13.105]) id 4e559c10155bc8794ffc504e; Sun, 23 Jan 2022 19:38:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=seznam.cz; s=beta; t=1642963096; bh=XMZCKGV8OMiltnWUVYIUOyTm2Mqm3NqumUNZCma58zc=; h=Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:X-szn-frgn: X-szn-frgc; b=UcuTcbE1wnMqJCvjtc+MONxVP7WHf88UI3MLn/zdAAPX5hu8LBi3zITbkYwWECdHp XrgTpPa2n2cbF8Avh9YWxtsLo2uOoUWgqDN8RIooNlNs4XixCkaD+EkozD5epBhZwl lPW7ajyWYTkwUGIzNM1B4hSvKi0gSKnalkHBEjGk= Received: from localhost.localdomain (ip-244-214.dynamic.ccinternet.cz [185.148.214.244]) by email-relay19.ng.seznam.cz (Seznam SMTPD 1.3.136) with ESMTP; Sun, 23 Jan 2022 19:38:13 +0100 (CET) From: michael.srba@seznam.cz To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Philipp Zabel Cc: Linus Walleij , Florian Fainelli , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Michael Srba Subject: [PATCH v2 3/5] dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus Date: Sun, 23 Jan 2022 19:35:45 +0100 Message-Id: <20220123183547.15830-3-michael.srba@seznam.cz> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220123183547.15830-1-michael.srba@seznam.cz> References: <20220123183547.15830-1-michael.srba@seznam.cz> MIME-Version: 1.0 X-szn-frgn: <28937899-e6ca-4b2a-89c8-ad12e2ea2f8b> X-szn-frgc: <0> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Michael Srba This patch adds bindings for the AHB bus which exposes the SCC block in the global address space. This bus (and the SSC block itself) is present on certain qcom SoCs. In typical configuration, this bus (as some of the clocks and registers that we need to manipulate) is not accessible to the OS, and the resources on this bus are indirectly accessed by communicating with a hexagon CPU core residing in the SSC block. In this configuration, the hypervisor is the one performing the bus initialization for the purposes of bringing the haxagon CPU core out of reset. However, it is possible to change the configuration, in which case this binding serves to allow the OS to initialize the bus. Signed-off-by: Michael Srba --- CHANGES: - v2: fix issues caught by by dt-schema --- Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml | 159 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml new file mode 100644 index 000000000000..f3f4a991337b --- /dev/null +++ b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs + +maintainers: + - Michael Srba + +description: | + This binding describes the dependencies (clocks, resets, power domains) which + need to be turned on in a sequence before communication over the AHB bus + becomes possible. + + Additionally, the reg property is used to pass to the driver the location of + two sadly undocumented registers which need to be poked as part of the sequence. + + Currently, this binding is known to apply to msm8998. If the binding applies + in it's current form, the compatible should contain "qcom,ssc-block-bus-v1". + If the binding needs tweaking in order to apply to another SoC, this binding + shall be extended. + + +properties: + compatible: + contains: + items: + - enum: [ qcom,ssc-block-bus-v1 ] + - const: qcom,ssc-block-bus + description: + Shall contain "qcom,ssc-block-bus" + + reg: + description: | + Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1 + registers + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: mpm_sscaon_config0 + - const: mpm_sscaon_config1 + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + clocks: + description: | + Clock phandles for the xo, aggre2, gcc_im_sleep, aggre2_north, + ssc_xo and ssc_ahbs clocks + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: xo + - const: aggre2 + - const: gcc_im_sleep + - const: aggre2_north + - const: ssc_xo + - const: ssc_ahbs + + power-domains: + description: Power domain phandles for the ssc_cx and ssc_mx power domains + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: ssc_cx + - const: ssc_mx + + resets: + description: | + Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the + branch control register associated with the ssc_xo and ssc_ahbs clocks) + minItems: 2 + maxItems: 2 + + reset-names: + items: + - const: ssc_reset + - const: ssc_bcr + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandle reference to a syscon representing TCSR followed by the + offset within syscon for the ssc AXI halt register. + +required: + - compatible + - reg + - reg-names + - '#address-cells' + - '#size-cells' + - ranges + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - qcom,halt-regs + +additionalProperties: true + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + ssc_ahb_slave: bus@10ac008 { // devices under this node are physically located in the SSC block, connected to an ssc-internal bus; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + compatible = "qcom,ssc-block-bus"; + reg = <0x10ac008 0x4>, <0x10ac010 0x4>; + reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1"; + + clocks = <&xo>, + <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&gcc GCC_IM_SLEEP>, + <&gcc AGGRE2_SNOC_NORTH_AXI>, + <&gcc SSC_XO>, + <&gcc SSC_CNOC_AHBS_CLK>; + clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs"; + + resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>; + reset-names = "ssc_reset", "ssc_bcr"; + + power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>; + power-domain-names = "ssc_cx", "ssc_mx"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x26000>; + + ssc_tlmm: pinctrl@5e10000 { + compatible = "qcom,msm8998-ssc-tlmm-pinctrl"; + reg = <0x5E10000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&ssc_tlmm 0 0 20>; + }; + }; + }; From patchwork Sun Jan 23 18:35:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Srba X-Patchwork-Id: 534279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7C62C4321E for ; Sun, 23 Jan 2022 18:38:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233181AbiAWSiu (ORCPT ); Sun, 23 Jan 2022 13:38:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239554AbiAWSiq (ORCPT ); Sun, 23 Jan 2022 13:38:46 -0500 Received: from mxd2.seznam.cz (mxd2.seznam.cz [IPv6:2a02:598:2::210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B91FBC06173B; Sun, 23 Jan 2022 10:38:45 -0800 (PST) Received: from email.seznam.cz by email-smtpc16b.ng.seznam.cz (email-smtpc16b.ng.seznam.cz [10.23.18.17]) id 71e0620e2aee36677049ae50; Sun, 23 Jan 2022 19:38:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=seznam.cz; s=beta; t=1642963097; bh=Ik/r5t5nairAc/XiILJZVjB8H0SgKH81lbvzG8dtTOU=; h=Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:X-szn-frgn: X-szn-frgc; b=UcouYHtsw+7KeJOKsQhoMNERZw06C+QfQsRZu2BznZ4hOgKhT32ZB7pzQMRrdnTVF WJQvcNU69VBX3g97t9+DXbmzkrku6GsHSLhHc/lZyM8kgXE7Kt5jJPSTkow8hSAlQg ZuLF+nVjgItCGW91ZgEME0sQ3z9b1NMf5jPdNzSY= Received: from localhost.localdomain (ip-244-214.dynamic.ccinternet.cz [185.148.214.244]) by email-relay19.ng.seznam.cz (Seznam SMTPD 1.3.136) with ESMTP; Sun, 23 Jan 2022 19:38:13 +0100 (CET) From: michael.srba@seznam.cz To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Philipp Zabel Cc: Linus Walleij , Florian Fainelli , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Michael Srba Subject: [PATCH 4/5] drivers: bus: add driver for initializing the SSC bus on (some) qcom SoCs Date: Sun, 23 Jan 2022 19:35:46 +0100 Message-Id: <20220123183547.15830-4-michael.srba@seznam.cz> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220123183547.15830-1-michael.srba@seznam.cz> References: <20220123183547.15830-1-michael.srba@seznam.cz> MIME-Version: 1.0 X-szn-frgn: <170cc573-3830-4244-b731-d2e95ed14765> X-szn-frgc: <0> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Michael Srba This patch adds bindings for the AHB bus which exposes the SCC block in the global address space. This bus (and the SSC block itself) is present on certain qcom SoCs. In typical configuration, this bus (as some of the clocks and registers that we need to manipulate) is not accessible to Linux, and the resources on this bus are indirectly accessed by communicating with a hexagon CPU core residing in the SSC block. In this configuration, the hypervisor is the one performing the bus initialization for the purposes of bringing the haxagon CPU core out of reset. However, it is possible to change the configuration, in which case this driver will initialize the bus. In combination with drivers for resources on the SSC bus, this driver can aid in debugging, and for example with a TLMM driver can be used to directly access SSC-dedicated GPIO pins, removing the need to commit to a particular usecase during hw design. Finally, until open firmware for the hexagon core is available, this approach allows for using sensors hooked up to SSC-dedicated GPIO pins on mainline Linux simply by utilizing the existing in-tree drivers for these sensors. Signed-off-by: Michael Srba --- CHANGES: - v2: none --- drivers/bus/Kconfig | 6 + drivers/bus/Makefile | 1 + drivers/bus/qcom-ssc-block-bus.c | 365 +++++++++++++++++++++++++++++++ 3 files changed, 372 insertions(+) create mode 100644 drivers/bus/qcom-ssc-block-bus.c diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 3c68e174a113..f2b2e3098491 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -173,6 +173,12 @@ config SUNXI_RSB with various RSB based devices, such as AXP223, AXP8XX PMICs, and AC100/AC200 ICs. +config QCOM_SSC_BLOCK_BUS + bool "Qualcomm SSC Block Bus Init Driver" + help + Say y here to enable support for initializing the bus that connects the SSC block's internal + bus to the cNoC on (some) qcom SoCs + config TEGRA_ACONNECT tristate "Tegra ACONNECT Bus Driver" depends on ARCH_TEGRA_210_SOC diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 52c2f35a26a9..e6756e83a9c4 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o +obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/qcom-ssc-block-bus.c b/drivers/bus/qcom-ssc-block-bus.c new file mode 100644 index 000000000000..a93c7350a231 --- /dev/null +++ b/drivers/bus/qcom-ssc-block-bus.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2021, Michael Srba + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* AXI Halt Register Offsets */ +#define AXI_HALTREQ_REG 0x0 +#define AXI_HALTACK_REG 0x4 +#define AXI_IDLE_REG 0x8 + +static const char * const qcom_ssc_block_pd_names[] = { + "ssc_cx", + "ssc_mx" +}; + +struct qcom_ssc_block_bus_data { + int num_pds; + const char **pd_names; + struct device *pds[ARRAY_SIZE(qcom_ssc_block_pd_names)]; + char __iomem *reg_mpm_sscaon_config0; // MPM - msm power manager; AON - always-on + char __iomem *reg_mpm_sscaon_config1; // that's as much as we know about these + struct regmap *halt_map; + u32 ssc_axi_halt; + struct clk *xo_clk; + struct clk *aggre2_clk; + struct clk *gcc_im_sleep_clk; + struct clk *aggre2_north_clk; + struct clk *ssc_xo_clk; + struct clk *ssc_ahbs_clk; + struct reset_control *ssc_bcr; + struct reset_control *ssc_reset; +}; + +static void reg32_set_bits(char __iomem *reg, u32 value) +{ + u32 tmp = ioread32(reg); + + iowrite32(tmp | value, reg); +} + +static void reg32_clear_bits(char __iomem *reg, u32 value) +{ + u32 tmp = ioread32(reg); + + iowrite32(tmp & (~value), reg); +} + + +static int qcom_ssc_block_bus_init(struct device *dev) +{ + int ret; + + struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev); + + clk_prepare_enable(data->xo_clk); + clk_prepare_enable(data->aggre2_clk); + + clk_prepare_enable(data->gcc_im_sleep_clk); + + reg32_clear_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5)); + reg32_clear_bits(data->reg_mpm_sscaon_config1, BIT(31)); + + clk_disable(data->aggre2_north_clk); + + ret = reset_control_deassert(data->ssc_reset); + if (ret) { + dev_err(dev, "error deasserting ssc_reset: %d\n", ret); + return ret; + } + + clk_prepare_enable(data->aggre2_north_clk); + + ret = reset_control_deassert(data->ssc_bcr); + if (ret) { + dev_err(dev, "error deasserting ssc_bcr: %d\n", ret); + return ret; + } + + regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 0); + + clk_prepare_enable(data->ssc_xo_clk); + + clk_prepare_enable(data->ssc_ahbs_clk); + + return 0; +} + +static int qcom_ssc_block_bus_deinit(struct device *dev) +{ + int ret; + + struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev); + + clk_disable(data->ssc_xo_clk); + clk_disable(data->ssc_ahbs_clk); + + ret = reset_control_assert(data->ssc_bcr); + if (ret) { + dev_err(dev, "error asserting ssc_bcr: %d\n", ret); + return ret; + } + + regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1); + + reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31)); + reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5)); + + ret = reset_control_assert(data->ssc_reset); + if (ret) { + dev_err(dev, "error asserting ssc_reset: %d\n", ret); + return ret; + } + + clk_disable(data->gcc_im_sleep_clk); + + clk_disable(data->aggre2_north_clk); + + clk_disable(data->aggre2_clk); + clk_disable(data->xo_clk); + + return 0; +} + + +static int qcom_ssc_block_bus_pds_attach(struct device *dev, struct device **pds, + const char **pd_names, size_t num_pds) +{ + int ret; + int i; + + for (i = 0; i < num_pds; i++) { + pds[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); + if (IS_ERR_OR_NULL(pds[i])) { + ret = PTR_ERR(pds[i]) ? : -ENODATA; + goto unroll_attach; + } + } + + return num_pds; + +unroll_attach: + for (i--; i >= 0; i--) + dev_pm_domain_detach(pds[i], false); + + return ret; +}; + +static void qcom_ssc_block_bus_pds_detach(struct device *dev, struct device **pds, size_t num_pds) +{ + int i; + + for (i = 0; i < num_pds; i++) + dev_pm_domain_detach(pds[i], false); +} + +static int qcom_ssc_block_bus_pds_enable(struct device **pds, size_t num_pds) +{ + int ret; + int i; + + for (i = 0; i < num_pds; i++) { + dev_pm_genpd_set_performance_state(pds[i], INT_MAX); + ret = pm_runtime_get_sync(pds[i]); + if (ret < 0) + goto unroll_pd_votes; + } + + return 0; + +unroll_pd_votes: + for (i--; i >= 0; i--) { + dev_pm_genpd_set_performance_state(pds[i], 0); + pm_runtime_put(pds[i]); + } + + return ret; +}; + +static void qcom_ssc_block_bus_pds_disable(struct device **pds, size_t num_pds) +{ + int i; + + for (i = 0; i < num_pds; i++) { + dev_pm_genpd_set_performance_state(pds[i], 0); + pm_runtime_put(pds[i]); + } +} + +static int qcom_ssc_block_bus_probe(struct platform_device *pdev) +{ + struct qcom_ssc_block_bus_data *data; + struct device_node *np = pdev->dev.of_node; + struct of_phandle_args halt_args; + struct resource *res; + int ret; + + if (np) + of_platform_populate(np, NULL, NULL, &pdev->dev); + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + platform_set_drvdata(pdev, data); + + data->pd_names = qcom_ssc_block_pd_names; + data->num_pds = ARRAY_SIZE(qcom_ssc_block_pd_names); + + ret = qcom_ssc_block_bus_pds_attach(&pdev->dev, data->pds, data->pd_names, data->num_pds); + if (ret < 0) { + dev_err(&pdev->dev, "error when attaching power domains: %d\n", ret); + return ret; + } + + ret = qcom_ssc_block_bus_pds_enable(data->pds, data->num_pds); + if (ret < 0) { + dev_err(&pdev->dev, "error when enabling power domains: %d\n", ret); + return ret; + } + + // the meaning of the bits in these two registers is sadly not documented, + // the set/clear operations are just copying what qcom does + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0"); + data->reg_mpm_sscaon_config0 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->reg_mpm_sscaon_config0)) { + ret = PTR_ERR(data->reg_mpm_sscaon_config0); + dev_err(&pdev->dev, "failed to ioremap mpm_sscaon_config0 (err: %d)\n", ret); + return ret; + } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0"); + data->reg_mpm_sscaon_config1 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->reg_mpm_sscaon_config1)) { + ret = PTR_ERR(data->reg_mpm_sscaon_config1); + dev_err(&pdev->dev, "failed to ioremap mpm_sscaon_config1 (err: %d)\n", ret); + return ret; + } + + data->ssc_bcr = devm_reset_control_get_exclusive(&pdev->dev, "ssc_bcr"); + if (IS_ERR(data->ssc_bcr)) { + ret = PTR_ERR(data->ssc_bcr); + dev_err(&pdev->dev, "failed to acquire reset: scc_bcr (err: %d)\n", ret); + return ret; + } + data->ssc_reset = devm_reset_control_get_exclusive(&pdev->dev, "ssc_reset"); + if (IS_ERR(data->ssc_reset)) { + ret = PTR_ERR(data->ssc_reset); + dev_err(&pdev->dev, "failed to acquire reset: ssc_reset: (err: %d)\n", ret); + return ret; + } + + data->xo_clk = devm_clk_get(&pdev->dev, "xo"); + if (IS_ERR(data->xo_clk)) { + ret = PTR_ERR(data->xo_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get clock: xo (err: %d)\n", ret); + return ret; + } + + data->aggre2_clk = devm_clk_get(&pdev->dev, "aggre2"); + if (IS_ERR(data->aggre2_clk)) { + ret = PTR_ERR(data->aggre2_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get clock: aggre2 (err: %d)\n", ret); + return ret; + } + + data->gcc_im_sleep_clk = devm_clk_get(&pdev->dev, "gcc_im_sleep"); + if (IS_ERR(data->gcc_im_sleep_clk)) { + ret = PTR_ERR(data->gcc_im_sleep_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get clock: gcc_im_sleep (err: %d)\n", ret); + return ret; + } + + data->aggre2_north_clk = devm_clk_get(&pdev->dev, "aggre2_north"); + if (IS_ERR(data->aggre2_north_clk)) { + ret = PTR_ERR(data->aggre2_north_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get clock: aggre2_north (err: %d)\n", ret); + return ret; + } + + data->ssc_xo_clk = devm_clk_get(&pdev->dev, "ssc_xo"); + if (IS_ERR(data->ssc_xo_clk)) { + ret = PTR_ERR(data->ssc_xo_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get clock: ssc_xo (err: %d)\n", ret); + return ret; + } + + data->ssc_ahbs_clk = devm_clk_get(&pdev->dev, "ssc_ahbs"); + if (IS_ERR(data->ssc_ahbs_clk)) { + ret = PTR_ERR(data->ssc_ahbs_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get clock: ssc_ahbs (err: %d)\n", ret); + return ret; + } + + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "qcom,halt-regs", 1, 0, + &halt_args); + if (ret < 0) { + dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); + return -EINVAL; + } + + data->halt_map = syscon_node_to_regmap(halt_args.np); + of_node_put(halt_args.np); + if (IS_ERR(data->halt_map)) + return PTR_ERR(data->halt_map); + + data->ssc_axi_halt = halt_args.args[0]; + + qcom_ssc_block_bus_init(&pdev->dev); + + return 0; +} + +static int qcom_ssc_block_bus_remove(struct platform_device *pdev) +{ + struct qcom_ssc_block_bus_data *data = platform_get_drvdata(pdev); + + qcom_ssc_block_bus_deinit(&pdev->dev); + + iounmap(data->reg_mpm_sscaon_config0); + iounmap(data->reg_mpm_sscaon_config1); + + qcom_ssc_block_bus_pds_disable(data->pds, data->num_pds); + qcom_ssc_block_bus_pds_detach(&pdev->dev, data->pds, data->num_pds); + pm_runtime_disable(&pdev->dev); + pm_clk_destroy(&pdev->dev); + + return 0; +} + +static const struct of_device_id qcom_ssc_block_bus_of_match[] = { + { .compatible = "qcom,ssc-block-bus", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, qcom_ssc_block_bus_of_match); + +static struct platform_driver qcom_ssc_block_bus_driver = { + .probe = qcom_ssc_block_bus_probe, + .remove = qcom_ssc_block_bus_remove, + .driver = { + .name = "qcom-ssc-block-bus", + .of_match_table = qcom_ssc_block_bus_of_match, + }, +}; + +module_platform_driver(qcom_ssc_block_bus_driver); + +MODULE_DESCRIPTION("A driver for handling the init sequence needed for accessing the SSC block on (some) qcom SoCs over AHB"); +MODULE_AUTHOR("Michael Srba "); +MODULE_LICENSE("GPL v2");