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Mon, 24 Jan 2022 03:18:35 -0800 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v3 1/4] dt-bindings: Add headers for Tegra234 I2C Date: Mon, 24 Jan 2022 16:48:14 +0530 Message-ID: <1643023097-5221-2-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com> References: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6266a1fd-e0fd-4e7e-7620-08d9df2b6453 X-MS-TrafficTypeDiagnostic: MWHPR12MB1503:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1186; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 869Qu0Bdv4hiAIGfoB/C4HvuRm/2u7ljn7y2/F6acn4wr5GgMH/whI0JsyX13vLhCyYGEztMySNPx/cN7nGkoyT5qohIE22RnJZ1s1XCg4vga2OnfU5xglbj+zoI3AODim96cSB/E1iXNATlpL5SC+VmwKRYBh+fvfOEg3pRbe5dNwft5U8y9mVJZOVyhNQ7GmcC0zx7Y9T8ji/6apgdhz0MgupXJ1TM/6M0EI+i5lxy72Hu08Mp+Fe8+RQ3YarEbbsg3QRyEIg5Pa6BYFZZePDqMe93bgxjJPJ85L5H1qoVSrmq0BkX8eZ4isQ+0K6tSU88J5GKQIWdCIOj+NFl6J27KE4rbjIOJq0MDGbrVmBEPlSoV5w8+7xM8tDXRCk14BK2Cop3oDKEqcm9BpO2qeu//rje9JJyJhc5bISNS/BvMcfYDYW9zFEbLWqofYxvZVF+HGEF5tUF6YDEDbFw5W+BB/QxAmCDRzsB4modyzbuZNvmjeYPKwg9/wwDX0MHOYQ5x4678wjByB9tx7ZdvhzPLQ/8wOrK5C0d5E6IhfxcTqDpQNaOrL9zJtS0SSHOwn6htk+uwA3N7KCI+MSbC8Vh2sTaor1CSnzOueIG8g2CsRfb9+g1BRByWSvyiu3Hm9xPImEUyU4SMfqTDiXWLOd5vyfVFxNJqs0EaJ8GiTvdqJhWv+3oiDLr7CLsvLF/P/T832xIXe28AsuYMw2lUTZbRTIcN/FA0WLcdJyN3DarHIR65Ph45jbnTwORz+7kI4ge6gQZ4HsgHiiy7acQBc08/k9mBq3FvvGcF5bKd8QAHyFyfKm4RTi9txWTRroSjaw+SUd/Ogm8lxACFyOcYg7HaisCgkKQajxRk9ZQh3E= X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:ErrorRetry; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(40470700004)(6666004)(186003)(8676002)(356005)(316002)(508600001)(26005)(107886003)(921005)(81166007)(36860700001)(110136005)(8936002)(5660300002)(86362001)(2906002)(82310400004)(4326008)(70206006)(426003)(2616005)(47076005)(36756003)(70586007)(7696005)(40460700003)(336012)(83380400001)(2101003)(36900700001)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2022 11:19:30.7696 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6266a1fd-e0fd-4e7e-7620-08d9df2b6453 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1503 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dt-bindings header files for I2C controllers for Tegra234 Signed-off-by: Akhil R --- include/dt-bindings/clock/tegra234-clock.h | 19 ++++++++++++++++++- include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8d7e66e..dc524e6 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -20,6 +20,24 @@ #define TEGRA234_CLK_EMC 31U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ +#define TEGRA234_CLK_I2C1 48U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ +#define TEGRA234_CLK_I2C2 49U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ +#define TEGRA234_CLK_I2C3 50U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ +#define TEGRA234_CLK_I2C4 51U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA234_CLK_I2C6 52U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ +#define TEGRA234_CLK_I2C7 53U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ +#define TEGRA234_CLK_I2C8 54U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ +#define TEGRA234_CLK_I2C9 55U +/** @brief PLLP clk output */ +#define TEGRA234_CLK_PLLP_OUT0 102U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ #define TEGRA234_CLK_SDMMC4 123U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ @@ -30,5 +48,4 @@ #define TEGRA234_CLK_PLLC4 237U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U - #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 50e13bc..2963259 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -10,6 +10,14 @@ * @brief Identifiers for Resets controllable by firmware * @{ */ +#define TEGRA234_RESET_I2C1 24U +#define TEGRA234_RESET_I2C2 29U +#define TEGRA234_RESET_I2C3 30U +#define TEGRA234_RESET_I2C4 31U +#define TEGRA234_RESET_I2C6 32U +#define TEGRA234_RESET_I2C7 33U +#define TEGRA234_RESET_I2C8 34U +#define TEGRA234_RESET_I2C9 35U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U From patchwork Mon Jan 24 11:18:15 2022 Content-Type: text/plain; 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Mon, 24 Jan 2022 03:18:44 -0800 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v3 2/4] arm64: tegra: Add Tegra234 I2C devicetree nodes Date: Mon, 24 Jan 2022 16:48:15 +0530 Message-ID: <1643023097-5221-3-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com> References: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a19edffa-137e-46a6-a4c3-08d9df2b4b28 X-MS-TrafficTypeDiagnostic: BN6PR12MB1554:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1079; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5Ya0mquiiiRhgAnFHdvUzJqAvNLYWNRxmnM48nTa9PF2G0JbRSChA/dm7sd0paAjA49r4+rDgaLXmHGVyw2AgybsmHuZZtFlvtqKKrjWy26X3shp0MgA5+kk8iXjON9SXsFka3mYDFkoJIj/nK49G3ZgHF2VabsPvdNBME61wspLcx54Wb15eNuufP4FCFM2p3tvMr+ZrQi/zBI+2eELUKmnpuwE/3eVKSOv8Wf+a1n2hsixj00ez2yEBdrp5DALFex2iZFS8Jt03z6D8yR5bsjekX9HYZIeJeaIw2jLOIkP6p/LKN8tcI6FLAuuTsIccJ37tntGnfHjYFADBAGzJzKPomvQCtbiHjfB3MI+XQBumPnOy0GYphFhjf3EFqVxap4HqB9QKCqEg2u/ZUv21xuHk1J6JB6UUWqrvocKSmXDuOpm5gpnqHIv+qzYIqY1Hm3XosbIJffifRw1yluM5HIR6OXY42pg1gi3SBq4N0XKp9HkndOcu1X87z3IigolrMDkpI4X7t2v47zEChFdiRESwTAeCM21ceIVLo6N3tFdXt9PNkaLzCwa0PV1HZtnKkNndO1t4/O15jfA9JSGIIZ0ZQ270S8/EfZ+DcLHNA6hyEAx8ZtTb3rXqxtEdcXdJwmp0E6c1+lMK36nbQVXF+KuDg3l1yRVeRn8/I9ZugjNhUeO+SR5syScm+iUGb4pDUIaY0cWxFhUEuqsYemi+tu55JJQ9SkiquhZNhFuQb6890bVIN3s0mRrBF8sG5Mq1RxI9Bjc1k20JUIAkd7s0tnc0IYzf38AEpWKzaGUJZZ4jJbn+FAaqHUPBgFweguIKZpIkmFoMmBKtDU9JEIXxhIJX3CcsD6YvtjXP08fXTs= X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(46966006)(40470700004)(36840700001)(8936002)(70206006)(921005)(47076005)(8676002)(70586007)(6666004)(356005)(107886003)(83380400001)(5660300002)(36860700001)(316002)(7696005)(36756003)(86362001)(4326008)(110136005)(186003)(508600001)(336012)(40460700003)(26005)(82310400004)(426003)(81166007)(2906002)(2616005)(36900700001)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2022 11:18:48.5928 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a19edffa-137e-46a6-a4c3-08d9df2b4b28 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1554 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree nodes for Tegra234 I2C controllers Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 121 +++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 6b6f1580..c686827 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -144,6 +144,96 @@ status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3160000 0x100>; + status = "disabled"; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C1 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C1>; + reset-names = "i2c"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3180000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C3 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C3>; + reset-names = "i2c"; + }; + + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3190000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C4 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C4>; + reset-names = "i2c"; + }; + + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31b0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C6 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C6>; + reset-names = "i2c"; + }; + + dp_aux_ch2_i2c: i2c@31c0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31c0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C7 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C7>; + reset-names = "i2c"; + }; + + dp_aux_ch3_i2c: i2c@31e0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31e0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C9 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C9>; + reset-names = "i2c"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; @@ -212,6 +302,37 @@ #mbox-cells = <2>; }; + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0xc240000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C2 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C2>; + reset-names = "i2c"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0xc250000 0x100>; + nvidia,hw-instance-id = <0x7>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C8 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C8>; + reset-names = "i2c"; + }; + rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; reg = <0x0c2a0000 0x10000>;