From patchwork Mon Jan 24 09:33:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jammy Huang X-Patchwork-Id: 534778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B803C433F5 for ; Mon, 24 Jan 2022 09:34:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233833AbiAXJea (ORCPT ); Mon, 24 Jan 2022 04:34:30 -0500 Received: from twspam01.aspeedtech.com ([211.20.114.71]:2603 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236464AbiAXJe2 (ORCPT ); Mon, 24 Jan 2022 04:34:28 -0500 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 20O9QV9m054147; Mon, 24 Jan 2022 17:26:31 +0800 (GMT-8) (envelope-from jammy_huang@aspeedtech.com) Received: from JammyHuang-PC.aspeed.com (192.168.2.115) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 24 Jan 2022 17:33:48 +0800 From: Jammy Huang To: , , , , , , , , Subject: [PATCH v3 2/4] media: aspeed: Use FIELD_GET to improve readability Date: Mon, 24 Jan 2022 17:33:43 +0800 Message-ID: <20220124093345.3935-3-jammy_huang@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220124093345.3935-1-jammy_huang@aspeedtech.com> References: <20220124093345.3935-1-jammy_huang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.115] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 20O9QV9m054147 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use the bitfield macro FIELD_GET, and GENMASK to do the shift and mask in one go for reg values. Signed-off-by: Jammy Huang Reviewed-by: Joel Stanley --- v3: - no update v2: - Put some codes on one line --- drivers/media/platform/aspeed-video.c | 31 +++++++++++---------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c index d5f77b205175..c241038ee27c 100644 --- a/drivers/media/platform/aspeed-video.c +++ b/drivers/media/platform/aspeed-video.c @@ -156,26 +156,22 @@ #define VE_SRC_LR_EDGE_DET_NO_H BIT(13) #define VE_SRC_LR_EDGE_DET_NO_DISP BIT(14) #define VE_SRC_LR_EDGE_DET_NO_CLK BIT(15) -#define VE_SRC_LR_EDGE_DET_RT_SHF 16 -#define VE_SRC_LR_EDGE_DET_RT GENMASK(27, VE_SRC_LR_EDGE_DET_RT_SHF) +#define VE_SRC_LR_EDGE_DET_RT GENMASK(27, 16) #define VE_SRC_LR_EDGE_DET_INTERLACE BIT(31) #define VE_SRC_TB_EDGE_DET 0x094 #define VE_SRC_TB_EDGE_DET_TOP GENMASK(12, 0) -#define VE_SRC_TB_EDGE_DET_BOT_SHF 16 -#define VE_SRC_TB_EDGE_DET_BOT GENMASK(28, VE_SRC_TB_EDGE_DET_BOT_SHF) +#define VE_SRC_TB_EDGE_DET_BOT GENMASK(28, 16) #define VE_MODE_DETECT_STATUS 0x098 #define VE_MODE_DETECT_H_PERIOD GENMASK(11, 0) -#define VE_MODE_DETECT_V_LINES_SHF 16 -#define VE_MODE_DETECT_V_LINES GENMASK(27, VE_MODE_DETECT_V_LINES_SHF) +#define VE_MODE_DETECT_V_LINES GENMASK(27, 16) #define VE_MODE_DETECT_STATUS_VSYNC BIT(28) #define VE_MODE_DETECT_STATUS_HSYNC BIT(29) #define VE_SYNC_STATUS 0x09c #define VE_SYNC_STATUS_HSYNC GENMASK(11, 0) -#define VE_SYNC_STATUS_VSYNC_SHF 16 -#define VE_SYNC_STATUS_VSYNC GENMASK(27, VE_SYNC_STATUS_VSYNC_SHF) +#define VE_SYNC_STATUS_VSYNC GENMASK(27, 16) #define VE_H_TOTAL_PIXELS 0x0A0 @@ -988,23 +984,20 @@ static void aspeed_video_get_resolution(struct aspeed_video *video) sync = aspeed_video_read(video, VE_SYNC_STATUS); htotal = aspeed_video_read(video, VE_H_TOTAL_PIXELS); - video->frame_bottom = (src_tb_edge & VE_SRC_TB_EDGE_DET_BOT) >> - VE_SRC_TB_EDGE_DET_BOT_SHF; - video->frame_top = src_tb_edge & VE_SRC_TB_EDGE_DET_TOP; + video->frame_bottom = FIELD_GET(VE_SRC_TB_EDGE_DET_BOT, src_tb_edge); + video->frame_top = FIELD_GET(VE_SRC_TB_EDGE_DET_TOP, src_tb_edge); det->vfrontporch = video->frame_top; - det->vbackporch = ((mds & VE_MODE_DETECT_V_LINES) >> - VE_MODE_DETECT_V_LINES_SHF) - video->frame_bottom; - det->vsync = (sync & VE_SYNC_STATUS_VSYNC) >> - VE_SYNC_STATUS_VSYNC_SHF; + det->vbackporch = FIELD_GET(VE_MODE_DETECT_V_LINES, mds) - + video->frame_bottom; + det->vsync = FIELD_GET(VE_SYNC_STATUS_VSYNC, sync); if (video->frame_top > video->frame_bottom) continue; - video->frame_right = (src_lr_edge & VE_SRC_LR_EDGE_DET_RT) >> - VE_SRC_LR_EDGE_DET_RT_SHF; - video->frame_left = src_lr_edge & VE_SRC_LR_EDGE_DET_LEFT; + video->frame_right = FIELD_GET(VE_SRC_LR_EDGE_DET_RT, src_lr_edge); + video->frame_left = FIELD_GET(VE_SRC_LR_EDGE_DET_LEFT, src_lr_edge); det->hfrontporch = video->frame_left; det->hbackporch = htotal - video->frame_right; - det->hsync = sync & VE_SYNC_STATUS_HSYNC; + det->hsync = FIELD_GET(VE_SYNC_STATUS_HSYNC, sync); if (video->frame_left > video->frame_right) continue; From patchwork Mon Jan 24 09:33:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jammy Huang X-Patchwork-Id: 534776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE309C433EF for ; Mon, 24 Jan 2022 09:36:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229629AbiAXJgc (ORCPT ); Mon, 24 Jan 2022 04:36:32 -0500 Received: from twspam01.aspeedtech.com ([211.20.114.71]:16675 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232440AbiAXJee (ORCPT ); Mon, 24 Jan 2022 04:34:34 -0500 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 20O9QVlT054148; Mon, 24 Jan 2022 17:26:31 +0800 (GMT-8) (envelope-from jammy_huang@aspeedtech.com) Received: from JammyHuang-PC.aspeed.com (192.168.2.115) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 24 Jan 2022 17:33:48 +0800 From: Jammy Huang To: , , , , , , , , Subject: [PATCH v3 4/4] media: aspeed: Fix timing polarity incorrect Date: Mon, 24 Jan 2022 17:33:45 +0800 Message-ID: <20220124093345.3935-5-jammy_huang@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220124093345.3935-1-jammy_huang@aspeedtech.com> References: <20220124093345.3935-1-jammy_huang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.115] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 20O9QVlT054148 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This is a workaround for polarity detection unstable. Because h/v sync polarity got from VR098 could be wrong, we try to use ast SoC's characteristic to confirm sync polarity. In ast SoC's design, sync value got by VR09C counts from sync's rising edge, which means sync value = bp + active + fp if negative polarity. Thus, sync value would be larger than de if negative. Ex. 1920x1200@60 VR098: c4d3efff, VR09C: 04cc001f v-total = 0x4D3 (VR098[27:16]) = 1235 v-sync = 0x4CC (VR09C[27:16]) = 1228 Signed-off-by: Jammy Huang --- v3: - Use active rather than 'total/2' as critera for workaround v2: - Use 'total/2' rather than 'total<<1' - Update comment --- drivers/media/platform/aspeed-video.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c index 7e988cd05161..a135a31b4234 100644 --- a/drivers/media/platform/aspeed-video.c +++ b/drivers/media/platform/aspeed-video.c @@ -985,6 +985,20 @@ static void aspeed_video_get_timings(struct aspeed_video *v, vsync = FIELD_GET(VE_SYNC_STATUS_VSYNC, sync); hsync = FIELD_GET(VE_SYNC_STATUS_HSYNC, sync); + /* + * This is a workaround for polarity detection. + * Because ast-soc counts sync from sync's rising edge, the reg value + * of sync would be larger than video's active area if negative. + */ + if (vsync > det->height) + det->polarities &= ~V4L2_DV_VSYNC_POS_POL; + else + det->polarities |= V4L2_DV_VSYNC_POS_POL; + if (hsync > det->width) + det->polarities &= ~V4L2_DV_HSYNC_POS_POL; + else + det->polarities |= V4L2_DV_HSYNC_POS_POL; + if (det->polarities & V4L2_DV_VSYNC_POS_POL) { det->vbackporch = v->frame_top - vsync; det->vfrontporch = vtotal - v->frame_bottom;