From patchwork Fri Jan 28 09:07:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 538027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4663DC433EF for ; Fri, 28 Jan 2022 09:09:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231432AbiA1JJj (ORCPT ); Fri, 28 Jan 2022 04:09:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347485AbiA1JHm (ORCPT ); Fri, 28 Jan 2022 04:07:42 -0500 Received: from albert.telenet-ops.be (albert.telenet-ops.be [IPv6:2a02:1800:110:4::f00:1a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D020C061747 for ; Fri, 28 Jan 2022 01:07:42 -0800 (PST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:3999:e79d:cb59:f2ec]) by albert.telenet-ops.be with bizsmtp id o97e2600p04fKGS0697fYU; Fri, 28 Jan 2022 10:07:40 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1nDNEI-00BjuV-NZ; Fri, 28 Jan 2022 10:07:38 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1nDNEH-005psG-W2; Fri, 28 Jan 2022 10:07:37 +0100 From: Geert Uytterhoeven To: Daniel Lezcano , Thomas Gleixner , Palmer Dabbelt , Paul Walmsley , Anup Patel Cc: Rob Herring , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Geert Uytterhoeven , Rob Herring Subject: [PATCH v4 1/2] dt-bindings: timer: sifive,clint: Fix number of interrupts Date: Fri, 28 Jan 2022 10:07:35 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The number of interrupts lacks an upper bound, thus assuming one, causing properly grouped "interrupts-extended" properties to be flagged as an error by "make dtbs_check". Fix this by adding the missing "maxItems", using the architectural maximum of 4095 interrupts. Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring --- v4: - Use architectural maximum instead of practical maximum of 10, v3: - Add Acked-by, v2: - Split in two patches, - Improve patch description and document limit rationale. --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 8d5f4687add9e81e..fe4b73c3f269fc0f 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -44,6 +44,7 @@ properties: interrupts-extended: minItems: 1 + maxItems: 4095 additionalProperties: false From patchwork Fri Jan 28 09:07:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 537739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E79CC433F5 for ; Fri, 28 Jan 2022 09:09:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237622AbiA1JJj (ORCPT ); Fri, 28 Jan 2022 04:09:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347477AbiA1JHm (ORCPT ); Fri, 28 Jan 2022 04:07:42 -0500 Received: from albert.telenet-ops.be (albert.telenet-ops.be [IPv6:2a02:1800:110:4::f00:1a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C471C061714 for ; Fri, 28 Jan 2022 01:07:42 -0800 (PST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:3999:e79d:cb59:f2ec]) by albert.telenet-ops.be with bizsmtp id o97e2600Y04fKGS0697eYM; Fri, 28 Jan 2022 10:07:40 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1nDNEI-00BjuW-Fe; Fri, 28 Jan 2022 10:07:38 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1nDNEI-005psK-0U; Fri, 28 Jan 2022 10:07:38 +0100 From: Geert Uytterhoeven To: Daniel Lezcano , Thomas Gleixner , Palmer Dabbelt , Paul Walmsley , Anup Patel Cc: Rob Herring , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Geert Uytterhoeven , Rob Herring Subject: [PATCH v4 2/2] dt-bindings: timer: sifive,clint: Group interrupt tuples Date: Fri, 28 Jan 2022 10:07:36 +0100 Message-Id: <62bf4ee6613550c07a99d4bd226ab0d33acae4c4.1643360652.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To improve human readability and enable automatic validation, the tuples in "interrupts-extended" properties should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring --- v4: - Add Reviewed-by (this time for real ;-), v3: - Add Reviewed-by, v2: - Split in two patches. --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index fe4b73c3f269fc0f..e64f46339079fa3f 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -57,10 +57,10 @@ examples: - | timer@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; - interrupts-extended = <&cpu1intc 3 &cpu1intc 7 - &cpu2intc 3 &cpu2intc 7 - &cpu3intc 3 &cpu3intc 7 - &cpu4intc 3 &cpu4intc 7>; + interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>, + <&cpu2intc 3>, <&cpu2intc 7>, + <&cpu3intc 3>, <&cpu3intc 7>, + <&cpu4intc 3>, <&cpu4intc 7>; reg = <0x2000000 0x10000>; }; ...