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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id l7-v6si33996649ybo.167.2018.11.23.06.49.19 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 06:49:19 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CESSUrP+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52764 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQClj-0003k7-08 for patch@linaro.org; Fri, 23 Nov 2018 09:49:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43767) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCif-0007yS-Qu for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCia-00036F-Pu for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:09 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:39293) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCia-00035H-35 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:04 -0500 Received: by mail-wm1-x344.google.com with SMTP id u13-v6so12247957wmc.4 for ; Fri, 23 Nov 2018 06:46:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fux7GoiV8l3FnF1Vyj9P8uU4timqrhfpmRWnGlzFzqM=; b=CESSUrP+KRFaLAPVT6X/RRGzPEY8pFM3Q53qJELQ9eIQkSg2FgI/zpc5c9bH1+VjFa kTxkm5O7Mh8xBOF1sskFOqJf1jJGu1K7exMd8+ptMHrZY1ff6z6OzbbcAtYTMSJmddgc P4WGhwPbr0Hf1LnFA2Hq1jxcgP8jbQ9hb3HMc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fux7GoiV8l3FnF1Vyj9P8uU4timqrhfpmRWnGlzFzqM=; b=tEaqmWGBG1cKWrKz2C7vTRIksZshfmCx3gHc5LnHAGUmT/YU6lLRRpWYknAi3Mj3IQ afGI6M48S/GEnCGv9qlxfvxcXthTo/g6i8eQBXInToFhGxrak6bVWsufT+gQsViW4ZcM XH3T1XrZnQobSzrMMy910qw/Whtolc0IlIqtv1ifvpThLHbpZcJzWaePIbRUT6NMBuM1 eJzFHDZFqt9YM6S5BC7GXdO4b8xyb34nJenRuvbfxFW10cbB7md3RytRyKT36v6hblw+ meljtUPVwXLILE1iwG6r5q+Giri9w/Jnve5I+Amigk3pvNUS5w2NVLiDtKRmra40ML+E XmlQ== X-Gm-Message-State: AGRZ1gIP92F9pOtUmcfEzbcbUYJMIq3DqUmtzMllIRvx5mHSbbOQ0/Nv /gsTlm0MJ4h/jAfvaBnZmUgKFVHb4heaiw== X-Received: by 2002:a1c:af89:: with SMTP id y131mr13884953wme.137.1542984361904; Fri, 23 Nov 2018 06:46:01 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:22 +0100 Message-Id: <20181123144558.5048-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 v2 01/37] tcg/i386: Always use %ebp for TCG_AREG0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For x86_64, this can result in smaller code when manipulating TCG_TYPE_I32, as we can omit a REX prefix. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) -- 2.17.2 Reviewed-by: Alex Bennée diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 9fdf37f23c..7488c3d869 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -84,6 +84,8 @@ typedef enum { TCG_REG_RBP = TCG_REG_EBP, TCG_REG_RSI = TCG_REG_ESI, TCG_REG_RDI = TCG_REG_EDI, + + TCG_AREG0 = TCG_REG_EBP, } TCGReg; /* used for function call generation */ @@ -194,12 +196,6 @@ extern bool have_avx2; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32) -#if TCG_TARGET_REG_BITS == 64 -# define TCG_AREG0 TCG_REG_R14 -#else -# define TCG_AREG0 TCG_REG_EBP -#endif - static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } From patchwork Fri Nov 23 14:45:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151877 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2207727ljp; Fri, 23 Nov 2018 06:46:47 -0800 (PST) X-Google-Smtp-Source: AFSGD/XmaqW4Q8Cx8ITgsqGl8EWnBgrtDmUItjgLtrMuN00JSnBOwriFT8Bum1IN3+Q71DQj9vJP X-Received: by 2002:a37:694:: with SMTP id 142mr14275882qkg.98.1542984407102; Fri, 23 Nov 2018 06:46:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984407; cv=none; d=google.com; s=arc-20160816; b=RxDC3aUB6B6PBPVFIdSDPSgBRHxLoPlDM02zJ1c70+AkNu/OHnzWgjvj3QMnQN0dyS swqd83uDpWT6NqBxFGqdhnmuAROc9i6zgQGKZdXk5mn4/tugJOwFsl7nLvBdLQZrXL/l yoVfEnNJyQ4UnyRUhwihKQLmaYsaDmMg0TK92ZvYRfIue04+c+V10asy9pN6ff5JKfkj x+Z0Np4cnsfoBQeoL8UzAW1YazjoXSJnuIH99xGkjCF3ZyRBstuIRMvFx832hg/qut0t h+e1LYyFjCmwurQxb8Ct1EN4KIrrmPY8PWUeMoLR7P40xSedDbPpgu1C3KYbyglz0Mpy 9vTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=yNQmwVUAvqPZBQpEvZxNr8bwL4aHF0jtNAxTMDvMNMk=; b=qxgikkTT+epe/r4tN1tNdk63rkKOxQvS3ltInDYcQiJheA6eb8fmJQTDlhVroModTi I4nEkcHe7Hgw1jiXzeP6X09u3FqhUnZh2WqmwfqWqvy4uxOCD+siuAz5qg2TT5L8DzOa oHadi1fBpO5KejU4e/YNZkLjiGIYXaPkJ/+3AYLdbCq5HddTlItx8uMn16mo4IGDntJQ 0Ae6U960dWYsehBFm4PTAKUlpw3ae/Jf9XwgCIiWbkh6uB+BY3gpsxFxdPrPJaKLl5ib zloqMLHV5hpa18PQ3sf+G85Wzrh/AuYNMnb4SsidNq5gg1Hg8Tsb5upcRjJ6Ez2LSI2G 8Y3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=auygdKAI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.0 v2 02/37] tcg/i386: Move TCG_REG_CALL_STACK from define to enum X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.2 Reviewed-by: Alex Bennée diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7488c3d869..2441658865 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -86,10 +86,10 @@ typedef enum { TCG_REG_RDI = TCG_REG_EDI, TCG_AREG0 = TCG_REG_EBP, + TCG_REG_CALL_STACK = TCG_REG_ESP } TCGReg; /* used for function call generation */ -#define TCG_REG_CALL_STACK TCG_REG_ESP #define TCG_TARGET_STACK_ALIGN 16 #if defined(_WIN64) #define TCG_TARGET_CALL_STACK_OFFSET 32 From patchwork Fri Nov 23 14:45:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151889 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2217665ljp; Fri, 23 Nov 2018 06:55:54 -0800 (PST) X-Google-Smtp-Source: AFSGD/WBDL7HK7RtZlMnL8iTbdJ7TzXDoY7mrEh25VCajk6OIlmJOgGnYApes2dB809ly0qQwo4W X-Received: by 2002:a25:3487:: with SMTP id b129-v6mr16272888yba.191.1542984954055; Fri, 23 Nov 2018 06:55:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984954; cv=none; d=google.com; s=arc-20160816; b=lDBeWcVxg5uoay8RtXAm9RrIyMaf0iy6MlqtCOEfLmN1VOKMm7Jzq7eDbJQ0nSuGMw hySXtCe3jzOUhjunOlKFyO6mdz+Kol2eD9+S2VfTUklF/PxBt05Clq/Yt8rDmHo6L0xc Dp/xytYX5HB1nB8GLDklEQpBIzEhSAkSN2XxgDTAacyRAtvj1RPNZJ4xSQKscaHP/zBR akVPtILDSrvu+VFB2MdodrbX6KWR26zu/Ey/GnoX6yUt7m9opr0p+aFA2q3tPXWPhGIG +AsDH1rYyZL14Ssih47LAP1fb1LVPXN7UBuCqWlrhCy0Gax7i+Y0vw5suZxJsNJjNldM xFBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=U79fIgS0hejBQL/zjUbT562kgbBz2dY+Sn5LbZq038M=; b=ZZVnvkeInSOkY8NDMlYMdVCZgF6kwsOKGeNYtyXbPZU/49R6mdV0G3GsHDzmt6S0Ga /iN4VQxlGwhBvKW5pnCoW/PxKczBTlH2bTgZo9iUE6N2B1vMZ5SnN6GFjiwgv49ZfpfJ RKJnEB/3SgQ1BbowUR+u4R4z45DXbQ8wdsaLPQIGrM+AjLTn8eSC+/unjMxG0/rmqCzE q52BmEamLwrhj89EUc+s5J8G17Rryycb62C3X7v9yoWPbGctXljSnKHr5GQfDqRn959y Uf/I1bTWNpPfaDipApdLKNykNOK7GkWFyD9kPZChVRIar+1u06SABux/unLHut3HmHfj efNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YTpMFc+r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 v2 03/37] tcg: Return success from patch_reloc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This moves the assert for success from inside patch_reloc to outside patch_reloc. This touches all tcg backends. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 44 ++++++++++++++------------------- tcg/arm/tcg-target.inc.c | 26 +++++++++----------- tcg/i386/tcg-target.inc.c | 17 +++++++------ tcg/mips/tcg-target.inc.c | 29 +++++++++------------- tcg/ppc/tcg-target.inc.c | 47 ++++++++++++++++++++++-------------- tcg/s390/tcg-target.inc.c | 37 +++++++++++++++++++--------- tcg/sparc/tcg-target.inc.c | 13 ++++++---- tcg/tcg-pool.inc.c | 5 +++- tcg/tcg.c | 8 +++--- tcg/tci/tcg-target.inc.c | 3 ++- 10 files changed, 125 insertions(+), 104 deletions(-) -- 2.17.2 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 083592a4d7..30091f6a69 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -78,48 +78,40 @@ static const int tcg_target_call_oarg_regs[1] = { #define TCG_REG_GUEST_BASE TCG_REG_X28 #endif -static inline void reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static inline bool reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target) { ptrdiff_t offset = target - code_ptr; - tcg_debug_assert(offset == sextract64(offset, 0, 26)); - /* read instruction, mask away previous PC_REL26 parameter contents, - set the proper offset, then write back the instruction. */ - *code_ptr = deposit32(*code_ptr, 0, 26, offset); + if (offset == sextract64(offset, 0, 26)) { + /* read instruction, mask away previous PC_REL26 parameter contents, + set the proper offset, then write back the instruction. */ + *code_ptr = deposit32(*code_ptr, 0, 26, offset); + return true; + } + return false; } -static inline void reloc_pc26_atomic(tcg_insn_unit *code_ptr, - tcg_insn_unit *target) +static inline bool reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target) { ptrdiff_t offset = target - code_ptr; - tcg_insn_unit insn; - tcg_debug_assert(offset == sextract64(offset, 0, 26)); - /* read instruction, mask away previous PC_REL26 parameter contents, - set the proper offset, then write back the instruction. */ - insn = atomic_read(code_ptr); - atomic_set(code_ptr, deposit32(insn, 0, 26, offset)); + if (offset == sextract64(offset, 0, 19)) { + *code_ptr = deposit32(*code_ptr, 5, 19, offset); + return true; + } + return false; } -static inline void reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target) -{ - ptrdiff_t offset = target - code_ptr; - tcg_debug_assert(offset == sextract64(offset, 0, 19)); - *code_ptr = deposit32(*code_ptr, 5, 19, offset); -} - -static inline void patch_reloc(tcg_insn_unit *code_ptr, int type, +static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(addend == 0); switch (type) { case R_AARCH64_JUMP26: case R_AARCH64_CALL26: - reloc_pc26(code_ptr, (tcg_insn_unit *)value); - break; + return reloc_pc26(code_ptr, (tcg_insn_unit *)value); case R_AARCH64_CONDBR19: - reloc_pc19(code_ptr, (tcg_insn_unit *)value); - break; + return reloc_pc19(code_ptr, (tcg_insn_unit *)value); default: - tcg_abort(); + g_assert_not_reached(); } } diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index e1fbf465cb..80d174ef44 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -187,27 +187,23 @@ static const uint8_t tcg_cond_to_arm_cond[] = { [TCG_COND_GTU] = COND_HI, }; -static inline void reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target) { ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; - *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff); + if (offset == sextract32(offset, 0, 24)) { + *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff); + return true; + } + return false; } -static inline void reloc_pc24_atomic(tcg_insn_unit *code_ptr, tcg_insn_unit *target) -{ - ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; - tcg_insn_unit insn = atomic_read(code_ptr); - tcg_debug_assert(offset == sextract32(offset, 0, 24)); - atomic_set(code_ptr, deposit32(insn, 0, 24, offset)); -} - -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(addend == 0); if (type == R_ARM_PC24) { - reloc_pc24(code_ptr, (tcg_insn_unit *)value); + return reloc_pc24(code_ptr, (tcg_insn_unit *)value); } else if (type == R_ARM_PC13) { intptr_t diff = value - (uintptr_t)(code_ptr + 2); tcg_insn_unit insn = *code_ptr; @@ -218,10 +214,9 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, if (!u) { diff = -diff; } - } else { + } else if (diff >= 0x1000 && diff < 0x100000) { int rd = extract32(insn, 12, 4); int rt = rd == TCG_REG_PC ? TCG_REG_TMP : rd; - assert(diff >= 0x1000 && diff < 0x100000); /* add rt, pc, #high */ *code_ptr++ = ((insn & 0xf0000000) | (1 << 25) | ARITH_ADD | (TCG_REG_PC << 16) | (rt << 12) @@ -230,10 +225,13 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, insn = deposit32(insn, 12, 4, rt); diff &= 0xfff; u = 1; + } else { + return false; } insn = deposit32(insn, 23, 1, u); insn = deposit32(insn, 0, 12, diff); *code_ptr = insn; + return true; } else { g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 436195894b..4f66a0c5ae 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -167,29 +167,32 @@ static bool have_lzcnt; static tcg_insn_unit *tb_ret_addr; -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { value += addend; - switch(type) { + + switch (type) { case R_386_PC32: value -= (uintptr_t)code_ptr; if (value != (int32_t)value) { - tcg_abort(); + return false; } /* FALLTHRU */ case R_386_32: tcg_patch32(code_ptr, value); - break; + return true; + case R_386_PC8: value -= (uintptr_t)code_ptr; if (value != (int8_t)value) { - tcg_abort(); + return false; } tcg_patch8(code_ptr, value); - break; + return true; + default: - tcg_abort(); + g_assert_not_reached(); } } diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index cff525373b..e59c66b607 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -144,36 +144,29 @@ static tcg_insn_unit *bswap32_addr; static tcg_insn_unit *bswap32u_addr; static tcg_insn_unit *bswap64_addr; -static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc16_cond(tcg_insn_unit *pc, tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic. */ ptrdiff_t disp = target - (pc + 1); - tcg_debug_assert(disp == (int16_t)disp); - return disp & 0xffff; + if (disp == (int16_t)disp) { + *pc = deposit32(*pc, 0, 16, disp); + return true; + } else { + return false; + } } -static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) { - *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); + tcg_debug_assert(reloc_pc16_cond(pc, target)); } -static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0); - return ((uintptr_t)target >> 2) & 0x3ffffff; -} - -static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target)); -} - -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(type == R_MIPS_PC16); tcg_debug_assert(addend == 0); - reloc_pc16(code_ptr, (tcg_insn_unit *)value); + return reloc_pc16_cond(code_ptr, (tcg_insn_unit *)value); } #define TCG_CT_CONST_ZERO 0x100 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index c2f729ee8f..656a9ff603 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -186,16 +186,14 @@ static inline bool in_range_b(tcg_target_long target) return target == sextract64(target, 0, 26); } -static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc24_cond(tcg_insn_unit *pc, tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); - tcg_debug_assert(in_range_b(disp)); - return disp & 0x3fffffc; -} - -static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target); + if (in_range_b(disp)) { + *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc); + return true; + } + return false; } static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) @@ -205,10 +203,22 @@ static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) return disp & 0xfffc; } +static bool reloc_pc14_cond(tcg_insn_unit *pc, tcg_insn_unit *target) +{ + ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); + if (disp == (int16_t) disp) { + *pc = (*pc & ~0xfffc) | (disp & 0xfffc); + return true; + } + return false; +} + +#ifdef CONFIG_SOFTMMU static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target) { - *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target); + tcg_debug_assert(reloc_pc14_cond(pc, target)); } +#endif static inline void tcg_out_b_noaddr(TCGContext *s, int insn) { @@ -525,7 +535,7 @@ static const uint32_t tcg_to_isel[] = { [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), }; -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_insn_unit *target; @@ -536,11 +546,9 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, switch (type) { case R_PPC_REL14: - reloc_pc14(code_ptr, target); - break; + return reloc_pc14_cond(code_ptr, target); case R_PPC_REL24: - reloc_pc24(code_ptr, target); - break; + return reloc_pc24_cond(code_ptr, target); case R_PPC_ADDR16: /* We are abusing this relocation type. This points to a pair of insns, addis + load. If the displacement is small, we @@ -552,11 +560,14 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, } else { int16_t lo = value; int hi = value - lo; - assert(hi + lo == value); - code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); - code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); + if (hi + lo == value) { + code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); + code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); + } else { + return false; + } } - break; + return true; default: g_assert_not_reached(); } diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 17c435ade5..a8d72dd630 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -366,7 +366,7 @@ static void * const qemu_st_helpers[16] = { static tcg_insn_unit *tb_ret_addr; uint64_t s390_facilities; -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { intptr_t pcrel2; @@ -377,22 +377,35 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, switch (type) { case R_390_PC16DBL: - assert(pcrel2 == (int16_t)pcrel2); - tcg_patch16(code_ptr, pcrel2); + if (pcrel2 == (int16_t)pcrel2) { + tcg_patch16(code_ptr, pcrel2); + return true; + } break; case R_390_PC32DBL: - assert(pcrel2 == (int32_t)pcrel2); - tcg_patch32(code_ptr, pcrel2); + if (pcrel2 == (int32_t)pcrel2) { + tcg_patch32(code_ptr, pcrel2); + return true; + } break; case R_390_20: - assert(value == sextract64(value, 0, 20)); - old = *(uint32_t *)code_ptr & 0xf00000ff; - old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); - tcg_patch32(code_ptr, old); + if (value == sextract64(value, 0, 20)) { + old = *(uint32_t *)code_ptr & 0xf00000ff; + old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); + tcg_patch32(code_ptr, old); + return true; + } break; default: g_assert_not_reached(); } + return false; +} + +static void patch_reloc_force(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + tcg_debug_assert(patch_reloc(code_ptr, type, value, addend)); } /* parse target specific constraints */ @@ -1618,7 +1631,8 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) TCGMemOpIdx oi = lb->oi; TCGMemOp opc = get_memop(oi); - patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2); + patch_reloc_force(lb->label_ptr[0], R_390_PC16DBL, + (intptr_t)s->code_ptr, 2); tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS == 64) { @@ -1639,7 +1653,8 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) TCGMemOpIdx oi = lb->oi; TCGMemOp opc = get_memop(oi); - patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2); + patch_reloc_force(lb->label_ptr[0], R_390_PC16DBL, + (intptr_t)s->code_ptr, 2); tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS == 64) { diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 04bdc3df5e..111f3312d3 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -291,32 +291,34 @@ static inline int check_fit_i32(int32_t val, unsigned int bits) # define check_fit_ptr check_fit_i32 #endif -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { uint32_t insn = *code_ptr; intptr_t pcrel; + bool ret; value += addend; pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); switch (type) { case R_SPARC_WDISP16: - assert(check_fit_ptr(pcrel >> 2, 16)); + ret = check_fit_ptr(pcrel >> 2, 16); insn &= ~INSN_OFF16(-1); insn |= INSN_OFF16(pcrel); break; case R_SPARC_WDISP19: - assert(check_fit_ptr(pcrel >> 2, 19)); + ret = check_fit_ptr(pcrel >> 2, 19); insn &= ~INSN_OFF19(-1); insn |= INSN_OFF19(pcrel); break; case R_SPARC_13: /* Note that we're abusing this reloc type for our own needs. */ + ret = true; if (!check_fit_ptr(value, 13)) { int adj = (value > 0 ? 0xff8 : -0x1000); value -= adj; - assert(check_fit_ptr(value, 13)); + ret = check_fit_ptr(value, 13); *code_ptr++ = (ARITH_ADD | INSN_RD(TCG_REG_T2) | INSN_RS1(TCG_REG_TB) | INSN_IMM13(adj)); insn ^= INSN_RS1(TCG_REG_TB) ^ INSN_RS1(TCG_REG_T2); @@ -328,12 +330,13 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, /* Note that we're abusing this reloc type for our own needs. */ code_ptr[0] = deposit32(code_ptr[0], 0, 22, value >> 10); code_ptr[1] = deposit32(code_ptr[1], 0, 10, value); - return; + return value == (intptr_t)(uint32_t)value; default: g_assert_not_reached(); } *code_ptr = insn; + return ret; } /* parse target specific constraints */ diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c index 7af5513ff3..ab8f6df8b0 100644 --- a/tcg/tcg-pool.inc.c +++ b/tcg/tcg-pool.inc.c @@ -140,6 +140,8 @@ static bool tcg_out_pool_finalize(TCGContext *s) for (; p != NULL; p = p->next) { size_t size = sizeof(tcg_target_ulong) * p->nlong; + bool ok; + if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) { if (unlikely(a > s->code_gen_highwater)) { return false; @@ -148,7 +150,8 @@ static bool tcg_out_pool_finalize(TCGContext *s) a += size; l = p; } - patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend); + ok = patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend); + tcg_debug_assert(ok); } s->code_ptr = a; diff --git a/tcg/tcg.c b/tcg/tcg.c index e85133ef05..54f1272187 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -66,7 +66,7 @@ static void tcg_target_init(TCGContext *s); static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); static void tcg_target_qemu_prologue(TCGContext *s); -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend); /* The CIE and FDE header definitions will be common to all hosts. */ @@ -268,7 +268,8 @@ static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, /* FIXME: This may break relocations on RISC targets that modify instruction fields in place. The caller may not have written the initial value. */ - patch_reloc(code_ptr, type, l->u.value, addend); + bool ok = patch_reloc(code_ptr, type, l->u.value, addend); + tcg_debug_assert(ok); } else { /* add a new relocation entry */ r = tcg_malloc(sizeof(TCGRelocation)); @@ -288,7 +289,8 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) tcg_debug_assert(!l->has_value); for (r = l->u.first_reloc; r != NULL; r = r->next) { - patch_reloc(r->ptr, r->type, value, r->addend); + bool ok = patch_reloc(r->ptr, r->type, value, r->addend); + tcg_debug_assert(ok); } l->has_value = 1; diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index 62ed097254..0015a98485 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -369,7 +369,7 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { }; #endif -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { /* tcg_out_reloc always uses the same type, addend. */ @@ -381,6 +381,7 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, } else { tcg_patch64(code_ptr, value); } + return true; } /* Parse target specific constraints. */ From patchwork Fri Nov 23 14:45:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151883 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2213920ljp; Fri, 23 Nov 2018 06:52:26 -0800 (PST) X-Google-Smtp-Source: AFSGD/WQMlTxbklOrVIgsHOUSEPBUtqM3iGNN17zfD33wv8gnFJKbSwpG/RnhHERH++lX0WAh0s9 X-Received: by 2002:a25:4bc4:: with SMTP id y187-v6mr15935367yba.264.1542984746526; Fri, 23 Nov 2018 06:52:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984746; cv=none; d=google.com; s=arc-20160816; b=Ndh8TpCl63aniILSZYgXpr71Y9fJbyVh91+ZLYpWMQx0RvcjuWgWkJadPw0oc4AD7F qUXovxGKbdR1A/swDuBFducldRWU7K5a7bLSFegt/HqhEEzsfHGOV+AVh5Zy/WS1Ys2I lCFtK9J3IY0ieMn5PKzf49OYd0Oumn3IBZAHsNWCVIe8CbiEHwsVV92/xo8uRwYywXBM E2mffvNZWbSuSPUh23ZxC8kasBc8txa+Wejy/w+nF2tOfv9klSL4EYw6vY7zpyqhJ1M/ iVUWxzRsySNgVIhITgFEsBvlI9UwRXO5u0n3+mHKTgzZS4p1Lbj4sKF4Rcz09diRjN1k 2VpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=gMtbi1YlmG7TeeMSvQDC1HT4x/YMqKbJWvOlr3IvkwQ=; b=GgFUgBY0SlcvTxzKCJtB/IaHA1kGEltDUU79HHPJeziFt9KMXW+Om/Pw3VwvzgT84/ KVOWk65g8mzwNOSAAdirkOe/cVPR42pN3sT0WPk6boA+76khKPsaM8iguIEGAV0xWpb9 eZBbxAlqR54tTo2iHxJYBSxLEecpVBSgBrhrp3TJ1rYxQMY58ToCrtvXbvCgeqoT7jot xj//zphdXCXUR2MNj+MzIX4uYaoCqAAr3MNgnEl/NAivlqoL7ow3Gru1iT8X70yS1tsg fpQmVEkpqG9ADh01//6lt/t8jSF4MsW1sx/zEnld3kKkA6Pk0IX6T19Fk7phq5eP9Vjj nSag== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WI97c4vs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r187-v6si34901956ywh.460.2018.11.23.06.52.26 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 06:52:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WI97c4vs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52785 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCoj-0006E0-SE for patch@linaro.org; Fri, 23 Nov 2018 09:52:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCif-0007yT-Qu for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCid-00038B-MO for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:09 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:50875) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCic-00036n-KQ for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:07 -0500 Received: by mail-wm1-x342.google.com with SMTP id 125so12199204wmh.0 for ; Fri, 23 Nov 2018 06:46:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gMtbi1YlmG7TeeMSvQDC1HT4x/YMqKbJWvOlr3IvkwQ=; b=WI97c4vsLQIhI8ZI+ykjd9EbCJUVakHqvRhgolNwE7j6N2/h18B4bktAfpRUgZvfUN rlVLW6I4UDmp7W0ESy/+KvZ3E2OCfDQM/a6gg1spCN9GSzOWpoG2CnYFaXC2046hCsHq s7Pr+uucuMItAX9ILPCFgScPwVOnMv/cy4pLc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gMtbi1YlmG7TeeMSvQDC1HT4x/YMqKbJWvOlr3IvkwQ=; b=gKKid48oo9b45qMAsXqt1060OqGrrlf1siacWrENHKvmYSrihPmQ7sMOTgVtmlVbvo eKdGsbWRhquy06Fy43+znuLlndya9UThAStWaKH2tJ6PxgLRixEbFDY0WUzE23G1nEgE HXH7ZcgonLAz3aMkSGa5XuisGH07OcGvR5Yc+QnCVv7KJFjwX7jVbbJGG3CyskTaF1Qu +ndDIN8+KiGrRy1DceB4gx78x9HRx90tCaqgpl+RRYSWbgRxo3LBqt+CR2jEFiM9Ns1O i1QNFqp82p0Zn5JcNMYvaZulc6M0JiZOv44VC4CvAlz7j5H/lkBDv/Fp5OkWhySapAqR n4mQ== X-Gm-Message-State: AA+aEWYLhSkxo+Li7qXD9BLMbXsZBJ3VB0aFpTlI3CcE//PciWOmcSq8 NdNV8F/mHyWVaz6qxgVgiUCXFwZOyl3b9Q== X-Received: by 2002:a1c:aecb:: with SMTP id x194mr13020337wme.96.1542984364704; Fri, 23 Nov 2018 06:46:04 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:25 +0100 Message-Id: <20181123144558.5048-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 v2 04/37] tcg: Add TCG_TARGET_NEED_LDST_OOL_LABELS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This variant of tcg-ldst.inc.c allows the entire thunk to be moved out-of-line, with caching across TBs within a region. Signed-off-by: Richard Henderson --- tcg/tcg.h | 5 +++ accel/tcg/translate-all.c | 15 +++++-- tcg/tcg-ldst-ool.inc.c | 95 +++++++++++++++++++++++++++++++++++++++ tcg/tcg.c | 28 ++++++++++++ 4 files changed, 140 insertions(+), 3 deletions(-) create mode 100644 tcg/tcg-ldst-ool.inc.c -- 2.17.2 diff --git a/tcg/tcg.h b/tcg/tcg.h index f4efbaa680..73737dc671 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -706,6 +706,11 @@ struct TCGContext { #ifdef TCG_TARGET_NEED_LDST_LABELS QSIMPLEQ_HEAD(ldst_labels, TCGLabelQemuLdst) ldst_labels; #endif +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + QSIMPLEQ_HEAD(ldst_labels, TCGLabelQemuLdstOol) ldst_ool_labels; + GHashTable *ldst_ool_thunks; + size_t ldst_ool_generation; +#endif #ifdef TCG_TARGET_NEED_POOL_LABELS struct TCGLabelPoolData *pool_labels; #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 639f0b2728..dd9332b24c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1678,6 +1678,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong virt_page2; tcg_insn_unit *gen_code_buf; int gen_code_size, search_size; +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + size_t ldst_ool_generation = tcg_ctx->ldst_ool_generation; +#endif #ifdef CONFIG_PROFILER TCGProfile *prof = &tcg_ctx->prof; int64_t ti; @@ -1831,10 +1834,16 @@ TranslationBlock *tb_gen_code(CPUState *cpu, existing_tb = tb_link_page(tb, phys_pc, phys_page2); /* if the TB already exists, discard what we just translated */ if (unlikely(existing_tb != tb)) { - uintptr_t orig_aligned = (uintptr_t)gen_code_buf; + bool discard = true; - orig_aligned -= ROUND_UP(sizeof(*tb), qemu_icache_linesize); - atomic_set(&tcg_ctx->code_gen_ptr, (void *)orig_aligned); +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + discard = ldst_ool_generation == tcg_ctx->ldst_ool_generation; +#endif + if (discard) { + uintptr_t orig_aligned = (uintptr_t)gen_code_buf; + orig_aligned -= ROUND_UP(sizeof(*tb), qemu_icache_linesize); + atomic_set(&tcg_ctx->code_gen_ptr, (void *)orig_aligned); + } return existing_tb; } tcg_tb_insert(tb); diff --git a/tcg/tcg-ldst-ool.inc.c b/tcg/tcg-ldst-ool.inc.c new file mode 100644 index 0000000000..70b8789797 --- /dev/null +++ b/tcg/tcg-ldst-ool.inc.c @@ -0,0 +1,95 @@ +/* + * TCG Backend Data: load-store optimization only. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +typedef struct TCGLabelQemuLdstOol { + QSIMPLEQ_ENTRY(TCGLabelQemuLdstOol) next; + tcg_insn_unit *label; /* label pointer to be updated */ + int reloc; /* relocation type from label_ptr */ + intptr_t addend; /* relocation addend from label_ptr */ + uint32_t key; /* oi : is_64 : is_ld */ +} TCGLabelQemuLdstOol; + + +/* + * Generate TB finalization at the end of block + */ + +static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, + bool is64, TCGMemOpIdx oi); + +static bool tcg_out_ldst_ool_finalize(TCGContext *s) +{ + TCGLabelQemuLdstOol *lb; + + /* qemu_ld/st slow paths */ + QSIMPLEQ_FOREACH(lb, &s->ldst_ool_labels, next) { + gpointer dest, key = (gpointer)(uintptr_t)lb->key; + TCGMemOpIdx oi; + bool is_ld, is_64, ok; + + /* If we have generated the thunk, and it's still in range, all ok. */ + dest = g_hash_table_lookup(s->ldst_ool_thunks, key); + if (dest && + patch_reloc(lb->label, lb->reloc, (intptr_t)dest, lb->addend)) { + continue; + } + + /* Generate a new thunk. */ + is_ld = extract32(lb->key, 0, 1); + is_64 = extract32(lb->key, 1, 1); + oi = extract32(lb->key, 2, 30); + dest = tcg_out_qemu_ldst_ool(s, is_ld, is_64, oi); + + /* Test for (pending) buffer overflow. The assumption is that any + one thunk beginning below the high water mark cannot overrun + the buffer completely. Thus we can test for overflow after + generating code without having to check during generation. */ + if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { + return false; + } + + /* Remember the thunk for next time. */ + g_hash_table_replace(s->ldst_ool_thunks, key, dest); + s->ldst_ool_generation++; + + /* The new thunk must be in range. */ + ok = patch_reloc(lb->label, lb->reloc, (intptr_t)dest, lb->addend); + tcg_debug_assert(ok); + } + return true; +} + +/* + * Allocate a new TCGLabelQemuLdstOol entry. + */ + +static void add_ldst_ool_label(TCGContext *s, bool is_ld, bool is_64, + TCGMemOpIdx oi, int reloc, intptr_t addend) +{ + TCGLabelQemuLdstOol *lb = tcg_malloc(sizeof(*lb)); + + QSIMPLEQ_INSERT_TAIL(&s->ldst_ool_labels, lb, next); + lb->label = s->code_ptr; + lb->reloc = reloc; + lb->addend = addend; + lb->key = is_ld | (is_64 << 1) | (oi << 2); +} diff --git a/tcg/tcg.c b/tcg/tcg.c index 54f1272187..17c193791f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -521,6 +521,13 @@ static void tcg_region_assign(TCGContext *s, size_t curr_region) s->code_gen_ptr = start; s->code_gen_buffer_size = end - start; s->code_gen_highwater = end - TCG_HIGHWATER; + +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + /* No thunks yet generated this region. Even if they were in range, + this is also the most convenient place to clear the table after a + full tb_flush. */ + g_hash_table_remove_all(s->ldst_ool_thunks); +#endif } static bool tcg_region_alloc__locked(TCGContext *s) @@ -756,6 +763,14 @@ void tcg_register_thread(void) err = tcg_region_initial_alloc__locked(tcg_ctx); g_assert(!err); qemu_mutex_unlock(®ion.lock); + +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + /* If n == 0, keep the hash table we allocated in tcg_context_init. */ + if (n) { + /* Both key and value are raw pointers. */ + s->ldst_ool_thunks = g_hash_table_new(NULL, NULL); + } +#endif } #endif /* !CONFIG_USER_ONLY */ @@ -964,6 +979,11 @@ void tcg_context_init(TCGContext *s) tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); cpu_env = temp_tcgv_ptr(ts); + +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + /* Both key and value are raw pointers. */ + s->ldst_ool_thunks = g_hash_table_new(NULL, NULL); +#endif } /* @@ -3540,6 +3560,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifdef TCG_TARGET_NEED_LDST_LABELS QSIMPLEQ_INIT(&s->ldst_labels); #endif +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + QSIMPLEQ_INIT(&s->ldst_ool_labels); +#endif #ifdef TCG_TARGET_NEED_POOL_LABELS s->pool_labels = NULL; #endif @@ -3620,6 +3643,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) return -1; } #endif +#ifdef TCG_TARGET_NEED_LDST_OOL_LABELS + if (!tcg_out_ldst_ool_finalize(s)) { + return -1; + } +#endif #ifdef TCG_TARGET_NEED_POOL_LABELS if (!tcg_out_pool_finalize(s)) { return -1; From patchwork Fri Nov 23 14:45:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151878 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2207756ljp; Fri, 23 Nov 2018 06:46:48 -0800 (PST) X-Google-Smtp-Source: AFSGD/Xf57Fp29bShJP6bUOB7VtETMJgdRgQV8NpIXH1ejFj67Vqzq0q5/s85SUpraGAwCSuzADu X-Received: by 2002:ad4:5307:: with SMTP id y7mr15238573qvr.9.1542984408798; Fri, 23 Nov 2018 06:46:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984408; cv=none; d=google.com; s=arc-20160816; b=e3w2ZnZnFobZ/QLr4qDx6Yn2MOBlmBt1BaVRoYGhOdjWW7WJM0wCnZNq8V5WnUDPwz 4f2sKEDVKD5t+l0IWegXnj4/0YHeeBPqtTlPb/8dVXE1XDpgNIK7l9VNDEoigy9l6oRb 1FRasOfW+TYHO9twUskLhkGKywxhquxpmBW+B2l7KEU2rtSx0c1qfyvyV390Kp8bEaXm iwVibl2FLVB225FbsI/VbVGRM70nHLL4+/KVFC3ijJoOn6Hpw59+k1tWEbGU2IrxjEoO erNUQ6VIf/3Z7RwoVy/Lceavdd1rG4BfQ2/yuzm5fUjVL3xk6zN2/ZmvJi7BLNsMm1V6 vUPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4t2w9HZ8vg+d4uGvmAWGgfBIIOHnvX6FaBvg4rQXysU=; b=K+7xH7HkdJIOD9vgTmtjg7UEWZlGVPOQEX4e64+T47Rso3GBerenDRrR2KneYOP1Xm sWTKmrXSRoIu/I3zlzKcoh+yf/84T937wuIIntZdACufTIyGGwgMjM+rx4F1DVWvAZLQ DpOR+NPuTr3+8U91wa7S6MZvAn7UB64WxU4/rp75nf8sAOBBW4mx91XMI7tiokds8tto Hj5iMDmpIv8YcqOHemWSU165fE7flIQGjCtXCBAlTZMx7a+HlQ8jGyxaX2wve+Z639Wi VYD+Y03Pu5g0XxVBUPaSVYIrxgK1tELlBfzUiDh/pNimafkYvFEDCfPmpOUmRUFZlFX6 DSNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CUa3zrQx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 v2 05/37] tcg/i386: Add constraints for r8 and r9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are function call arguments for x86_64 we will need soon. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.2 Reviewed-by: Alex Bennée diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 4f66a0c5ae..8aef66e430 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -233,6 +233,14 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); break; + case 'E': /* "Eight", r8 */ + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_R8); + break; + case 'N': /* "Nine", r9 */ + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_R9); + break; case 'q': /* A register that can be used as a byte operand. */ ct->ct |= TCG_CT_REG; From patchwork Fri Nov 23 14:45:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151887 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2217016ljp; Fri, 23 Nov 2018 06:55:21 -0800 (PST) X-Google-Smtp-Source: AJdET5dzSccd79i0+mSuSbTUSy2U6w+ZQFV9We6oI27zNgqDkpnW7q9jhsbHrdqGkd+1jn2EZCEk X-Received: by 2002:a81:3906:: with SMTP id g6-v6mr17111974ywa.123.1542984921777; Fri, 23 Nov 2018 06:55:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984921; cv=none; d=google.com; s=arc-20160816; b=z1k3N7vyfVm26hzoNy/JVnZk9YAsYpL+SQZmPhVMDqVErByGfErP6kYgRel5vWgQfK MrhioBUSSVeJwMqGMHdUdkTgSXZl5K276wkh5sewchgHcXbL0sIcJsJ7tpsADdBHXu6J 5/ryUXYboYAMotqrE4/seYVuqjhd5Domw6OJztzySMWWd+j4QMBWcU6A3zW9ukdfKVuO bApRuhS8ldJW0wfFN+9JaTXTbVwrSLMEqpOVVoIfV1T2Wh4ylBE84y2xegr3xlvwmZO6 iCyNUu9niiTH82rNJdsI2ewzH7ie7Ux7mz0YXUSpsL4TBHvx8J3ykoZKGAMf+fJxG65G lK/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=81OeRW7ulziampPD+KOnmfbUyMMOUlVeu4i4kj52zbk=; b=FYDwVDyoJQW4kZ6feFgtRgiY/RlkrYu/RmWGhTP7zDFFZZzaulJEaixvf5HQIDHUUO SZSJZzh+kvY6bKsatByzS83yQk9U9iA7NM8MNbdnmWEl9BM13b29j55W9zsGeZNdVbGa cx3Avf67+oYj0LlbKr6clBKGefOiYiWf0iOVfHMhUd/o1wPFWs5NE+qOWM1UnJ79y/ER PpsUbzcoY7Fj8pT2+IiHhTGCjAfFLesW7PkKciwiK05rQ5loNQxwEalubbKlmi13WLcH EsBNZTwbugW1pUP3MBoWdXLJYa7ByUXjR7NlsQ7qTvpC1jokSc7HJ0aRKATSLMaaiUw1 rZ/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g9xQMxzV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 06/37] tcg/i386: Return a base register from tcg_out_tlb_load X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly be asking the hot path not to assume TCG_REG_L1 for the host base address. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 56 ++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 27 deletions(-) -- 2.17.2 Reviewed-by: Alex Bennée diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 8aef66e430..3234a8d8bf 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1614,9 +1614,9 @@ static void * const qemu_st_helpers[16] = { First argument register is clobbered. */ -static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - int mem_index, TCGMemOp opc, - tcg_insn_unit **label_ptr, int which) +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, + int mem_index, TCGMemOp opc, + tcg_insn_unit **label_ptr, int which) { const TCGReg r0 = TCG_REG_L0; const TCGReg r1 = TCG_REG_L1; @@ -1696,6 +1696,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, /* add addend(r0), r1 */ tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, offsetof(CPUTLBEntry, addend) - which); + + return r1; } /* @@ -2001,10 +2003,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#if defined(CONFIG_SOFTMMU) - int mem_index; - tcg_insn_unit *label_ptr[2]; -#endif datalo = *args++; datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); @@ -2014,17 +2012,21 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - mem_index = get_mmuidx(oi); + { + int mem_index = get_mmuidx(oi); + tcg_insn_unit *label_ptr[2]; + TCGReg base; - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_read)); + base = tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + label_ptr, offsetof(CPUTLBEntry, addr_read)); - /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); + /* TLB Hit. */ + tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, opc); - /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Record the current context of a load into ldst label */ + add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); + } #else { int32_t offset = guest_base; @@ -2141,10 +2143,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#if defined(CONFIG_SOFTMMU) - int mem_index; - tcg_insn_unit *label_ptr[2]; -#endif datalo = *args++; datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); @@ -2154,17 +2152,21 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - mem_index = get_mmuidx(oi); + { + int mem_index = get_mmuidx(oi); + tcg_insn_unit *label_ptr[2]; + TCGReg base; - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_write)); + base = tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + label_ptr, offsetof(CPUTLBEntry, addr_write)); - /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, 0, 0, opc); + /* TLB Hit. */ + tcg_out_qemu_st_direct(s, datalo, datahi, base, 0, 0, opc); - /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Record the current context of a store into ldst label */ + add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); + } #else { int32_t offset = guest_base; From patchwork Fri Nov 23 14:45:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151881 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2211051ljp; Fri, 23 Nov 2018 06:49:52 -0800 (PST) X-Google-Smtp-Source: AJdET5fZKoWKyhHHZCtZVTCtmdejGbeFGAb+pZSzVz0wi45Wa8V0deiduyfavFTEiKIpaJny4abH X-Received: by 2002:a81:3594:: with SMTP id c142mr16955664ywa.234.1542984592399; Fri, 23 Nov 2018 06:49:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984592; cv=none; d=google.com; s=arc-20160816; b=FT3rkhOFwwcS+bFPOUZX8C9RKCRPI5E45XS5uuAC0U+iYSOlbcP5tCdTXkRaYmiLWt NEpE3fe0LCMgQ+UCg3gnqs/pcykXbnMd6e8UYf3S5IlQ9TMOoDHwdRSrLqiolokYWsN4 uA4j5cHzKkR2u3ZecdjyY3TNdHoziYUXiCJQds9GAFROHiKmhuplAPu0FRgQ+AMtlgFJ RhAAienD5REQt7uX1NhQNI8meWOpBYK/Ex0oX44mqAGZXKpBHvJzUCTSPNtZsSYqLh6I TL8pVf1YF16I+cnoQZ5TBC4W07Mr2hrSkbUO3uqSno1HXSmN691Obe9sG3vMEzS1BjSj 8GcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=LVTH7A9iopjvf2drxrX25J5edqtzezG4K/9PFSj6hBg=; b=MBB4MLbopKC+F5V4U41JpuIXO5D7SrpJQ2opVbbz3XCcaMsqbxA3V+9lSIoCpkZmjP UWW4maZUT6GB/H3tr6qgODl5DWeCW56w+myoJ+UjxX0v0tbniYZ8J3wNXfBBXs6JJXTq JTatzmI5US+81jjIwCGcARCblBiup6Guz7Ll6XeJlszabgqYboLObNYVeS8XdLKDwPnT BcVuNGLTvZTyAPdQj1GWJAC1keRACOEazd5/QIZ1TqRHG4VmWZ7nvbP2T4Dwv7cWpWP7 TXle+hx3dMEuVODffoS2kRNRsdu0J12OqCapI2Sgyq0jFyxXN7A60VsPTfy5+sgcZ2XH WeLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GXAQFiFf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 07/37] tcg/i386: Change TCG_REG_L[01] to not overlap function arguments X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly be forcing qemu_ld/st arguments into registers that match the function call abi of the host, which means that the temps must be elsewhere. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) -- 2.17.2 Reviewed-by: Alex Bennée diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 3234a8d8bf..07df4b2b12 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -121,12 +121,16 @@ static const int tcg_target_call_oarg_regs[] = { #define TCG_CT_CONST_I32 0x400 #define TCG_CT_CONST_WSZ 0x800 -/* Registers used with L constraint, which are the first argument - registers on x86_64, and two random call clobbered registers on - i386. */ +/* Registers used with L constraint, which are two random + * call clobbered registers. These should be free. + */ #if TCG_TARGET_REG_BITS == 64 -# define TCG_REG_L0 tcg_target_call_iarg_regs[0] -# define TCG_REG_L1 tcg_target_call_iarg_regs[1] +# define TCG_REG_L0 TCG_REG_RAX +# ifdef _WIN64 +# define TCG_REG_L1 TCG_REG_R10 +# else +# define TCG_REG_L1 TCG_REG_RDI +# endif #else # define TCG_REG_L0 TCG_REG_EAX # define TCG_REG_L1 TCG_REG_EDX @@ -1628,6 +1632,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, unsigned a_mask = (1 << a_bits) - 1; unsigned s_mask = (1 << s_bits) - 1; target_ulong tlb_mask; + TCGReg base; if (TCG_TARGET_REG_BITS == 64) { if (TARGET_LONG_BITS == 64) { @@ -1674,7 +1679,12 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, before the fastpath ADDQ below. For 64-bit guest and x32 host, MOVQ copies the entire guest address for the slow path, while truncation for the 32-bit host happens with the fastpath ADDL below. */ - tcg_out_mov(s, ttype, r1, addrlo); + if (TCG_TARGET_REG_BITS == 64) { + base = tcg_target_call_iarg_regs[1]; + } else { + base = r1; + } + tcg_out_mov(s, ttype, base, addrlo); /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -1693,11 +1703,11 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, /* TLB Hit. */ - /* add addend(r0), r1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, + /* add addend(r0), base */ + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, base, r0, offsetof(CPUTLBEntry, addend) - which); - return r1; + return base; } /* From patchwork Fri Nov 23 14:45:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151896 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2224258ljp; Fri, 23 Nov 2018 07:01:25 -0800 (PST) X-Google-Smtp-Source: AFSGD/WcVwHBRbAOVUX8H2M4q/2qog7NHNMDi/ziaSEsF8RKSwYBnpl2gT/E3s4vDr02kBC+l2hK X-Received: by 2002:a25:1409:: with SMTP id 9-v6mr15755069ybu.220.1542985285196; Fri, 23 Nov 2018 07:01:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985285; cv=none; d=google.com; s=arc-20160816; b=bSulotl62J1ZDe3TLwKBhmH8JVMkGwgtUrsJcp9dK46hD1KVPxP0tlMBfBjfsK9bmA 5I+K9JlQr0wFxdT+rE9A1gy5lI+n2aQfcXSE+aaBS5N3YcTcJAxNoQfBzNrPjwnZgK/x k0oV5RCtRet3QcTE+BjcEKJxrEMMg9OEd3lGiHk+MyJ5Et0mHtByESM5VSk2QsAIOUOB CJCLrASjOIH2DHGP0fK45OBqilsdRQ+/RfN/D028fLiSwaNB63VM9HN/S6W1IW/rdIUO 9ET6u0WEfNBP1RkvUmjqSSFFc9suCt81uf8k/cg6V+TP29svKOamilT72NvHPTj7kGwh f4VA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=V5pHnTSnR5PCVaavqferbtjCEb5UujC1bIeJMyb+BuI=; b=t1wvHEb3ROORqeVM+4SdQnVs75NNiUJnfWH3koFca1kPCLOH2DqjoqJTyntanGJ9P7 mc3GPsHsDWSqKeIXfpnkr36j0F2b+2Vx5wWYS8xTW3qHxFjvkhzY719ua7BPYfbxu65z 4I5FgxBjrp1IODcD6WUXDJ5NAh4a4I4H14O2YkjwCfFVbxgOHAQclfd0IOZ4IBKaPEUN U5WM5Z9E16JbB34x2bF/IrmTA8NIRu/5hMGOGsYnERbg4XVFOmr9dlPH6csLFSXE5wzL ZOiVyFdv6iSqXwgCQV5JRKk2eEQj2hX++TePNbPeHQMdj++RukdVRYyKaCBsH550YdTB 8hZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TTqJjopl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 08/37] tcg/i386: Force qemu_ld/st arguments into fixed registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is an incremental step toward moving the qemu_ld/st code sequence out of line. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 203 +++++++++++++++++++++++++++++++------- 1 file changed, 169 insertions(+), 34 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 07df4b2b12..50e5dc31b3 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -171,6 +171,80 @@ static bool have_lzcnt; static tcg_insn_unit *tb_ret_addr; +typedef enum { + ARG_ADDR, + ARG_STVAL, + ARG_LDVAL, +} QemuMemArgType; + +#ifdef CONFIG_SOFTMMU +/* + * Constraint to choose a particular register. This is used for softmmu + * loads and stores. Registers with no assignment get an empty string. + */ +static const char * const one_reg_constraint[TCG_TARGET_NB_REGS] = { + [TCG_REG_EAX] = "a", + [TCG_REG_EBX] = "b", + [TCG_REG_ECX] = "c", + [TCG_REG_EDX] = "d", + [TCG_REG_ESI] = "S", + [TCG_REG_EDI] = "D", +#if TCG_TARGET_REG_BITS == 64 + [TCG_REG_R8] = "E", + [TCG_REG_R9] = "N", +#endif +}; + +/* + * Calling convention for the softmmu load and store thunks. + * + * For 64-bit, we mostly use the host calling convention, therefore the + * real first argument is reserved for the ENV parameter that is passed + * on to the slow path helpers. + * + * For 32-bit, the host calling convention is stack based; we invent a + * private convention that uses 4 of the 6 available host registers. + * We reserve EAX and EDX as temporaries for use by the thunk, we require + * INDEX_op_qemu_st_i32 to have a 'q' register from which to store, and + * further complicate this last by wanting a call-clobbered for that store. + * The 'q' requirement allows MO_8 stores at all; the call-clobbered part + * allows bswap to operate in-place, clobbering the input. + */ +static TCGReg softmmu_arg(QemuMemArgType type, bool is_64, int hi) +{ + switch (type) { + case ARG_ADDR: + tcg_debug_assert(!hi || TARGET_LONG_BITS > TCG_TARGET_REG_BITS); + if (TCG_TARGET_REG_BITS == 64) { + return tcg_target_call_iarg_regs[1]; + } else { + return hi ? TCG_REG_EDI : TCG_REG_ESI; + } + case ARG_STVAL: + tcg_debug_assert(!hi || (TCG_TARGET_REG_BITS == 32 && is_64)); + if (TCG_TARGET_REG_BITS == 64) { + return tcg_target_call_iarg_regs[2]; + } else { + return hi ? TCG_REG_EBX : TCG_REG_ECX; + } + case ARG_LDVAL: + tcg_debug_assert(!hi || (TCG_TARGET_REG_BITS == 32 && is_64)); + return tcg_target_call_oarg_regs[hi]; + } + g_assert_not_reached(); +} + +static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, int hi) +{ + return one_reg_constraint[softmmu_arg(type, is_64, hi)]; +} +#else +static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, int hi) +{ + return "L"; +} +#endif /* CONFIG_SOFTMMU */ + static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { @@ -1680,11 +1754,15 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, copies the entire guest address for the slow path, while truncation for the 32-bit host happens with the fastpath ADDL below. */ if (TCG_TARGET_REG_BITS == 64) { - base = tcg_target_call_iarg_regs[1]; + tcg_debug_assert(addrlo == tcg_target_call_iarg_regs[1]); + if (TARGET_LONG_BITS == 32) { + tcg_out_ext32u(s, addrlo, addrlo); + } + base = addrlo; } else { base = r1; + tcg_out_mov(s, ttype, base, addrlo); } - tcg_out_mov(s, ttype, base, addrlo); /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -2009,16 +2087,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, common. */ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); + TCGReg datalo, addrlo; + TCGReg datahi __attribute__((unused)) = -1; + TCGReg addrhi __attribute__((unused)) = -1; TCGMemOpIdx oi; TCGMemOp opc; + int i = -1; - datalo = *args++; - datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); - addrlo = *args++; - addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi = *args++; + datalo = args[++i]; + if (TCG_TARGET_REG_BITS == 32 && is64) { + datahi = args[++i]; + } + addrlo = args[++i]; + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + addrhi = args[++i]; + } + oi = args[++i]; opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) @@ -2027,6 +2111,15 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) tcg_insn_unit *label_ptr[2]; TCGReg base; + tcg_debug_assert(datalo == softmmu_arg(ARG_LDVAL, is64, 0)); + if (TCG_TARGET_REG_BITS == 32 && is64) { + tcg_debug_assert(datahi == softmmu_arg(ARG_LDVAL, is64, 1)); + } + tcg_debug_assert(addrlo == softmmu_arg(ARG_ADDR, 0, 0)); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_debug_assert(addrhi == softmmu_arg(ARG_ADDR, 0, 1)); + } + base = tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, label_ptr, offsetof(CPUTLBEntry, addr_read)); @@ -2149,16 +2242,22 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); + TCGReg datalo, addrlo; + TCGReg datahi __attribute__((unused)) = -1; + TCGReg addrhi __attribute__((unused)) = -1; TCGMemOpIdx oi; TCGMemOp opc; + int i = -1; - datalo = *args++; - datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); - addrlo = *args++; - addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi = *args++; + datalo = args[++i]; + if (TCG_TARGET_REG_BITS == 32 && is64) { + datahi = args[++i]; + } + addrlo = args[++i]; + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + addrhi = args[++i]; + } + oi = args[++i]; opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) @@ -2167,6 +2266,15 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) tcg_insn_unit *label_ptr[2]; TCGReg base; + tcg_debug_assert(datalo == softmmu_arg(ARG_STVAL, is64, 0)); + if (TCG_TARGET_REG_BITS == 32 && is64) { + tcg_debug_assert(datahi == softmmu_arg(ARG_STVAL, is64, 1)); + } + tcg_debug_assert(addrlo == softmmu_arg(ARG_ADDR, 0, 0)); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_debug_assert(addrhi == softmmu_arg(ARG_ADDR, 0, 1)); + } + base = tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, label_ptr, offsetof(CPUTLBEntry, addr_write)); @@ -2836,15 +2944,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } }; static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } }; static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L_L - = { .args_ct_str = { "L", "L", "L", "L" } }; static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } }; static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } }; static const TCGTargetOpDef x_x_x_x @@ -3026,17 +3125,53 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) } case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; - case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L; + { + static TCGTargetOpDef ld32; + int i; + + ld32.args_ct_str[0] = constrain_memop_arg(ARG_LDVAL, 0, 0); + for (i = 0; i * TCG_TARGET_REG_BITS < TARGET_LONG_BITS; ++i) { + ld32.args_ct_str[i + 1] = constrain_memop_arg(ARG_ADDR, 0, i); + } + return &ld32; + } case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L); + { + static TCGTargetOpDef ld64; + int i, j = 0; + + for (i = 0; i * TCG_TARGET_REG_BITS < 64; ++i) { + ld64.args_ct_str[j++] = constrain_memop_arg(ARG_LDVAL, 1, i); + } + for (i = 0; i * TCG_TARGET_REG_BITS < TARGET_LONG_BITS; ++i) { + ld64.args_ct_str[j++] = constrain_memop_arg(ARG_ADDR, 0, i); + } + return &ld64; + } + case INDEX_op_qemu_st_i32: + { + static TCGTargetOpDef st32; + int i; + + st32.args_ct_str[0] = constrain_memop_arg(ARG_STVAL, 0, 0); + for (i = 0; i * TCG_TARGET_REG_BITS < TARGET_LONG_BITS; ++i) { + st32.args_ct_str[i + 1] = constrain_memop_arg(ARG_ADDR, 0, i); + } + return &st32; + } case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &L_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L - : &L_L_L_L); + { + static TCGTargetOpDef st64; + int i, j = 0; + + for (i = 0; i * TCG_TARGET_REG_BITS < 64; ++i) { + st64.args_ct_str[j++] = constrain_memop_arg(ARG_STVAL, 1, i); + } + for (i = 0; i * TCG_TARGET_REG_BITS < TARGET_LONG_BITS; ++i) { + st64.args_ct_str[j++] = constrain_memop_arg(ARG_ADDR, 0, i); + } + return &st64; + } case INDEX_op_brcond2_i32: { From patchwork Fri Nov 23 14:45:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151895 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2223931ljp; Fri, 23 Nov 2018 07:01:13 -0800 (PST) X-Google-Smtp-Source: AJdET5e8qhOLRYddkjZcdEc1VcaZeEcFN7BDo2+L+QYtAxM4P8twgJAwizzFi3+XGrQcHsYBwizc X-Received: by 2002:a81:7051:: with SMTP id l78mr16360526ywc.146.1542985273093; Fri, 23 Nov 2018 07:01:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985273; cv=none; d=google.com; s=arc-20160816; b=y85SMSVVv6Adaq8Mo/28nTprGCDdy/EIehmTWRVOJryr8q77sP6V10y6jOHaQoPEt6 Ja36bJZiHohHhR5liuVNmTEFd5gWAgBZGYgXHXPKVjU06DDJdfukiUmd2Q9K+lvSF05R kZDH64LgCgP7cc/+gpre0DsZoDZ/VddWnjB1xPDuevY6uXYkvr1bb4hBKwC5xTl93p4a w9HdP6OZQtLhXloaploZIW63N0EAsMi7vwNEowMW4gm04WdAGcEV8YKcl4ywcvQrY69I 7cidhdi5LJWLXY+GCsEGyJgRIMolEATd1gzK/o0zX4tMZchJYve4Rb+jr44HzzqOdrMZ OGqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=EcT4jjYW2sEeAnKGx9+I7bAH1gthrHWnSv8affH5DRQ=; b=u5XXimwJFaAEVI85a3PtsaZ5y+DTFtD/Sj3B/xZ9ilETWFbHxdAxFgqqgDNQSd2x5q WJFknNlUgtuc+pbL9G++F8yeM7b+318qTF1GMoHy+zj17K2KrOwMRAxcxrp/WhajugT3 qrGsUvZ35H2W1/GSUt3KlJbJ/xLctxxMHfSeAVXBg6erlhjBjpgTk8kb+U1uhn7HHGtc +0U2ZZLUwgRVZtt1TaFUoEFml9X55vB1nqUvW76TxASuG0V3JgjiyFEym4Ax5s86Wr7W XAjdAGzpN09+ae1eNiJvIZ54LNldTf73SRktJMu8EuIIZxR1M3gZlija8VMN5YwbCuQZ Ajvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IxZTQKmV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 v2 09/37] tcg/i386: Use TCG_TARGET_NEED_LDST_OOL_LABELS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the entire memory operation out of line. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 391 ++++++++++++++++---------------------- 2 files changed, 162 insertions(+), 231 deletions(-) -- 2.17.2 Reviewed-by: Alex Bennée diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2441658865..1b2d4e1b0d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -220,7 +220,7 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) #ifdef CONFIG_SOFTMMU -#define TCG_TARGET_NEED_LDST_LABELS +#define TCG_TARGET_NEED_LDST_OOL_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 50e5dc31b3..5c68cbd43d 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1643,7 +1643,7 @@ static void tcg_out_nopn(TCGContext *s, int n) } #if defined(CONFIG_SOFTMMU) -#include "tcg-ldst.inc.c" +#include "tcg-ldst-ool.inc.c" /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1656,6 +1656,14 @@ static void * const qemu_ld_helpers[16] = { [MO_BEUW] = helper_be_lduw_mmu, [MO_BEUL] = helper_be_ldul_mmu, [MO_BEQ] = helper_be_ldq_mmu, + + [MO_SB] = helper_ret_ldsb_mmu, + [MO_LESW] = helper_le_ldsw_mmu, + [MO_BESW] = helper_be_ldsw_mmu, +#if TCG_TARGET_REG_BITS == 64 + [MO_LESL] = helper_le_ldsl_mmu, + [MO_BESL] = helper_be_ldsl_mmu, +#endif }; /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, @@ -1765,18 +1773,18 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, } /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + tcg_out_opc(s, OPC_JCC_short + JCC_JNE, 0, 0, 0); label_ptr[0] = s->code_ptr; - s->code_ptr += 4; + s->code_ptr += 1; if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { /* cmp 4(r0), addrhi */ tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, 4); /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + tcg_out_opc(s, OPC_JCC_short + JCC_JNE, 0, 0, 0); label_ptr[1] = s->code_ptr; - s->code_ptr += 4; + s->code_ptr += 1; } /* TLB Hit. */ @@ -1788,181 +1796,6 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, return base; } -/* - * Record the context of a call to the out of line helper code for the slow path - * for a load or store, so that we can later generate the correct helper code - */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, - tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->datalo_reg = datalo; - label->datahi_reg = datahi; - label->addrlo_reg = addrlo; - label->addrhi_reg = addrhi; - label->raddr = raddr; - label->label_ptr[0] = label_ptr[0]; - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - label->label_ptr[1] = label_ptr[1]; - } -} - -/* - * Generate code for the slow path for a load at the end of block - */ -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - TCGMemOpIdx oi = l->oi; - TCGMemOp opc = get_memop(oi); - TCGReg data_reg; - tcg_insn_unit **label_ptr = &l->label_ptr[0]; - - /* resolve label address */ - tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); - } - - if (TCG_TARGET_REG_BITS == 32) { - int ofs = 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs += 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs += 4; - - if (TARGET_LONG_BITS == 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs += 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs += 4; - - tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); - /* The second argument is already loaded with addrlo. */ - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); - tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], - (uintptr_t)l->raddr); - } - - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - data_reg = l->datalo_reg; - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_out_ext8s(s, data_reg, TCG_REG_EAX, P_REXW); - break; - case MO_SW: - tcg_out_ext16s(s, data_reg, TCG_REG_EAX, P_REXW); - break; -#if TCG_TARGET_REG_BITS == 64 - case MO_SL: - tcg_out_ext32s(s, data_reg, TCG_REG_EAX); - break; -#endif - case MO_UB: - case MO_UW: - /* Note that the helpers have zero-extended to tcg_target_long. */ - case MO_UL: - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - break; - case MO_Q: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); - } else if (data_reg == TCG_REG_EDX) { - /* xchg %edx, %eax */ - tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX); - } else { - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX); - } - break; - default: - tcg_abort(); - } - - /* Jump to the code corresponding to next IR of qemu_st */ - tcg_out_jmp(s, l->raddr); -} - -/* - * Generate code for the slow path for a store at the end of block - */ -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - TCGMemOpIdx oi = l->oi; - TCGMemOp opc = get_memop(oi); - TCGMemOp s_bits = opc & MO_SIZE; - tcg_insn_unit **label_ptr = &l->label_ptr[0]; - TCGReg retaddr; - - /* resolve label address */ - tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); - } - - if (TCG_TARGET_REG_BITS == 32) { - int ofs = 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs += 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs += 4; - - if (TARGET_LONG_BITS == 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs += 4; - } - - tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs); - ofs += 4; - - if (s_bits == MO_64) { - tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs); - ofs += 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs += 4; - - retaddr = TCG_REG_EAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); - /* The second argument is already loaded with addrlo. */ - tcg_out_mov(s, (s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - tcg_target_call_iarg_regs[2], l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); - - if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) { - retaddr = tcg_target_call_iarg_regs[4]; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - } else { - retaddr = TCG_REG_RAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, - TCG_TARGET_CALL_STACK_OFFSET); - } - } - - /* "Tail call" to the helper, with the return address back inline. */ - tcg_out_push(s, retaddr); - tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); -} #elif defined(__x86_64__) && defined(__linux__) # include # include @@ -2091,7 +1924,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) TCGReg datahi __attribute__((unused)) = -1; TCGReg addrhi __attribute__((unused)) = -1; TCGMemOpIdx oi; - TCGMemOp opc; int i = -1; datalo = args[++i]; @@ -2103,35 +1935,25 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) addrhi = args[++i]; } oi = args[++i]; - opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - { - int mem_index = get_mmuidx(oi); - tcg_insn_unit *label_ptr[2]; - TCGReg base; - - tcg_debug_assert(datalo == softmmu_arg(ARG_LDVAL, is64, 0)); - if (TCG_TARGET_REG_BITS == 32 && is64) { - tcg_debug_assert(datahi == softmmu_arg(ARG_LDVAL, is64, 1)); - } - tcg_debug_assert(addrlo == softmmu_arg(ARG_ADDR, 0, 0)); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_debug_assert(addrhi == softmmu_arg(ARG_ADDR, 0, 1)); - } - - base = tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_read)); - - /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, opc); - - /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Assert that we've set up the constraints properly. */ + tcg_debug_assert(datalo == softmmu_arg(ARG_LDVAL, is64, 0)); + if (TCG_TARGET_REG_BITS == 32 && is64) { + tcg_debug_assert(datahi == softmmu_arg(ARG_LDVAL, is64, 1)); } + tcg_debug_assert(addrlo == softmmu_arg(ARG_ADDR, 0, 0)); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_debug_assert(addrhi == softmmu_arg(ARG_ADDR, 0, 1)); + } + + /* Call to thunk. */ + tcg_out8(s, OPC_CALL_Jz); + add_ldst_ool_label(s, true, is64, oi, R_386_PC32, -4); + s->code_ptr += 4; #else { + TCGMemOp opc = get_memop(oi); int32_t offset = guest_base; TCGReg base = addrlo; int index = -1; @@ -2246,7 +2068,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) TCGReg datahi __attribute__((unused)) = -1; TCGReg addrhi __attribute__((unused)) = -1; TCGMemOpIdx oi; - TCGMemOp opc; int i = -1; datalo = args[++i]; @@ -2258,35 +2079,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) addrhi = args[++i]; } oi = args[++i]; - opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - { - int mem_index = get_mmuidx(oi); - tcg_insn_unit *label_ptr[2]; - TCGReg base; - - tcg_debug_assert(datalo == softmmu_arg(ARG_STVAL, is64, 0)); - if (TCG_TARGET_REG_BITS == 32 && is64) { - tcg_debug_assert(datahi == softmmu_arg(ARG_STVAL, is64, 1)); - } - tcg_debug_assert(addrlo == softmmu_arg(ARG_ADDR, 0, 0)); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_debug_assert(addrhi == softmmu_arg(ARG_ADDR, 0, 1)); - } - - base = tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_write)); - - /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, base, 0, 0, opc); - - /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Assert that we've set up the constraints properly. */ + tcg_debug_assert(datalo == softmmu_arg(ARG_STVAL, is64, 0)); + if (TCG_TARGET_REG_BITS == 32 && is64) { + tcg_debug_assert(datahi == softmmu_arg(ARG_STVAL, is64, 1)); } + tcg_debug_assert(addrlo == softmmu_arg(ARG_ADDR, 0, 0)); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_debug_assert(addrhi == softmmu_arg(ARG_ADDR, 0, 1)); + } + + /* Call to thunk. */ + tcg_out8(s, OPC_CALL_Jz); + add_ldst_ool_label(s, false, is64, oi, R_386_PC32, -4); + s->code_ptr += 4; #else { + TCGMemOp opc = get_memop(oi); int32_t offset = guest_base; TCGReg base = addrlo; int seg = 0; @@ -2321,6 +2132,126 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) #endif } +#if defined(CONFIG_SOFTMMU) +/* + * Generate code for an out-of-line thunk performing a load. + */ +static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, + bool is_64, TCGMemOpIdx oi) +{ + TCGMemOp opc = get_memop(oi); + int mem_index = get_mmuidx(oi); + tcg_insn_unit *label_ptr[2], *thunk; + TCGReg datalo, addrlo, base; + TCGReg datahi __attribute__((unused)) = -1; + TCGReg addrhi __attribute__((unused)) = -1; + int i; + + /* Since we're amortizing the cost, align the thunk. */ + thunk = QEMU_ALIGN_PTR_UP(s->code_ptr, 16); + if (thunk != s->code_ptr) { + memset(s->code_ptr, 0x90, thunk - s->code_ptr); + s->code_ptr = thunk; + } + + /* Discover where the inputs are held. */ + addrlo = softmmu_arg(ARG_ADDR, 0, 0); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + addrhi = softmmu_arg(ARG_ADDR, 0, 1); + } + datalo = softmmu_arg(is_ld ? ARG_LDVAL : ARG_STVAL, is_64, 0); + if (TCG_TARGET_REG_BITS == 32 && is_64) { + datahi = softmmu_arg(is_ld ? ARG_LDVAL : ARG_STVAL, is_64, 1); + } + + base = tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, label_ptr, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + + /* TLB Hit. */ + if (is_ld) { + tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, opc); + } else { + tcg_out_qemu_st_direct(s, datalo, datahi, base, 0, 0, opc); + } + tcg_out_opc(s, OPC_RET, 0, 0, 0); + + /* TLB Miss. */ + + /* resolve label address */ + tcg_patch8(label_ptr[0], s->code_ptr - label_ptr[0] - 1); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_patch8(label_ptr[1], s->code_ptr - label_ptr[1] - 1); + } + + if (TCG_TARGET_REG_BITS == 32) { + /* Copy the return address into a temporary. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_ESP, 0); + i = 4; + + tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, i); + i += 4; + + tcg_out_st(s, TCG_TYPE_I32, addrlo, TCG_REG_ESP, i); + i += 4; + + if (TARGET_LONG_BITS == 64) { + tcg_out_st(s, TCG_TYPE_I32, addrhi, TCG_REG_ESP, i); + i += 4; + } + + if (!is_ld) { + tcg_out_st(s, TCG_TYPE_I32, datalo, TCG_REG_ESP, i); + i += 4; + + if (is_64) { + tcg_out_st(s, TCG_TYPE_I32, datahi, TCG_REG_ESP, i); + i += 4; + } + } + + tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, i); + i += 4; + + tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_ESP, i); + } else { + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + + /* The address and data values have been placed by constraints. */ + tcg_debug_assert(addrlo == tcg_target_call_iarg_regs[1]); + if (is_ld) { + i = 2; + } else { + tcg_debug_assert(datalo == tcg_target_call_iarg_regs[2]); + i = 3; + } + + tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[i++], oi); + + /* Copy the return address from the stack to the rvalue argument. + * WIN64 runs out of argument registers for stores. + */ + if (i < (int)ARRAY_SIZE(tcg_target_call_iarg_regs)) { + tcg_out_ld(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[i], + TCG_REG_ESP, 0); + } else { + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_RAX, TCG_REG_ESP, 0); + tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_RAX, TCG_REG_ESP, + TCG_TARGET_CALL_STACK_OFFSET + 8); + } + } + + /* Tail call to the helper. */ + if (is_ld) { + tcg_out_jmp(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); + } else { + tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + } + + return thunk; +} +#endif + static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { From patchwork Fri Nov 23 14:45:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151885 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2215452ljp; Fri, 23 Nov 2018 06:53:54 -0800 (PST) X-Google-Smtp-Source: AFSGD/XXtvBGnZjxLpNi6/Ww99iI6wtHVdNGLkyDwYt1CXhNjnN7mtu3E5Yvn1VNdF0tqmXkqWYI X-Received: by 2002:a81:de0d:: with SMTP id k13mr5500817ywj.61.1542984834187; Fri, 23 Nov 2018 06:53:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984834; cv=none; d=google.com; s=arc-20160816; b=q3dhd0i7nk3AieYA7RFBw03ZJ9k5wosNaQtvcnZK1k47bb+5fd8i3yirRnGgqqd3fS 9licNXTBx2t+EwfNoMQKgcq4jB91Fy2IJbcXRDFWpD6Pyy2XzwTxjmJ+vsofJAF5ssQk 02bOn2eTJNb7z5UGV6F3tjc2IjozlFcGmP4ZMlSPi/ndHJ3tlGacnmPAnXK6JORmyDmq BFZTwpbiYzQAkqyVgEPqj4JQORZqjVHh+J/aNo85UL3zk0XaUQinfRZ+K2KJi4FmTyzB nzlpzESDLCkNTC7x69seyFNmKGODjrbObDVFPX9O9xmtVhJFHkZgjQMgm/Oxhp6O9gv9 XxSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=dEMW7UG/VwRHHO8qBaUD73G0cEqvXtdIe4LBfAmg/J0=; b=VQVpCzTVrFt5OiFWJOYTiRvH/5TYzanF+xqs/rTyykprwey1f7i2O4RBbfemm9anWD oIX22+TcG+HvP9l7zJViJVAGLRleYTQdlWNl6eXdu232sRo7oTzQhGkbiSHEC9e58D/J SpcD5M70/UZTmP+715QuiZO9Es2rzzPGg1X3RMZ6IJa0Qa4Hot+AVaPlMPNCPetDksry rdKiV267wycD/bGsu0PYe2vlbhESub7g8tDCBxSE1+1F5YOd2HnPUv84LD3G+L24716Q tgZ6AQlndQnzytjxCcNqsXg3N0OoabgII/NUFTSv6agK97tysxv6jAG9YK6BhQoxldJ7 uhLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kMLvLT+r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g64-v6si34577106ywd.44.2018.11.23.06.53.53 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 06:53:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kMLvLT+r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52793 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCq9-0008Hl-Hd for patch@linaro.org; Fri, 23 Nov 2018 09:53:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCij-00080W-RF for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCih-0003Du-Qz for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:13 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:34360) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCih-0003CZ-Iw for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:11 -0500 Received: by mail-wm1-x344.google.com with SMTP id y185so7737542wmd.1 for ; Fri, 23 Nov 2018 06:46:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dEMW7UG/VwRHHO8qBaUD73G0cEqvXtdIe4LBfAmg/J0=; b=kMLvLT+rLD14wrCk4zA0iX1FSJpw7j2sCcO7yspP31Tn6e6yKLV6JmMlleud6kOHuz MhJDp7+1TqM8VTRypp8DS22+TOMp37WjARPd0v3LJoK0kcQ5d9mNQ9E3+A6X5SY/15RE yZ5sdOoS8AcVDhRSDPOHCz8LnkOAqojnV4zoE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dEMW7UG/VwRHHO8qBaUD73G0cEqvXtdIe4LBfAmg/J0=; b=lIEKNUn7Iv2Rb9S378ccqL/55EPuYWWp9J9+J8pQC9gyG06U3LPgGVtWawy7Wp5Wbu L2Q0RPcrFJGlpN54g9R/X0O90jfRu7obhvz4WbSaBJ5qAGYX/9zWFBJGHLOmh4Bt1pC5 v+3P3XaApQ4cm9oW8/8LDmXiSkRUin5n+7Ww0p6zETaw1cZrzOurn5KYorW6YezZYTA6 dSOXLV0VjuVRySt5aFCDeqDk3FE6asVbhbAh0T458QYiNY3ZBe2cVWEWUyHNIObMdDHT BOQUVW42t0/qtWxYQjPd87BDVJ9SZIZr2THVzluE02EKttC1SxWGCpccfoXxB/NrHT+r Lryg== X-Gm-Message-State: AGRZ1gIWLUZTcYjnEO8HUHGvSmXvhLpaM03rND56PGhQKT8xoEB3PYCC l342oBPWlQDycuf+K5SAWz/HAY9VS3LZ7A== X-Received: by 2002:a1c:8314:: with SMTP id f20-v6mr14249722wmd.120.1542984370190; Fri, 23 Nov 2018 06:46:10 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:31 +0100 Message-Id: <20181123144558.5048-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 v2 10/37] tcg/aarch64: Add constraints for x0, x1, x2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are function call arguments that we will need soon. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.17.2 Reviewed-by: Alex Bennée diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 30091f6a69..148de0b7f2 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -125,6 +125,18 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType type) { switch (*ct_str++) { + case 'a': /* x0 */ + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_X0); + break; + case 'b': /* x1 */ + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_X1); + break; + case 'c': /* x2 */ + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_X2); + break; case 'r': /* general registers */ ct->ct |= TCG_CT_REG; ct->u.regs |= 0xffffffffu; From patchwork Fri Nov 23 14:45:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151884 Delivered-To: patch@linaro.org Received: by 2002:a2e:5d95:0:0:0:0:0 with SMTP id v21-v6csp2227439lje; Fri, 23 Nov 2018 06:52:52 -0800 (PST) X-Google-Smtp-Source: AFSGD/X8RUd8z2MzCWoOUN9/X3ULqEU1I6VPh7kxl9Uw9rWuCVJxHDcrnxdhG/JjHjKp2xzHz0T1 X-Received: by 2002:a25:aaa1:: with SMTP id t30-v6mr16965656ybi.175.1542984772568; Fri, 23 Nov 2018 06:52:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984772; cv=none; d=google.com; s=arc-20160816; b=WOturfD9fDh/JL0+IGlCxuyofLxMRL703O6drYWEAP3drB9AXeKvZcSG0G48b+Cv5Q IeJu+Uk4MDWihNO0drlEexBYc1Za/V5CF0MQftCf2eHHHk3mivgic+j1JG1oUqXiqbBP 0hnrSVYMaPaeXj7ReD/UeJuZvtXDNZq93oFyP5hn2+0q83jjEWLmx2fAwkBQnAKLyNJ9 tGmIGpPB4aCDqfvaQNuZWWVyHLtSGoKW0sHFTNQN5oVJCGuP5pBaYMclaLecvRnoJH3g 0J4cHrJ0HyjgLToD7HfeqFP5JOk3UcJFfxp/A8NrQWvUXLfgkfh57nG3paUQ7Lbu4cJt HrLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=2ItTk51JTjzE0w3i+PlYwVgMsWgaDFle4WWcoNcT4uk=; b=LI/xHIuhga+N1MxLAxr4qIoUtmisJsFwD8pBcs0YPwEf1c3tYpd/r0Z9pay64JfKxD uDOwz4vIhufYTA4X6aXt0r3K7q/h6HS/diXTjRlx5iMlCRvc1zYo+IN/WUQnJIWvSe6S uje4QsH0ZDT1rA2dxqr9/IR2GvMOqD3wNQrFdgM3LQO7tkSinUeeO03zQTIs2bBXNsC4 Osj5NAur2AEqZgp/g89gc0/5n9d3By6ipF0z1pyxqSnPoNu1l2alp8P/bap2auS1p9km PfOCMl1Xc8jCNsOu1QJyF7tVjfjGVUN92+fki5tWNjwcX+d95M3q2ZHVd+TCjb6GWDmD IFig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=R9VQioAg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 11/37] tcg/aarch64: Parameterize the temps for tcg_out_tlb_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When moving the qemu_ld/st arguments to the right place for a function call, we'll need to move the temps out of the way. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 74 +++++++++++++++++++----------------- 1 file changed, 40 insertions(+), 34 deletions(-) -- 2.17.2 Reviewed-by: Alex Bennée diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 148de0b7f2..c0ba9a6d50 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1467,13 +1467,15 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->label_ptr[0] = label_ptr; } -/* Load and compare a TLB entry, emitting the conditional jump to the - slow path for the failure case, which will be patched later when finalizing - the slow path. Generated code returns the host addend in X1, - clobbers X0,X2,X3,TMP. */ -static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, - tcg_insn_unit **label_ptr, int mem_index, - bool is_read) +/* + * Load and compare a TLB entry, emitting the conditional jump to the + * slow path on failure. Returns the register for the host addend. + * Clobbers t0, t1, t2, t3. + */ +static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, + tcg_insn_unit **label_ptr, int mem_index, + bool is_read, TCGReg t0, TCGReg t1, + TCGReg t2, TCGReg t3) { int tlb_offset = is_read ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) @@ -1491,55 +1493,56 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, if (a_bits >= s_bits) { x3 = addr_reg; } else { + x3 = t3; tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS == 64, - TCG_REG_X3, addr_reg, s_mask - a_mask); - x3 = TCG_REG_X3; + x3, addr_reg, s_mask - a_mask); } tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask; - /* Extract the TLB index from the address into X0. - X0 = + /* Extract the TLB index from the address into T0. + T0 = addr_reg */ - tcg_out_ubfm(s, TARGET_LONG_BITS == 64, TCG_REG_X0, addr_reg, + tcg_out_ubfm(s, TARGET_LONG_BITS == 64, t0, addr_reg, TARGET_PAGE_BITS, TARGET_PAGE_BITS + CPU_TLB_BITS); - /* Store the page mask part of the address into X3. */ + /* Store the page mask part of the address into T3. */ tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS == 64, - TCG_REG_X3, x3, tlb_mask); + t3, x3, tlb_mask); - /* Add any "high bits" from the tlb offset to the env address into X2, + /* Add any "high bits" from the tlb offset to the env address into T2, to take advantage of the LSL12 form of the ADDI instruction. - X2 = env + (tlb_offset & 0xfff000) */ + T2 = env + (tlb_offset & 0xfff000) */ if (tlb_offset & 0xfff000) { - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_X2, base, + tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, t2, base, tlb_offset & 0xfff000); - base = TCG_REG_X2; + base = t2; } - /* Merge the tlb index contribution into X2. - X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */ - tcg_out_insn(s, 3502S, ADD_LSL, TCG_TYPE_I64, TCG_REG_X2, base, - TCG_REG_X0, CPU_TLB_ENTRY_BITS); + /* Merge the tlb index contribution into T2. + T2 = T2 + (T0 << CPU_TLB_ENTRY_BITS) */ + tcg_out_insn(s, 3502S, ADD_LSL, TCG_TYPE_I64, + t2, base, t0, CPU_TLB_ENTRY_BITS); - /* Merge "low bits" from tlb offset, load the tlb comparator into X0. - X0 = load [X2 + (tlb_offset & 0x000fff)] */ + /* Merge "low bits" from tlb offset, load the tlb comparator into T0. + T0 = load [T2 + (tlb_offset & 0x000fff)] */ tcg_out_ldst(s, TARGET_LONG_BITS == 32 ? I3312_LDRW : I3312_LDRX, - TCG_REG_X0, TCG_REG_X2, tlb_offset & 0xfff, - TARGET_LONG_BITS == 32 ? 2 : 3); + t0, t2, tlb_offset & 0xfff, TARGET_LONG_BITS == 32 ? 2 : 3); /* Load the tlb addend. Do that early to avoid stalling. - X1 = load [X2 + (tlb_offset & 0xfff) + offsetof(addend)] */ - tcg_out_ldst(s, I3312_LDRX, TCG_REG_X1, TCG_REG_X2, + T1 = load [T2 + (tlb_offset & 0xfff) + offsetof(addend)] */ + tcg_out_ldst(s, I3312_LDRX, t1, t2, (tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) - (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)), 3); /* Perform the address comparison. */ - tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0); + tcg_out_cmp(s, (TARGET_LONG_BITS == 64), t0, t3, 0); /* If not equal, we jump to the slow path. */ *label_ptr = s->code_ptr; tcg_out_goto_cond_noaddr(s, TCG_COND_NE); + + return t1; } #endif /* CONFIG_SOFTMMU */ @@ -1644,10 +1647,12 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, #ifdef CONFIG_SOFTMMU unsigned mem_index = get_mmuidx(oi); tcg_insn_unit *label_ptr; + TCGReg base; - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1); + base = tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1, + TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3); tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_X1, otype, addr_reg); + base, otype, addr_reg); add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ @@ -1669,10 +1674,11 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, #ifdef CONFIG_SOFTMMU unsigned mem_index = get_mmuidx(oi); tcg_insn_unit *label_ptr; + TCGReg base; - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0); - tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_X1, otype, addr_reg); + base = tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0, + TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3); + tcg_out_qemu_st_direct(s, memop, data_reg, base, otype, addr_reg); add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ From patchwork Fri Nov 23 14:45:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151898 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2229451ljp; Fri, 23 Nov 2018 07:04:42 -0800 (PST) X-Google-Smtp-Source: AJdET5cQIPEzkZcs6kMjzloH3ujT3XuVZ3+tZPrf735FbMpnOJV65cq1g/JsXpWrUtgLtdzrrrWF X-Received: by 2002:a81:a986:: with SMTP id g128-v6mr16639435ywh.269.1542985482224; Fri, 23 Nov 2018 07:04:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985482; cv=none; d=google.com; s=arc-20160816; b=oAtU2EUOVwxX5qYAk6oNmc+eOrKLYFC0jrfReJsziFDAD1mVeE9DvpZ8Oy5ph8aPu4 8ZgWM98uEmCtU8mXc+vLidhcKxi6XDmbhQFPWxTFpBxUKzS7Z5ifHTRylAOVNvgRCfCX DooNlPmBHcIebo+lwKID8Xt9GbDUWbHuvBHAvdKp1nEvr0m8JLuckxbh3Zdo1B20GDVy 3ak0q4WVzbWNypJu4BRpZ2ZCOQ9CjDYVrybKF5BwpHfecCTGRy9XfhraZbPsI14jNFSE lx+btqiKDuHlNcnGQV3fH7tu36iJH7CO7907QJx2RpwntrwQPRKWkGEKxKgWxIkXhJ+A p29Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=bfXp2m+eG0fPw8rnLzBA4705O4L8LprWDujoyvgpuQg=; b=r9Fm0roIH7mtb1Uv34QF1U8QoA3tTTFG4/bCBtq2mRtoKhJj1i3/ofe2ji9e/R0bYO pkIRt1TfTRwJQpc3XydB9LbNYk2oR/8bqwkJ+fwXp4Hx4b4ICGbFODM39RB2AlMBDlHN TKa670/8ZvicR4Q6f5YwuGW/Z7RuQ9D2s9gknGHzM45oRnPByY3MY+1lcOAiVcV7oEI3 uDCSa+E2Su0y4Psfol6Jvg0l/UQtjmCN8zgs6FsU4F+B232x+Py2Y9keK9oBCczzv5/q XQwtBc5hvqd22oUoScQoNfZA8CYn84c2FYrd/vMTfzvaewUQCiwM/A7cqsb8R+D9UPet zyTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=U7k3uJk6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f18-v6si22478425ybn.255.2018.11.23.07.04.42 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 07:04:42 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=U7k3uJk6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52856 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD0b-0000mt-Iz for patch@linaro.org; Fri, 23 Nov 2018 10:04:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCik-00081X-Vm for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCij-0003Ga-RE for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:14 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:39293) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCij-0003FK-IT for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:13 -0500 Received: by mail-wm1-x343.google.com with SMTP id u13-v6so12248483wmc.4 for ; Fri, 23 Nov 2018 06:46:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bfXp2m+eG0fPw8rnLzBA4705O4L8LprWDujoyvgpuQg=; b=U7k3uJk6yF8aTFNtqpq2sGt1Gfmct4617lnV/6ozerK48fvJPlSoDQ4pc5nnIk7PaW 06lyt6nlYMGgUEZQPIh9dgPfmRgiUda6M/qHecfWDyzI3PEzskBh8VIX9Snbk3FT13pw nH2Z8qJblUD6/DqTcI6gBWihVY7Coy+Rcx8f0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bfXp2m+eG0fPw8rnLzBA4705O4L8LprWDujoyvgpuQg=; b=lqyYP3ttlWXEfELdoQeL/Sc6Ud68xBrdH2i5xRopNwCHsu6521njsoq93py0vtLpj+ LLoN2kcsPLURcuncy7c4uf2Ro9k6frOOkIIjyEVrLXLWqxVR+f7zGPjmnWVKogsV4XRv PvPFu1rsDdoLNJGqCgNNQk1ayqPB6ChHUQPElWYkGgesf898a4TCLwLx+r9YoVKxg4D/ sbQQQvzO90DjmJUwOAaCH+xxbRTgvYYOB07f7PE+spQi0YUUhumrOP598yCC0fIuBhnT PB0xEaMydmeL5wobWxHic51/QXyRzLmcPPfHcomIFiSlXvesuqiU5+27pNS70LwjQBcj nLbA== X-Gm-Message-State: AA+aEWZC6H2EaqkEAtV7w5l2d+0UbCnN5dx8qpUoG45Kv7XYB1ZufGxi kciD/lx8fE+OE38e2KuyFsyMIKSykH2e7A== X-Received: by 2002:a1c:6408:: with SMTP id y8mr14108517wmb.0.1542984372267; Fri, 23 Nov 2018 06:46:12 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:33 +0100 Message-Id: <20181123144558.5048-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 12/37] tcg/aarch64: Parameterize the temp for tcg_out_goto_long X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We cannot use TCG_REG_LR (aka TCG_REG_TMP) for tail calls. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 2.17.2 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index c0ba9a6d50..ea5fe33fca 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1134,14 +1134,15 @@ static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) tcg_out_insn(s, 3206, B, offset); } -static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target) +static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target, + TCGReg scratch) { ptrdiff_t offset = target - s->code_ptr; if (offset == sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, BL, offset); } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); - tcg_out_insn(s, 3207, BR, TCG_REG_TMP); + tcg_out_movi(s, TCG_TYPE_I64, scratch, (intptr_t)target); + tcg_out_insn(s, 3207, BR, scratch); } } @@ -1716,10 +1717,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ if (a0 == 0) { - tcg_out_goto_long(s, s->code_gen_epilogue); + tcg_out_goto_long(s, s->code_gen_epilogue, TCG_REG_TMP); } else { tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); - tcg_out_goto_long(s, tb_ret_addr); + tcg_out_goto_long(s, tb_ret_addr, TCG_REG_TMP); } break; From patchwork Fri Nov 23 14:45:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151888 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2217594ljp; Fri, 23 Nov 2018 06:55:50 -0800 (PST) X-Google-Smtp-Source: AFSGD/W7rQ6fddHYFvJORZUeoJcQ4x8Ujyh87b5ic8gT2KC9ln7CJWgCyJOETWhuEA6pje/vCSeX X-Received: by 2002:a25:6602:: with SMTP id a2-v6mr16017360ybc.75.1542984950765; Fri, 23 Nov 2018 06:55:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984950; cv=none; d=google.com; s=arc-20160816; b=1IKFxjly70J6Sb2x782T0W89sFMPyAbuc9T7T7f2bwKvYLmkinUuPJ20d8lzmp0vc+ Mb0kte9Pzs3uRbh/r5T3aDemIUu16qUWbeCRVP/a9i6Od+KXcogm8YOZoW9NE/6BXj+O DFhI5Qu/XakB3kwkYhRvJJWVKhEG82IRv414yku+toJT5qCtpqGLmk7Q9ZmwyiQHqBhE YgMFpwD4lbJU5lm+GFFcAFzMlC05esF/qceBueZDXRM5c5KEc1P/3K9/oi3p4eJJ/K9b R98oq/OZna/0Vlf0oXSywAhCHb0stzo1N4BBsPpD2j/kaZyq8VlydaSz73CrnN4Z2zq7 9VfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ZgQoWHRJcRFp4C9KfWwThoalEdmTxoVA/RPtSMYllzE=; b=rJS3jPjiHGcwkxUprCiXwRSbDkP+vCiRAdrVe+VpNTACxBxviJkrUFrT0aw3U/ZI7G crbFgj6PrqPI+DkuhoacTsQaaXfdjddxN9GdHT6DaHXiT15Aln5dyYhWq0nz9/QYnNbD 04di9jrZzM4YE+LmNVBrvJmBCE7z0QujePZLh5YJmiBuf5Ori4j0YQpLNiDQ/XkTQMHC cxkV47wYWUE3JXbesdSWVjRm58AxoEaePhZpczo1Zxs8IMMyMPhvJu46PzyzffpYAdrJ vZFv2uL8sc8gWZ8ICa7Si72UYcW+kcjlzmDU5ikeJV0T7TsdIOzvLhkeyvPFYgVxzty7 YghA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IO0lPlsc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id x67si22869138ywd.103.2018.11.23.06.55.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 06:55:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IO0lPlsc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52804 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCs1-00015L-V4 for patch@linaro.org; Fri, 23 Nov 2018 09:55:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43986) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCio-00085T-4c for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCik-0003IY-RO for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:18 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:37536) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCik-0003HE-L3 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:14 -0500 Received: by mail-wm1-x344.google.com with SMTP id p2-v6so12177621wmc.2 for ; Fri, 23 Nov 2018 06:46:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZgQoWHRJcRFp4C9KfWwThoalEdmTxoVA/RPtSMYllzE=; b=IO0lPlscYZimtQJ26EFSh6S+eEW6Zc8r8dMpVzjv8SKcV4NCG5qfwx7zPUtoI44WcV LdmtzqxvhhJQlohS1G7KOhDRPzHdLDwpIugVlPGyk8ZtVPB5mOyHhsp0rwu1L94edhV4 59SK759pIY7gziJNojCxeYhfvt/keSPgAE0yY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZgQoWHRJcRFp4C9KfWwThoalEdmTxoVA/RPtSMYllzE=; b=qyxSJ3aevbDoFrg9gNZ2oUA28ItUqyOCsWMTTpcWsrOQ+e79hqJECEwtI/m0BEb3Er VwsmvDwDPhJZlD0wzY5UwHZjKc20rmmQ3MXHVm1f+jZqKev55sYxuW683AzqrvPWP5c+ 5jZmqyq2OEz2bMxC+OMp9CVI77cTzSkfTxppyu8rP3jwqDtLCmY9iftbpnTC6x7LOhir imTleDI+FnmYuT3cTLnyBIA3moDaTcSrXocAnnBmYzk/vnWhvSv3ODdRS9MwP/WHz71y 5SkkdYLnTmG+E2quvt7apqs48wyK0WNHV42feUV/Qm7rhq3zH6j3/dsbJAibrqyOKc0q PIbw== X-Gm-Message-State: AA+aEWapGnRw35ufwSj8MpTENXDiBrSqkXNEmDLMfjptFrIl4l1TUT/d +t94m2fMM37vU/YNRpaI/QJoPzhkYq2OPw== X-Received: by 2002:a1c:7e8e:: with SMTP id z136mr15007888wmc.140.1542984373317; Fri, 23 Nov 2018 06:46:13 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:34 +0100 Message-Id: <20181123144558.5048-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 v2 13/37] tcg/aarch64: Use B not BL for tcg_out_goto_long X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This was a typo copying from tcg_out_call, apparently. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.2 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index ea5fe33fca..403f5caf14 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1139,7 +1139,7 @@ static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target, { ptrdiff_t offset = target - s->code_ptr; if (offset == sextract64(offset, 0, 26)) { - tcg_out_insn(s, 3206, BL, offset); + tcg_out_insn(s, 3206, B, offset); } else { tcg_out_movi(s, TCG_TYPE_I64, scratch, (intptr_t)target); tcg_out_insn(s, 3207, BR, scratch); From patchwork Fri Nov 23 14:45:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151882 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2211934ljp; Fri, 23 Nov 2018 06:50:37 -0800 (PST) X-Google-Smtp-Source: AFSGD/XjPfoMWIcjQvsE0cCaz2jhgujaKHHM4j+1RTob9esGpUM8oJouJ0odGF5jtVJtYSwjy4vs X-Received: by 2002:a81:c50d:: with SMTP id k13mr15344219ywi.42.1542984637654; Fri, 23 Nov 2018 06:50:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984637; cv=none; d=google.com; s=arc-20160816; b=UuQC1J5XUYZ2SGV55ORdota6N+vhfua8nxW5vh7bWuz1kAzYtJHscKEgWdIkJrU+pH vonmkI95pPlN4+J4LKDMOUCCwkxaGmYRgVK7wPyrqMMX+UA6YxI/XXigfIzD1btIFqei KDSGDRX5hvKXUN0aBGOHT41FwOaqgo0wVSquUHPwgfVl8a9Cuq3yKbmp5vM8RO2woc7j nwJc22B2UOJ7Ebvg+Yidy7NnGhqGlveKycosFL2/jzvpFjMdJ850NMZQ9ZF2E/EzmEzR o8rVIxhxAcsupw3jxrMTS76IkiwEhii9keFJ4zLynNG/zYek8wD+D9ig5uL7Rzz1LNeh GMLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=UrR/IldFdFkWy6ywHmFI8AClyOk1jWWQ8mWiO+LW0Iw=; b=SISXkLKbIiz24VL0MBfPmZUjp9/oTXXI5t5wyAowjGh3U71GkO9S/EeuU79NTtZayU KXGMJebauS+TPuxd+YKsLP7J6ZRt07OW+MYBfJqVAaR4O72lMgdvrDJWQJbJbnbJtabb rBQdOTToNGWcqYMCTLsb41caei0mTs73OV0PRM8D1OlvnJ0ZSnINXQXbC/Ba74CxyODW 7JaCCsfInmNlOYg5t8axoEa/WTGWZv50Sa5YnTCVIEwb1V3eMIRSFIErc/PbgP9IoJmp ncU8oRkGYb0VsUyir2uJBhR2kJEBGk3FPR7jdFDQcUCYAi4Mp6u930GhaV0yrxDXf+r5 SAgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FlGMdLNP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 14/37] tcg/aarch64: Use TCG_TARGET_NEED_LDST_OOL_LABELS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 191 +++++++++++++++++------------------ 2 files changed, 93 insertions(+), 100 deletions(-) -- 2.17.2 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 9aea1d1771..d1bd77c41d 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -146,7 +146,7 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU -#define TCG_TARGET_NEED_LDST_LABELS +#define TCG_TARGET_NEED_LDST_OOL_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 403f5caf14..8edea527f7 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -145,18 +145,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, ct->ct |= TCG_CT_REG; ct->u.regs |= 0xffffffff00000000ull; break; - case 'l': /* qemu_ld / qemu_st address, data_reg */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffffu; -#ifdef CONFIG_SOFTMMU - /* x0 and x1 will be overwritten when reading the tlb entry, - and x2, and x3 for helper args, better to avoid using them. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3); -#endif - break; case 'A': /* Valid for arithmetic immediate (positive or negative). */ ct->ct |= TCG_CT_CONST_AIMM; break; @@ -1378,7 +1366,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d, } #ifdef CONFIG_SOFTMMU -#include "tcg-ldst.inc.c" +#include "tcg-ldst-ool.inc.c" /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) @@ -1391,6 +1379,12 @@ static void * const qemu_ld_helpers[16] = { [MO_BEUW] = helper_be_lduw_mmu, [MO_BEUL] = helper_be_ldul_mmu, [MO_BEQ] = helper_be_ldq_mmu, + + [MO_SB] = helper_ret_ldsb_mmu, + [MO_LESW] = helper_le_ldsw_mmu, + [MO_LESL] = helper_le_ldsl_mmu, + [MO_BESW] = helper_be_ldsw_mmu, + [MO_BESL] = helper_be_ldsl_mmu, }; /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, @@ -1407,67 +1401,6 @@ static void * const qemu_st_helpers[16] = { [MO_BEQ] = helper_be_stq_mmu, }; -static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target) -{ - ptrdiff_t offset = tcg_pcrel_diff(s, target); - tcg_debug_assert(offset == sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi = lb->oi; - TCGMemOp opc = get_memop(oi); - TCGMemOp size = opc & MO_SIZE; - - reloc_pc19(lb->label_ptr[0], s->code_ptr); - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); - tcg_out_adr(s, TCG_REG_X3, lb->raddr); - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - if (opc & MO_SIGN) { - tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0); - } else { - tcg_out_mov(s, size == MO_64, lb->datalo_reg, TCG_REG_X0); - } - - tcg_out_goto(s, lb->raddr); -} - -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi = lb->oi; - TCGMemOp opc = get_memop(oi); - TCGMemOp size = opc & MO_SIZE; - - reloc_pc19(lb->label_ptr[0], s->code_ptr); - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi); - tcg_out_adr(s, TCG_REG_X4, lb->raddr); - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); - tcg_out_goto(s, lb->raddr); -} - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGType ext, TCGReg data_reg, TCGReg addr_reg, - tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->type = ext; - label->datalo_reg = data_reg; - label->addrlo_reg = addr_reg; - label->raddr = raddr; - label->label_ptr[0] = label_ptr; -} - /* * Load and compare a TLB entry, emitting the conditional jump to the * slow path on failure. Returns the register for the host addend. @@ -1644,19 +1577,22 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, TCGMemOpIdx oi, TCGType ext) { TCGMemOp memop = get_memop(oi); - const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; -#ifdef CONFIG_SOFTMMU - unsigned mem_index = get_mmuidx(oi); - tcg_insn_unit *label_ptr; - TCGReg base; - base = tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1, - TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3); - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - base, otype, addr_reg); - add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, - s->code_ptr, label_ptr); +#ifdef CONFIG_SOFTMMU + /* Ignore the requested "ext". We get the same correct result from + * a 16-bit sign-extended to 64-bit as we do sign-extended to 32-bit, + * and we create fewer out-of-line thunks. + */ + bool is_64 = (memop & MO_SIGN) || ((memop & MO_SIZE) == MO_64); + + tcg_debug_assert(data_reg == TCG_REG_X0); + tcg_debug_assert(addr_reg == TCG_REG_X1); + + add_ldst_ool_label(s, true, is_64, oi, R_AARCH64_JUMP26, 0); + tcg_out_insn(s, 3206, BL, 0); #else /* !CONFIG_SOFTMMU */ + const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + if (USE_GUEST_BASE) { tcg_out_qemu_ld_direct(s, memop, ext, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); @@ -1671,18 +1607,18 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, TCGMemOpIdx oi) { TCGMemOp memop = get_memop(oi); - const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; -#ifdef CONFIG_SOFTMMU - unsigned mem_index = get_mmuidx(oi); - tcg_insn_unit *label_ptr; - TCGReg base; - base = tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0, - TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3); - tcg_out_qemu_st_direct(s, memop, data_reg, base, otype, addr_reg); - add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64, - data_reg, addr_reg, s->code_ptr, label_ptr); +#ifdef CONFIG_SOFTMMU + bool is_64 = (memop & MO_SIZE) == MO_64; + + tcg_debug_assert(addr_reg == TCG_REG_X1); + tcg_debug_assert(data_reg == TCG_REG_X2); + + add_ldst_ool_label(s, false, is_64, oi, R_AARCH64_JUMP26, 0); + tcg_out_insn(s, 3206, BL, 0); #else /* !CONFIG_SOFTMMU */ + const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + if (USE_GUEST_BASE) { tcg_out_qemu_st_direct(s, memop, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); @@ -1693,6 +1629,52 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, #endif /* CONFIG_SOFTMMU */ } +#ifdef CONFIG_SOFTMMU +static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, + bool is_64, TCGMemOpIdx oi) +{ + const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + const TCGMemOp memop = get_memop(oi); + const unsigned mem_index = get_mmuidx(oi); + const TCGReg addr_reg = TCG_REG_X1; + const TCGReg data_reg = is_ld ? TCG_REG_X0 : TCG_REG_X2; + tcg_insn_unit * const thunk = s->code_ptr; + tcg_insn_unit *label; + TCGReg base, arg; + + base = tcg_out_tlb_read(s, addr_reg, memop, &label, mem_index, is_ld, + TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7); + + /* TLB Hit */ + if (is_ld) { + tcg_out_qemu_ld_direct(s, memop, is_64, data_reg, + base, otype, addr_reg); + } else { + tcg_out_qemu_st_direct(s, memop, data_reg, base, otype, addr_reg); + } + tcg_out_insn(s, 3207, RET, TCG_REG_LR); + + /* TLB Miss */ + reloc_pc19(label, s->code_ptr); + + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); + /* addr_reg and data_reg are already in place. */ + arg = is_ld ? TCG_REG_X2 : TCG_REG_X3; + tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); + tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_REG_LR); + + if (is_ld) { + tcg_out_goto_long(s, qemu_ld_helpers[memop & (MO_BSWAP | MO_SSIZE)], + TCG_REG_X7); + } else { + tcg_out_goto_long(s, qemu_st_helpers[memop & (MO_BSWAP | MO_SIZE)], + TCG_REG_X7); + } + + return thunk; +} +#endif + static tcg_insn_unit *tb_ret_addr; static void tcg_out_op(TCGContext *s, TCGOpcode opc, @@ -2262,10 +2244,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } }; static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } }; static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } }; - static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } }; static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } }; +#ifdef CONFIG_SOFTMMU + static const TCGTargetOpDef a_b = { .args_ct_str = { "a", "b" } }; + static const TCGTargetOpDef c_b = { .args_ct_str = { "c", "b" } }; +#endif static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } }; static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } }; @@ -2397,10 +2381,19 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_l; +#ifdef CONFIG_SOFTMMU + return &a_b; +#else + return &r_r; +#endif + case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return &lZ_l; +#ifdef CONFIG_SOFTMMU + return &c_b; +#else + return &r_r; +#endif case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: From patchwork Fri Nov 23 14:45:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151892 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2219303ljp; Fri, 23 Nov 2018 06:57:22 -0800 (PST) X-Google-Smtp-Source: AJdET5dUG6QrId+hbkGu23lrkSlyuo7Lf9O1LDavxTP3moH1fD7XF0o/G85Qqu6V82u6omw1iVgh X-Received: by 2002:a81:6104:: with SMTP id v4-v6mr16699800ywb.386.1542985042022; Fri, 23 Nov 2018 06:57:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985042; cv=none; d=google.com; s=arc-20160816; b=sqh3Rb3cM3UcXLzZNdTDCdFZEiokjZjEMQ0fTaa5cgsR15dgvS7ntGb6HD2oFB5gdN p9zQKn38p7J3etwsA+hzr5/l604s135+JiYa79oQMW9SaKm2t8cert5rullXQXnfuJJd lIpml8SBXLcnx5yukOD0Dx5NRaNrCZ+Uy3VhO499bxSBwnbNLn1t2xHXcZZggRZMZ9H7 v6EiAGnqhRHAxeagP+B/k00qRlgAQHJ82/OtjB64XxjDCl/SJfylkyvCej4PvizX5O7j NOuRH4io0sWelvVYME9FU0V92VT8EhbDKxyPOMa1pBLMjbCC6FuGW4mvQBnr2MIuNYpA 5kKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=8t7gEiP0UljdZGOq63+3IiIupXpsvdWUor96eMaww/U=; b=OswsrTemQyLTkGpcHC0Va2+GZfGhMpdiT7vyJrPHZwe0LEBFX5hvBIXlVkh+YJUdet 3weNekGDasa+B3/QYZYN1MJGspPcsqKl9vR6V0j9AgaffBjWrgZwh+Ai8EEI3SoBPYfq FDQapAm0oFI49Beyv56qs+YxpInPFIanV0CPAisbJk1hXXpULhJoh1t2HR4w4/054z64 7oy5YuhYiKawk1seZ9/JciaE4iMpBTljcXTtNFjAam/YBHtqSUgN+pnc2YQsy6pQZLiV nbT3BBeH6bxob67lx5t1dGDZs1BtzXlzb8sIsDhjJIU8HFeyjk470JdlWTqXxh+s6Q/q 9eXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Mqq7XUuC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 v2 15/37] tcg/arm: Parameterize the temps for tcg_out_tlb_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When moving the qemu_ld/st arguments to the right place for a function call, we'll need to move the temps out of the way. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 89 +++++++++++++++++++++------------------- 1 file changed, 46 insertions(+), 43 deletions(-) -- 2.17.2 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 80d174ef44..414c91c9ea 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1245,11 +1245,14 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, /* We're expecting to use an 8-bit immediate and to mask. */ QEMU_BUILD_BUG_ON(CPU_TLB_BITS > 8); -/* Load and compare a TLB entry, leaving the flags set. Returns the register - containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ - +/* + *Load and compare a TLB entry, leaving the flags set. Returns the register + * containing the addend of the tlb entry. Clobbers t0, t1, t2, t3. + * T0 and T1 must be consecutive for LDRD. + */ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - TCGMemOp opc, int mem_index, bool is_load) + TCGMemOp opc, int mem_index, bool is_load, + TCGReg t0, TCGReg t1, TCGReg t2, TCGReg t3) { TCGReg base = TCG_AREG0; int cmp_off = @@ -1262,36 +1265,37 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, unsigned a_bits = get_alignment_bits(opc); /* V7 generates the following: - * ubfx r0, addrlo, #TARGET_PAGE_BITS, #CPU_TLB_BITS - * add r2, env, #high - * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS - * ldr r0, [r2, #cmp] - * ldr r2, [r2, #add] - * movw tmp, #page_align_mask - * bic tmp, addrlo, tmp - * cmp r0, tmp + * ubfx t0, addrlo, #TARGET_PAGE_BITS, #CPU_TLB_BITS + * add t2, env, #high + * add t2, t2, r0, lsl #CPU_TLB_ENTRY_BITS + * ldr t0, [t2, #cmp] (and t1 w/ldrd) + * ldr t2, [t2, #add] + * movw t3, #page_align_mask + * bic t3, addrlo, t3 + * cmp t0, t3 * * Otherwise we generate: - * shr tmp, addrlo, #TARGET_PAGE_BITS - * add r2, env, #high - * and r0, tmp, #(CPU_TLB_SIZE - 1) - * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS - * ldr r0, [r2, #cmp] - * ldr r2, [r2, #add] + * shr t3, addrlo, #TARGET_PAGE_BITS + * add t2, env, #high + * and t0, t3, #(CPU_TLB_SIZE - 1) + * add t2, t2, t0, lsl #CPU_TLB_ENTRY_BITS + * ldr t0, [t2, #cmp] (and t1 w/ldrd) + * ldr t2, [t2, #add] * tst addrlo, #s_mask - * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS + * cmpeq t0, t3, lsl #TARGET_PAGE_BITS */ if (use_armv7_instructions) { - tcg_out_extract(s, COND_AL, TCG_REG_R0, addrlo, + tcg_out_extract(s, COND_AL, t0, addrlo, TARGET_PAGE_BITS, CPU_TLB_BITS); } else { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, t3, 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); } /* Add portions of the offset until the memory access is in range. * If we plan on using ldrd, reduce to an 8-bit offset; otherwise - * we can use a 12-bit offset. */ + * we can use a 12-bit offset. + */ if (use_armv6_instructions && TARGET_LONG_BITS == 64) { mask_off = 0xff; } else { @@ -1301,34 +1305,33 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, int shift = ctz32(cmp_off & ~mask_off) & ~1; int rot = ((32 - shift) << 7) & 0xf00; int addend = cmp_off & (0xff << shift); - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t2, base, rot | ((cmp_off >> shift) & 0xff)); - base = TCG_REG_R2; + base = t2; add_off -= addend; cmp_off -= addend; } if (!use_armv7_instructions) { - tcg_out_dat_imm(s, COND_AL, ARITH_AND, - TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); + tcg_out_dat_imm(s, COND_AL, ARITH_AND, t0, t3, CPU_TLB_SIZE - 1); } - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, - TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, t2, base, t0, + SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); /* Load the tlb comparator. Use ldrd if needed and available, but due to how the pointer needs setting up, ldm isn't useful. Base arm5 doesn't have ldrd, but armv5te does. */ if (use_armv6_instructions && TARGET_LONG_BITS == 64) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off); + tcg_out_ldrd_8(s, COND_AL, t0, t2, cmp_off); } else { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off); + tcg_out_ld32_12(s, COND_AL, t0, t2, cmp_off); if (TARGET_LONG_BITS == 64) { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2, cmp_off + 4); + tcg_out_ld32_12(s, COND_AL, t1, t2, cmp_off + 4); } } /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off); + tcg_out_ld32_12(s, COND_AL, t2, t2, add_off); /* Check alignment. We don't support inline unaligned acceses, but we can easily support overalignment checks. */ @@ -1341,29 +1344,27 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, int rot = encode_imm(mask); if (rot >= 0) { - tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo, + tcg_out_dat_imm(s, COND_AL, ARITH_BIC, t3, addrlo, rotl(mask, rot) | (rot << 7)); } else { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - addrlo, TCG_REG_TMP, 0); + tcg_out_movi32(s, COND_AL, t3, mask); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, t3, addrlo, t3, 0); } - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP, 0); + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, t0, t3, 0); } else { if (a_bits) { tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - 1); } tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R0, TCG_REG_TMP, - SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + 0, t0, t3, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); } if (TARGET_LONG_BITS == 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0); + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, t1, addrhi, 0); } - return TCG_REG_R2; + return t2; } /* Record the context of a call to the out of line helper code for the slow @@ -1629,7 +1630,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) #ifdef CONFIG_SOFTMMU mem_index = get_mmuidx(oi); - addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1); + addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1, + TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R14); /* This a conditional BL only to load a pointer within this opcode into LR for the slow path. We will not be using the value for a tail call. */ @@ -1760,7 +1762,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) #ifdef CONFIG_SOFTMMU mem_index = get_mmuidx(oi); - addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0); + addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0, + TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R14); tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); From patchwork Fri Nov 23 14:45:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151886 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2216046ljp; Fri, 23 Nov 2018 06:54:24 -0800 (PST) X-Google-Smtp-Source: AFSGD/VT5heCVILdXgexx4JcHXcihMgt958oRiycUGHmHPfHw/v49y5ZRO+ZWDRRI9vtddwKyLuM X-Received: by 2002:a25:504e:: with SMTP id e75-v6mr16212195ybb.41.1542984864848; Fri, 23 Nov 2018 06:54:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984864; cv=none; d=google.com; s=arc-20160816; b=M0bKvXO2JqiWfnQ2BwWPcppOtnE26Pl8Q2yO7TLQDtrQhyoJZSMvgM/O7parkVOHA5 RunlyodYXxjEK1LzquM58qmcU5KteBVHHijLEM3HKRbbCb6mRb5xTvZid7bV6F2PxlzJ T/3+NHibvXR0NIuzy2PKFYwk5cP6BOGI8mVRiCHOSkkVOnu1EFTbJvoQaUfIsPpv7Lyo sTa4BBGP4Kj2P4tW+RefdVUsKTWtm47lhQ4A7ehAD359hdRF5E/gIV0GidtWcM28dXqF pWFB7JWWheoSw0dv1psSYUHLLL/Zj5fYppvkcVeojMCZAB7tkq7AN0+js97JYRRzJ95o 9A9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=K9NRP+HhbIk1nF+G1KmKV31hLuf4u/VMHyrlWpIJenM=; b=SCVr5J4j/GrogYGvx7NdAO49tlse58TLvcJcYZsTvNJvR61Yk8VU/88LKZsPIBLSlt fI0zreRmpusp7wi8FIb1LL88TSeNas3xeI8WylRLoXrL+an4wIEBPrtQW4MkQVzuZLh1 yZCbtuTOb1cfLgNIjkEakcxjRY1nGQmZFxcNj0Zi0FilrMwKTstY6QKj8WkaPtnjNIhA xMDDf+M+gpxoVEMwfFbZw/lammls0BNMdpPj6FC/oKL7bDU8fCi+BvfkzlZHyn8dONah neX+MTz4QDCsqi4WCU77llBFj2X/thUf1JGbwxiKGEdmyJQCs8bCMdOM+2c6+XS9EEeK 1loA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=E5tklL5h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 16/37] tcg/arm: Add constraints for R0-R5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are function call arguments that we will need soon. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 414c91c9ea..4339c472e8 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -246,7 +246,12 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType type) { - switch (*ct_str++) { + char c = *ct_str++; + switch (c) { + case 'a' ... 'f': /* r0 - r5 */ + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_R0 + (c - 'a')); + break; case 'I': ct->ct |= TCG_CT_CONST_ARM; break; From patchwork Fri Nov 23 14:45:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151903 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2235435ljp; Fri, 23 Nov 2018 07:08:38 -0800 (PST) X-Google-Smtp-Source: AFSGD/W7TU82V064aPqeAw+HQcUJj/7fpJR1Z+Qyeb+09Dy3iv3oszKNJspF/YFwh2V24aHQ+hVW X-Received: by 2002:a9f:3e9b:: with SMTP id x27mr6989280uai.94.1542985718531; Fri, 23 Nov 2018 07:08:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985718; cv=none; d=google.com; s=arc-20160816; b=pxUG7TppfD3hsAIFVKJqELrhGfHy+bfayVgkm+jVDtY6FZfj2Q6cCQQtxo8GHRPN9l lSeU72c2vb8nQNX1I6r0Tloh+YhJaieeUKL/WpikTQO6xuG+5j1VwP1TvD7oRHVd3k7b yHHOhoA783hYDv9pF0bMDm5ARIxjwVTmc+2Tud2UyG2pqzbkTthBR4z5PNvlsuzCVmPV GJ0HQynaO7sC2iMPfkod2GfvdnNnZVj5QmMzlzhLJL71Z9Tn493ZvowNZDVy8+sZHb7D vLUqRm0dbtaTtChGy91fjRwvupyKAhUGyQ9nIhlWznVBMpkRfJLagu30UfTWOtQ1mcDY FuAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IfteVwIt0QRdTAT9d1pABeNMo7np6fWushm//ba1JvM=; b=yMV3UN4AqUROMHwQOK8+q50Tegv6rr74DS+w6uD2eFLXUTe+XrMIHRUJrLhajosY9/ EhPrrtjns+4LMO70NATMCUHAl2P83z2dd6flX07O1VpR6IRfeJtiwwCsZtFvZ7aG9yfY TSVM+cNY7t+lI/oKyJFmCOe/Ik1PoAq+jl/nD0i9YWbygj9u0qm0KyGwifgEMnu2QSWw TinfvFWRGN1I54zz3Q0aXoO6GFGHtsPL4x4GMLSRHVuoEQYooARYvsOjDF60YTcDz+XE z2UaQg04OU4r+i36oP4u5JltjLy4B8Kdn1wf2tsjCF1h3XgEcLZ69Ru35/cqu7ptYnZd D8yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g1oiuvpg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m28si12358195vsj.171.2018.11.23.07.08.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 07:08:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g1oiuvpg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52880 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD4P-0005ly-QF for patch@linaro.org; Fri, 23 Nov 2018 10:08:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44051) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCiv-0008Ui-UH for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCis-0003SS-7W for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:24 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:37564) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCiq-0003Nq-9G for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:22 -0500 Received: by mail-wr1-x443.google.com with SMTP id j10so12585832wru.4 for ; Fri, 23 Nov 2018 06:46:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IfteVwIt0QRdTAT9d1pABeNMo7np6fWushm//ba1JvM=; b=g1oiuvpgnRccF4d64LKl01YZBPEobjCeQmkwboWykH8/s4pya/BuT99VUsy9p7+Yfv trSFOs3vk7vr0X9M5hi09KrBzg8g10GdGSBxoKl35iWg8AS7i+CRxe/J0Vbz5emRKxIM S6vZp8Fw6AtULJchuV4Duv54M/4lc9ZX97gFw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IfteVwIt0QRdTAT9d1pABeNMo7np6fWushm//ba1JvM=; b=mN91md4tM+i+t8mJC6pX34DirVxCBWka/L0aZFaf3MV6vqBIqa+iQhEJFdLZkhea+T rA35HI9OH67efFWmPvbwF/2XOFFpp8sgLwZYL0jlPYTVbf8lQbfl6gGPRHP3Z7c98B7E l+Ky3cfa4pOOJ6Zdn3Jh+2WdQHpBUl5LIqcQ5K3kDJu59PDHTx5OxTKUsPKoR+F30Nyw zcPzMgVY92CyMN09MLAreNR+h+u2WLfOCMOMsc8NeMafGSxCOUbRbBfT8f/pl0BvR05X mnR/QENhFvgOb7j26mTEO8e0DEScUfltYk6JK1Fw1CtPJK51ZJrIR9AHka/TY/e5AwRs 3NLQ== X-Gm-Message-State: AA+aEWYd5hKJS+kaOGlfF39DU30ojK1k5loiN1FfUKOfQt4M3g4hol2U EfW1/Rp8DEXUBeog00Mr2HjSksjmOI9kVQ== X-Received: by 2002:adf:c888:: with SMTP id k8mr15338977wrh.6.1542984377475; Fri, 23 Nov 2018 06:46:17 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:38 +0100 Message-Id: <20181123144558.5048-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 v2 17/37] tcg/arm: Reduce the number of temps for tcg_out_tlb_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When moving the qemu_ld/st thunk out of line, we no longer have LR for use as a temporary. In the worst case we must make do with 3 temps, when dealing with a 64-bit guest address. This in turn imples that we cannot use LDRD anymore, as there are not enough temps. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 97 ++++++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 44 deletions(-) -- 2.17.2 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 4339c472e8..2deeb1f5d1 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1251,13 +1251,12 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, QEMU_BUILD_BUG_ON(CPU_TLB_BITS > 8); /* - *Load and compare a TLB entry, leaving the flags set. Returns the register - * containing the addend of the tlb entry. Clobbers t0, t1, t2, t3. - * T0 and T1 must be consecutive for LDRD. + * Load and compare a TLB entry, leaving the flags set. Returns the register + * containing the addend of the tlb entry. Clobbers t0, t1, t2. */ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, TCGMemOp opc, int mem_index, bool is_load, - TCGReg t0, TCGReg t1, TCGReg t2, TCGReg t3) + TCGReg t0, TCGReg t1, TCGReg t2) { TCGReg base = TCG_AREG0; int cmp_off = @@ -1265,49 +1264,64 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write)); int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend); - int mask_off; unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); /* V7 generates the following: * ubfx t0, addrlo, #TARGET_PAGE_BITS, #CPU_TLB_BITS * add t2, env, #high - * add t2, t2, r0, lsl #CPU_TLB_ENTRY_BITS - * ldr t0, [t2, #cmp] (and t1 w/ldrd) + * add t2, t2, t0, lsl #CPU_TLB_ENTRY_BITS + * ldr t0, [t2, #cmp] * ldr t2, [t2, #add] - * movw t3, #page_align_mask - * bic t3, addrlo, t3 - * cmp t0, t3 + * movw t1, #page_align_mask + * bic t1, addrlo, t1 + * cmp t0, t1 + * + * ubfx t0, addrlo, #TPB, #CTB -- 64-bit address + * add t2, env, #high + * add t2, t2, t0, lsl #CTEB + * ldr t0, [t2, #cmplo] + * movw t1, #page_align_mask + * bic t1, addrlo, t1 + * cmp t0, t1 + * ldr t0, [t2, #cmphi] + * ldr t2, [t2, #add] + * cmpeq t0, addrhi * * Otherwise we generate: * shr t3, addrlo, #TARGET_PAGE_BITS * add t2, env, #high * and t0, t3, #(CPU_TLB_SIZE - 1) * add t2, t2, t0, lsl #CPU_TLB_ENTRY_BITS - * ldr t0, [t2, #cmp] (and t1 w/ldrd) + * ldr t0, [t2, #cmp] * ldr t2, [t2, #add] * tst addrlo, #s_mask * cmpeq t0, t3, lsl #TARGET_PAGE_BITS + * + * shr t1, addrlo, #TPB -- 64-bit address + * add t2, env, #high + * and t0, t1, #CTS-1 + * add t2, t2, t0, lsl #CTEB + * ldr t0, [t2, #cmplo] + * tst addrlo, #s_mask + * cmpeq t0, t1, lsl #TBP + * ldr t0, [t2, #cmphi] + * ldr t2, [t2, #add] + * cmpeq t0, addrhi */ if (use_armv7_instructions) { tcg_out_extract(s, COND_AL, t0, addrlo, TARGET_PAGE_BITS, CPU_TLB_BITS); } else { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, t3, + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, t1, 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); } /* Add portions of the offset until the memory access is in range. - * If we plan on using ldrd, reduce to an 8-bit offset; otherwise - * we can use a 12-bit offset. + * We are not using ldrd, so we can use a 12-bit offset. */ - if (use_armv6_instructions && TARGET_LONG_BITS == 64) { - mask_off = 0xff; - } else { - mask_off = 0xfff; - } - while (cmp_off > mask_off) { - int shift = ctz32(cmp_off & ~mask_off) & ~1; + while (cmp_off > 0xfff) { + int shift = ctz32(cmp_off & ~0xfff) & ~1; int rot = ((32 - shift) << 7) & 0xf00; int addend = cmp_off & (0xff << shift); tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t2, base, @@ -1318,25 +1332,13 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, } if (!use_armv7_instructions) { - tcg_out_dat_imm(s, COND_AL, ARITH_AND, t0, t3, CPU_TLB_SIZE - 1); + tcg_out_dat_imm(s, COND_AL, ARITH_AND, t0, t1, CPU_TLB_SIZE - 1); } tcg_out_dat_reg(s, COND_AL, ARITH_ADD, t2, base, t0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); - /* Load the tlb comparator. Use ldrd if needed and available, - but due to how the pointer needs setting up, ldm isn't useful. - Base arm5 doesn't have ldrd, but armv5te does. */ - if (use_armv6_instructions && TARGET_LONG_BITS == 64) { - tcg_out_ldrd_8(s, COND_AL, t0, t2, cmp_off); - } else { - tcg_out_ld32_12(s, COND_AL, t0, t2, cmp_off); - if (TARGET_LONG_BITS == 64) { - tcg_out_ld32_12(s, COND_AL, t1, t2, cmp_off + 4); - } - } - - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, t2, t2, add_off); + /* Load the tlb comparator (low part). */ + tcg_out_ld32_12(s, COND_AL, t0, t2, cmp_off); /* Check alignment. We don't support inline unaligned acceses, but we can easily support overalignment checks. */ @@ -1349,24 +1351,31 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, int rot = encode_imm(mask); if (rot >= 0) { - tcg_out_dat_imm(s, COND_AL, ARITH_BIC, t3, addrlo, + tcg_out_dat_imm(s, COND_AL, ARITH_BIC, t1, addrlo, rotl(mask, rot) | (rot << 7)); } else { - tcg_out_movi32(s, COND_AL, t3, mask); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, t3, addrlo, t3, 0); + tcg_out_movi32(s, COND_AL, t1, mask); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, t1, addrlo, t1, 0); } - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, t0, t3, 0); + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, t0, t1, 0); } else { if (a_bits) { tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - 1); } tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, - 0, t0, t3, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + 0, t0, t1, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); } + /* Load the tlb comparator (high part). */ if (TARGET_LONG_BITS == 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, t1, addrhi, 0); + tcg_out_ld32_12(s, COND_AL, t0, t2, cmp_off + 4); + } + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, t2, t2, add_off); + + if (TARGET_LONG_BITS == 64) { + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, t0, addrhi, 0); } return t2; @@ -1636,7 +1645,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) #ifdef CONFIG_SOFTMMU mem_index = get_mmuidx(oi); addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1, - TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R14); + TCG_REG_R0, TCG_REG_R1, TCG_REG_TMP); /* This a conditional BL only to load a pointer within this opcode into LR for the slow path. We will not be using the value for a tail call. */ @@ -1768,7 +1777,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) #ifdef CONFIG_SOFTMMU mem_index = get_mmuidx(oi); addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0, - TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R14); + TCG_REG_R0, TCG_REG_R1, TCG_REG_TMP); tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); From patchwork Fri Nov 23 14:45:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151904 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2235753ljp; Fri, 23 Nov 2018 07:08:51 -0800 (PST) X-Google-Smtp-Source: AFSGD/XtJaTC0Dhdu9Nq0s/0ZiFkGS9bEK21vanhjvxqHv7Hpy4KLxjfQr3eNejE6j423qQK+Rlq X-Received: by 2002:a37:8f02:: with SMTP id r2mr4196615qkd.246.1542985731408; Fri, 23 Nov 2018 07:08:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985731; cv=none; d=google.com; s=arc-20160816; b=hznYieLtnXyjA3khnt45qwYKQSnQ7boFRjn2W+zjMbAXsh+qt1Jh6ixTfcnmE5hM/r eDfyhz85/J63Odz4ssy/g5tnTrX96trDz3BNunQz9ttB7wX/qe9P43IdDhfYdcBJBDXi GaI7Qzj5zjLGpgzUACIzaSRRauPzdzHSIBwwFKn9f4pbF+bL88+EDIvWN8glY9WGTF6q tLBL5nD53fF3T5WBcJyKUtWYvC4h7zkYLuVaiCdt7qg/lPlMgRfVWPNmlNeQ/LYPKKQe Cx0atENSjSxoF7GAYcrPopAe4k8xQZFGar/T7nNwtb6vywvFebOFV4wAIL4oDGGFCJJV nIeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=XzP/1RMAHcHXzxJDoQwNYCK5LC+cbzzfmGI/RlU+HSs=; b=RuHi9zwxkYhHnQhPnG0kZSwh0bxWAgKApy8OmkpQGTmz7fJvMHg+cIgwFJh+9WSI8N qXLoTUdfGWHUwpPcfSJPDWtzKTitOd5IGZgu/OipOkY9KvIeQA3QGpAabXt5XWLisR1y RX2cqM59+uhpgA6hDNSCk0tbvYVhOWQqhZhshsGvlZdikdzAagz/Tsm5l+8kFA3X9om5 iYdWOPiZxDv2QdOtTuRKwrnM05n/05mhM0MplOkVf8v76GMeZZ0TGNjamN8iZSeNJ8HK VPqAmCn/pta8ieydEtKXLO9T47YKvJvgzVu3iStX12mpQYWs38czZ+1Bnew+1CcxBbZ9 1TIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=J98NTb6X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.0 v2 18/37] tcg/arm: Force qemu_ld/st arguments into fixed registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is an incremental step toward moving the qemu_ld/st code sequence out of line. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 113 +++++++++++++++++++++++++-------------- 1 file changed, 73 insertions(+), 40 deletions(-) -- 2.17.2 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 2deeb1f5d1..6b89ac7983 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -270,37 +270,13 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, ct->u.regs = 0xffff; break; - /* qemu_ld address */ - case 'l': - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; -#ifdef CONFIG_SOFTMMU - /* r0-r2,lr will be overwritten when reading the tlb entry, - so don't use these. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); -#endif - break; - /* qemu_st address & data */ case 's': ct->ct |= TCG_CT_REG; ct->u.regs = 0xffff; - /* r0-r2 will be overwritten when reading the tlb entry (softmmu only) - and r0-r1 doing the byte swapping, so don't use these. */ + /* r0-r1 doing the byte swapping, so don't use these */ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); -#if defined(CONFIG_SOFTMMU) - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); -#if TARGET_LONG_BITS == 64 - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); -#endif - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); -#endif break; default: @@ -1630,8 +1606,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) TCGMemOpIdx oi; TCGMemOp opc; #ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; + int mem_index, avail; + TCGReg addend, t0, t1; tcg_insn_unit *label_ptr; #endif @@ -1644,8 +1620,20 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) #ifdef CONFIG_SOFTMMU mem_index = get_mmuidx(oi); + + avail = 0xf; + avail &= ~(1 << addrlo); + if (TARGET_LONG_BITS == 64) { + avail &= ~(1 << addrhi); + } + tcg_debug_assert(avail & 1); + t0 = TCG_REG_R0; + avail &= ~1; + tcg_debug_assert(avail != 0); + t1 = ctz32(avail); + addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1, - TCG_REG_R0, TCG_REG_R1, TCG_REG_TMP); + t0, t1, TCG_REG_TMP); /* This a conditional BL only to load a pointer within this opcode into LR for the slow path. We will not be using the value for a tail call. */ @@ -1762,8 +1750,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) TCGMemOpIdx oi; TCGMemOp opc; #ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; + int mem_index, avail; + TCGReg addend, t0, t1; tcg_insn_unit *label_ptr; #endif @@ -1776,8 +1764,24 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) #ifdef CONFIG_SOFTMMU mem_index = get_mmuidx(oi); + + avail = 0xf; + avail &= ~(1 << addrlo); + avail &= ~(1 << datalo); + if (TARGET_LONG_BITS == 64) { + avail &= ~(1 << addrhi); + } + if (is64) { + avail &= ~(1 << datahi); + } + tcg_debug_assert(avail & 1); + t0 = TCG_REG_R0; + avail &= ~1; + tcg_debug_assert(avail != 0); + t1 = ctz32(avail); + addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0, - TCG_REG_R0, TCG_REG_R1, TCG_REG_TMP); + t0, t1, TCG_REG_TMP); tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); @@ -2118,11 +2122,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } }; - static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; + static const TCGTargetOpDef a_b = { .args_ct_str = { "a", "b" } }; + static const TCGTargetOpDef c_b = { .args_ct_str = { "c", "b" } }; static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } }; - static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } }; static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } }; + static const TCGTargetOpDef a_c_d = { .args_ct_str = { "a", "c", "d" } }; + static const TCGTargetOpDef a_b_b = { .args_ct_str = { "a", "b", "b" } }; + static const TCGTargetOpDef e_c_d = { .args_ct_str = { "e", "c", "d" } }; + static const TCGTargetOpDef e_f_b = { .args_ct_str = { "e", "f", "b" } }; static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; static const TCGTargetOpDef r_r_rIN @@ -2131,10 +2138,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) = { .args_ct_str = { "r", "r", "rIK" } }; static const TCGTargetOpDef r_r_r_r = { .args_ct_str = { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l_l - = { .args_ct_str = { "r", "r", "l", "l" } }; static const TCGTargetOpDef s_s_s_s = { .args_ct_str = { "s", "s", "s", "s" } }; + static const TCGTargetOpDef a_b_c_d + = { .args_ct_str = { "a", "b", "c", "d" } }; + static const TCGTargetOpDef e_f_c_d + = { .args_ct_str = { "e", "f", "c", "d" } }; static const TCGTargetOpDef br = { .args_ct_str = { "r", "rIN" } }; static const TCGTargetOpDef dep @@ -2215,13 +2224,37 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return &setc2; case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l; + if (!USING_SOFTMMU) { + return TARGET_LONG_BITS == 32 ? &r_r : &r_r_r; + } else if (TARGET_LONG_BITS == 32) { + return &a_b; /* temps available r0, r2, r3, r12 */ + } else { + return &a_c_d; /* temps available r0, r1, r12 */ + } case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l; + if (!USING_SOFTMMU) { + return TARGET_LONG_BITS == 32 ? &r_r_r : &r_r_r_r; + } else if (TARGET_LONG_BITS == 32) { + return &a_b_b; /* temps available r0, r2, r3, r12 */ + } else { + return &a_b_c_d; /* temps available r0, r1, r12 */ + } case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s; + if (!USING_SOFTMMU) { + return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s; + } else if (TARGET_LONG_BITS == 32) { + return &c_b; /* temps available r0, r3, r12 */ + } else { + return &e_c_d; /* temps available r0, r1, r12 */ + } case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s; + if (!USING_SOFTMMU) { + return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s; + } else if (TARGET_LONG_BITS == 32) { + return &e_f_b; /* temps available r0, r2, r3, r12 */ + } else { + return &e_f_c_d; /* temps available r0, r1, r12 */ + } default: return NULL; From patchwork Fri Nov 23 14:45:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151905 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2236053ljp; Fri, 23 Nov 2018 07:09:03 -0800 (PST) X-Google-Smtp-Source: AJdET5eBA7Oyec/gQUbnFGYIdMdgHuR6CceulfFrSBJ2mGhyN+/+ShbJ9EGRgXHdjNpJuZIMCv7f X-Received: by 2002:aed:3a22:: with SMTP id n31mr14904718qte.29.1542985743259; Fri, 23 Nov 2018 07:09:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985743; cv=none; d=google.com; s=arc-20160816; b=OM10jSkJYEivuefATt3saWQBHajYbeqTdeYsv/0o0lOS8GqHGnOEzskclCBwesfWiY vIM42By58gRygW5PnE+zBMtns9DMnUytttzuGZGObIl12HH3vn1iIzpcG5YrcBZCvMMj vgJluH4JKA7PiILdMBAOdMgr+YOHYlFc8py8TP+MfG1+wXRoKKFYqOdl/CM2ord+sUlB 6g0wpfBnpBwk0AMw5znz45sSxVMaNvwUtnH3kOBMga3Ra7BMdF+8xuCX1+TLeeL5KdD6 8a+mHjMJrSdA8NCkO6HrBIUmd5UNx/tgzlLKFK7Al1wj90BgHBI+mtL0BxKPO3lK0D2Q gt5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=yJf+mKna6oyCQX+8QLpW7ASUSLIfMAQTCAnpD7BKT6k=; b=zNcp4Zql6ctUbHTz0Bac9gm2QlmeEhQAZLkQcTcIoFGPeTOPTuncK/gKZ7NMO41/h/ oHcIINyKdRNtP2b8MJGjLgMzEocXnX+h+bZ0fnS+nsKWnM6MgmmbatJS5RNZmijsyg1f p6SrqK9YEJVoLc1bo3b8LQe8lpPU9uoPEsSuTorhE34QWih1uPpCYkqX9sdU8vZ91thX 6inCQKdfoTi45C27FItmNKFSwzKQwP4f2R2gIRM0v0TSfLulpMsN60NlPITqCGVWit8f RO5626ne27RDeehuPjSclWOEBBCaHDFsG1mkGRH/YH2lha9qVhetf+KtHr29Z421lwQ+ Ujag== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VwzHPYs9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 19/37] tcg/arm: Use TCG_TARGET_NEED_LDST_OOL_LABELS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.inc.c | 314 ++++++++++++++++----------------------- 2 files changed, 125 insertions(+), 191 deletions(-) -- 2.17.2 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 94b3578c55..02981abdcc 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -141,7 +141,7 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU -#define TCG_TARGET_NEED_LDST_LABELS +#define TCG_TARGET_NEED_LDST_OOL_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 6b89ac7983..5a15f6a546 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1133,7 +1133,7 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, } #ifdef CONFIG_SOFTMMU -#include "tcg-ldst.inc.c" +#include "tcg-ldst-ool.inc.c" /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1356,128 +1356,6 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, return t2; } - -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGReg datalo, TCGReg datahi, TCGReg addrlo, - TCGReg addrhi, tcg_insn_unit *raddr, - tcg_insn_unit *label_ptr) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->datalo_reg = datalo; - label->datahi_reg = datahi; - label->addrlo_reg = addrlo; - label->addrhi_reg = addrhi; - label->raddr = raddr; - label->label_ptr[0] = label_ptr; -} - -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGReg argreg, datalo, datahi; - TCGMemOpIdx oi = lb->oi; - TCGMemOp opc = get_memop(oi); - void *func; - - reloc_pc24(lb->label_ptr[0], s->code_ptr); - - argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); - if (TARGET_LONG_BITS == 64) { - argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg); - } else { - argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - argreg = tcg_out_arg_imm32(s, argreg, oi); - argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14); - - /* For armv6 we can use the canonical unsigned helpers and minimize - icache usage. For pre-armv6, use the signed helpers since we do - not have a single insn sign-extend. */ - if (use_armv6_instructions) { - func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]; - } else { - func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]; - if (opc & MO_SIGN) { - opc = MO_UL; - } - } - tcg_out_call(s, func); - - datalo = lb->datalo_reg; - datahi = lb->datahi_reg; - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_out_ext8s(s, COND_AL, datalo, TCG_REG_R0); - break; - case MO_SW: - tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0); - break; - default: - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - break; - case MO_Q: - if (datalo != TCG_REG_R1) { - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - } else if (datahi != TCG_REG_R0) { - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - } else { - tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP); - } - break; - } - - tcg_out_goto(s, COND_AL, lb->raddr); -} - -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGReg argreg, datalo, datahi; - TCGMemOpIdx oi = lb->oi; - TCGMemOp opc = get_memop(oi); - - reloc_pc24(lb->label_ptr[0], s->code_ptr); - - argreg = TCG_REG_R0; - argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0); - if (TARGET_LONG_BITS == 64) { - argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg); - } else { - argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - - datalo = lb->datalo_reg; - datahi = lb->datahi_reg; - switch (opc & MO_SIZE) { - case MO_8: - argreg = tcg_out_arg_reg8(s, argreg, datalo); - break; - case MO_16: - argreg = tcg_out_arg_reg16(s, argreg, datalo); - break; - case MO_32: - default: - argreg = tcg_out_arg_reg32(s, argreg, datalo); - break; - case MO_64: - argreg = tcg_out_arg_reg64(s, argreg, datalo, datahi); - break; - } - - argreg = tcg_out_arg_imm32(s, argreg, oi); - argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14); - - /* Tail-call to the helper, which will return to the fast path. */ - tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); -} #endif /* SOFTMMU */ static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc, @@ -1602,14 +1480,12 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); + TCGReg addrlo __attribute__((unused)); + TCGReg addrhi __attribute__((unused)); + TCGReg datalo __attribute__((unused)); + TCGReg datahi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index, avail; - TCGReg addend, t0, t1; - tcg_insn_unit *label_ptr; -#endif datalo = *args++; datahi = (is64 ? *args++ : 0); @@ -1619,32 +1495,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) opc = get_memop(oi); #ifdef CONFIG_SOFTMMU - mem_index = get_mmuidx(oi); - - avail = 0xf; - avail &= ~(1 << addrlo); - if (TARGET_LONG_BITS == 64) { - avail &= ~(1 << addrhi); - } - tcg_debug_assert(avail & 1); - t0 = TCG_REG_R0; - avail &= ~1; - tcg_debug_assert(avail != 0); - t1 = ctz32(avail); - - addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1, - t0, t1, TCG_REG_TMP); - - /* This a conditional BL only to load a pointer within this opcode into LR - for the slow path. We will not be using the value for a tail call. */ - label_ptr = s->code_ptr; - tcg_out_bl_noaddr(s, COND_NE); - - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend); - - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ + add_ldst_ool_label(s, true, is64, oi, R_ARM_PC24, 0); + tcg_out_bl_noaddr(s, COND_AL); +#else if (guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP); @@ -1746,14 +1599,12 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); + TCGReg addrlo __attribute__((unused)); + TCGReg addrhi __attribute__((unused)); + TCGReg datalo __attribute__((unused)); + TCGReg datahi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index, avail; - TCGReg addend, t0, t1; - tcg_insn_unit *label_ptr; -#endif datalo = *args++; datahi = (is64 ? *args++ : 0); @@ -1763,35 +1614,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) opc = get_memop(oi); #ifdef CONFIG_SOFTMMU - mem_index = get_mmuidx(oi); - - avail = 0xf; - avail &= ~(1 << addrlo); - avail &= ~(1 << datalo); - if (TARGET_LONG_BITS == 64) { - avail &= ~(1 << addrhi); - } - if (is64) { - avail &= ~(1 << datahi); - } - tcg_debug_assert(avail & 1); - t0 = TCG_REG_R0; - avail &= ~1; - tcg_debug_assert(avail != 0); - t1 = ctz32(avail); - - addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0, - t0, t1, TCG_REG_TMP); - - tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); - - /* The conditional call must come last, as we're going to return here. */ - label_ptr = s->code_ptr; - tcg_out_bl_noaddr(s, COND_NE); - - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ + add_ldst_ool_label(s, false, is64, oi, R_ARM_PC24, 0); + tcg_out_bl_noaddr(s, COND_AL); +#else if (guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); tcg_out_qemu_st_index(s, COND_AL, opc, datalo, @@ -1802,6 +1627,115 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) #endif } +#ifdef CONFIG_SOFTMMU +static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, + bool is_64, TCGMemOpIdx oi) +{ + TCGReg addrlo, addrhi, datalo, datahi, addend, argreg, t0, t1; + TCGMemOp opc = get_memop(oi); + int mem_index = get_mmuidx(oi); + tcg_insn_unit *thunk = s->code_ptr; + tcg_insn_unit *label; + uintptr_t func; + int avail; + + /* Pick out where the arguments are located. A 64-bit address is + * aligned in the register pair R2:R3. Loads return into R0:R1. + * A 32-bit store with a 32-bit address has room at R2, but + * otherwise uses R4:R5. + */ + if (TARGET_LONG_BITS == 64) { + addrlo = TCG_REG_R2, addrhi = TCG_REG_R3; + } else { + addrlo = TCG_REG_R1, addrhi = -1; + } + if (is_ld) { + datalo = TCG_REG_R0; + } else if (TARGET_LONG_BITS == 64 || is_64) { + datalo = TCG_REG_R4; + } else { + datalo = TCG_REG_R2; + } + datahi = (is_64 ? datalo + 1 : -1); + + /* We need 3 call-clobbered temps. One of them is always R12, + * one of them is always R0. The third is somewhere in R[1-3]. + */ + avail = 0xf; + avail &= ~(1 << addrlo); + if (TARGET_LONG_BITS == 64) { + avail &= ~(1 << addrhi); + } + if (!is_ld) { + avail &= ~(1 << datalo); + if (is_64) { + avail &= ~(1 << datahi); + } + } + tcg_debug_assert(avail & 1); + t0 = TCG_REG_R0; + avail &= ~1; + tcg_debug_assert(avail != 0); + t1 = ctz32(avail); + + addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, is_ld, + t0, t1, TCG_REG_TMP); + + label = s->code_ptr; + tcg_out_b_noaddr(s, COND_NE); + + /* TCG Hit. */ + if (is_ld) { + tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend); + } else { + tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi, addrlo, addend); + } + tcg_out_bx(s, COND_AL, TCG_REG_R14); + + /* TLB Miss. */ + reloc_pc24(label, s->code_ptr); + + tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); + /* addrlo and addrhi are in place -- see above */ + argreg = addrlo + (TARGET_LONG_BITS / 32); + if (!is_ld) { + switch (opc & MO_SIZE) { + case MO_8: + argreg = tcg_out_arg_reg8(s, argreg, datalo); + break; + case MO_16: + argreg = tcg_out_arg_reg16(s, argreg, datalo); + break; + case MO_32: + argreg = tcg_out_arg_reg32(s, argreg, datalo); + break; + case MO_64: + argreg = tcg_out_arg_reg64(s, argreg, datalo, datahi); + break; + default: + g_assert_not_reached(); + } + } + argreg = tcg_out_arg_imm32(s, argreg, oi); + argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14); + + /* Tail call to the helper. */ + if (is_ld) { + func = (uintptr_t)qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]; + } else { + func = (uintptr_t)qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]; + } + if (use_armv7_instructions) { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, func); + tcg_out_bx(s, COND_AL, TCG_REG_TMP); + } else { + tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, func); + } + + return thunk; +} +#endif + static tcg_insn_unit *tb_ret_addr; static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, From patchwork Fri Nov 23 14:45:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151909 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2239826ljp; Fri, 23 Nov 2018 07:11:41 -0800 (PST) X-Google-Smtp-Source: AJdET5dQ1GlPkRLpv6yC/Cbe6pI5XSIdLPI/hRwNbJ+iJX21muoEZri16rBYKUUxPCsAWaTIkGYy X-Received: by 2002:a81:33c4:: with SMTP id z187mr16994156ywz.294.1542985901634; Fri, 23 Nov 2018 07:11:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985901; cv=none; d=google.com; s=arc-20160816; b=qfPwiaW9e20VqDu4siAzxcBq6rYebXevX7DQPRCmiCP+W8DFdFGGOkC9kEhE9b4Gxy jS1abKcNwoRU6joO2YD9TVtM/H4NwdI0SzxUjoxa+M4qepIk1iYkiBuSVDtG3hIFPjT8 oKmCOcNu41RDPjpzhtiP2SI7YR1xN9W0Cfgfud4h3uChaKQ99+BQGtHp29QtUnYF36c9 B5KCQ6ImNJsZeEpOW5mjV2IrKw+Jd+Y9P23P6rjKaMi7USd4BByw8UL42xThqojha+I4 xP2F50XM0oKaQe1fT1DnzTOgR0MM8iL69t0/2KEWaYnvhs82t7YFmRWXT3RSfYkBfomT hV4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=E5nUlX178Yhhbrid2SVbDu1cU354OJxLXoIiQ6IH5Bw=; b=GhYhFU92Ig4khO9is1en4Jtj3o2x2VHIRxNi3RPHsasc9ZkMnvPyjVIuXT8esgoVFQ 2hORLvcGFyNj4pLGk/ph+UxvXdDKe6OauNWE3x+mjH2slGi5UESmdRCaj9Vt4cltTLCL TCS0ZkIgKV1/YJL/5JxgTlWvT506PZYlyhg9MFjU/FiVkNgfalVhOo4hEgjyb8R9fiW5 En4q9ZUHn0QJ54kP46O4xhaQaQGbzwMoJ9+dKsEk2lXw1LzpnvxJklg8v681PvrLRjDt zihjehHLt09sIs+shBorZWAn89w9JMHrNi1EP9EYMQaTIAbgSomj38YsCF9wTzMEFzF+ SlZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Wn7I2EsK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 v2 20/37] tcg/ppc: Parameterize the temps for tcg_out_tlb_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When moving the qemu_ld/st arguments to the right place for a function call, we'll need to move the temps out of the way. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) -- 2.17.2 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 656a9ff603..6e656cd41e 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1516,12 +1516,14 @@ static void * const qemu_st_helpers[16] = { }; /* Perform the TLB load and compare. Places the result of the comparison - in CR7, loads the addend of the TLB into R3, and returns the register - containing the guest address (zero-extended into R4). Clobbers R0 and R2. */ + in CR7, loads the addend of the TLB, and returns the register containing + the guest address, places the addend into T0. + Clobbers t0, t1, TCG_REG_R0, TCG_REG_TMP1. */ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, TCGReg addrlo, TCGReg addrhi, - int mem_index, bool is_read) + int mem_index, bool is_read, + TCGReg t0, TCGReg t1) { int cmp_off = (is_read @@ -1536,10 +1538,10 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, if (TCG_TARGET_REG_BITS == 64) { if (TARGET_LONG_BITS == 32) { /* Zero-extend the address into a place helpful for further use. */ - tcg_out_ext32u(s, TCG_REG_R4, addrlo); - addrlo = TCG_REG_R4; + tcg_out_ext32u(s, t1, addrlo); + addrlo = t1; } else { - tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo, + tcg_out_rld(s, RLDICL, t0, addrlo, 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS); } } @@ -1559,27 +1561,27 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, /* Extraction and shifting, part 2. */ if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) { - tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo, + tcg_out_rlw(s, RLWINM, t0, addrlo, 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS), 31 - CPU_TLB_ENTRY_BITS); } else { - tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS); + tcg_out_shli64(s, t0, t0, CPU_TLB_ENTRY_BITS); } - tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base)); + tcg_out32(s, ADD | TAB(t0, t0, base)); /* Load the tlb comparator. */ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4); + tcg_out_ld(s, TCG_TYPE_I32, t1, t0, cmp_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, t0, cmp_off + 4); } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, t0, cmp_off); } /* Load the TLB addend for use on the fast path. Do this asap to minimize any load use delay. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off); + tcg_out_ld(s, TCG_TYPE_PTR, t0, t0, add_off); /* Clear the non-page, non-alignment bits from the address */ if (TCG_TARGET_REG_BITS == 32) { @@ -1624,7 +1626,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, 0, 7, TCG_TYPE_I32); - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32); + tcg_out_cmp(s, TCG_COND_EQ, addrhi, t1, 0, 6, TCG_TYPE_I32); tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); } else { tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, @@ -1778,13 +1780,14 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) #ifdef CONFIG_SOFTMMU mem_index = get_mmuidx(oi); - addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true); + rbase = TCG_REG_R3; + addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true, + rbase, TCG_REG_R4); /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr = s->code_ptr; tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - rbase = TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ rbase = guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { @@ -1853,13 +1856,14 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #ifdef CONFIG_SOFTMMU mem_index = get_mmuidx(oi); - addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false); + rbase = TCG_REG_R3; + addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false, + rbase, TCG_REG_R4); /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr = s->code_ptr; tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - rbase = TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ rbase = guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { From patchwork Fri Nov 23 14:45:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151902 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2235407ljp; Fri, 23 Nov 2018 07:08:37 -0800 (PST) X-Google-Smtp-Source: AFSGD/VKeuVbGKylkXJjQx9zmw5cGWixIAgNRfwD5mfa8tcvZem4drmPhcB1/o+pQ0QwyYHBmOhr X-Received: by 2002:a0c:e789:: with SMTP id x9mr15138230qvn.245.1542985717522; Fri, 23 Nov 2018 07:08:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985717; cv=none; d=google.com; s=arc-20160816; b=UCOZPdO+Jd6humF2liXvPW37+IpEN1pQaGXsKZpScVJJ6yd6hV9UMR1c8rmZ5iSWj9 bMP8CFuxR8V5nk4kPeDQ4Gohb6szZt6MIFfD5U4iu80WPKlM3+uX1GqyH9X8gRxxFo/d LTlAFgPkQU7gRXG9teFV1zW2iWUvsgaKvn3JZ0RQ9FY5WSkWhQDjMh1neVZt6GaRswbT K9Pu58Y7z95tbzj5fSMNn75Zzlvmgxj+3wrXiLaodV+995Q/GGyeZepfrvTw2Q6/KiPW LjtY8UaWt3kEGXSvQIryytytuu9MsgbZjaHNhpa5zb9+kduvE5Me5cX5BB8Pp4Lnc0qH /wxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=hZUCxApR4j0ObPvqrCHsopCtmT5xOXmakkLY1hrC/Hk=; b=qkqIqKy7gVD7ejf29RIo9NHOrZS+6zGixD27Dc0kxvOjzkEKM51Nc/SurXLPaoCbDm ukLOvOF1UdnzWOHSeZPcPsUzAv1ph5xfap5aNUCiE81NBkvWhAN0n9Jx67gip1Ue7feN 2oK9YnTWetVWYyfEkbuE9y06LxwhkOx6RrBvxTSmiye4xByA6HpZpO85npX8MBn2ypm6 XxGzA0ef1Sjn/BuPUZ8MmGGEIDJlH/qAksCyBWWvs3wTmNojT6jLeFSyZipYo+pztUzg 05w8xTyMD7ditmhIPoq7wFFN4x7Qs3bYEjntinMbNH8FfrD4Pchw1i8NaEDScfpg8UN3 l1cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jMvyyhap; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 v2 21/37] tcg/ppc: Split out tcg_out_call_int X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pass in a LK parameter, allowing us to create tail calls. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) -- 2.17.2 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 6e656cd41e..6377e3a829 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1408,7 +1408,7 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *target, int lk) { #ifdef _CALL_AIX /* Look through the descriptor. If the branch is in range, and we @@ -1419,7 +1419,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) if (in_range_b(diff) && toc == (uint32_t)toc) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); - tcg_out_b(s, LK, tgt); + tcg_out_b(s, lk, tgt); } else { /* Fold the low bits of the constant into the addresses below. */ intptr_t arg = (intptr_t)target; @@ -1434,7 +1434,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); + tcg_out32(s, BCCTR | BO_ALWAYS | lk); } #elif defined(_CALL_ELF) && _CALL_ELF == 2 intptr_t diff; @@ -1448,16 +1448,21 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) diff = tcg_pcrel_diff(s, target); if (in_range_b(diff)) { - tcg_out_b(s, LK, target); + tcg_out_b(s, lk, target); } else { tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); + tcg_out32(s, BCCTR | BO_ALWAYS | lk); } #else - tcg_out_b(s, LK, target); + tcg_out_b(s, lk, target); #endif } +static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +{ + tcg_out_call_int(s, target, LK); +} + static const uint32_t qemu_ldx_opc[16] = { [MO_UB] = LBZX, [MO_UW] = LHZX, From patchwork Fri Nov 23 14:45:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151890 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2217891ljp; Fri, 23 Nov 2018 06:56:06 -0800 (PST) X-Google-Smtp-Source: AJdET5fWjUdwqzc2ZTuz3u3CvSpJMYD9egbphllLNy9ah0sEVSduS7QaTnYipxcl1LO+vOpyr+nM X-Received: by 2002:a81:334d:: with SMTP id z74mr15893069ywz.437.1542984966147; Fri, 23 Nov 2018 06:56:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984966; cv=none; d=google.com; s=arc-20160816; b=fQEUzYBCOdy/lEtTsKqr8QSZdMnx7zL98pcb9ZY6FWPPyfFJLqlNtNOyraYSVtC43P 2zwlaMlX4nGQKRm3JuDn0w3mipHG4XDgQwcY12aHJPl3JEaKGxYODxBVzz0/vK5iJKfx 8kqJuBDEkC0i1US+4H7GbVZQd6ronZAInKWs8aNkVYbld5S7JB3TiVfNn6QuKcp9o/PI W7K+3ga7xRZR/Szdt3JeXDTvdMmgzAgri1U12zQLyEcYhlCIFRfo6o9I4tnKIDWweB+U TmDRgGg45qa51Y2W4jIRPThpZa/tlUliLiz8KVSV5/kIaASle3yXfpKMYXsufetHfky8 F1yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=2kjkOBwc36m3JzNrOy40V8NSFyoaC4yO+K9bCMPV9ck=; b=Lfqlga1TK0tA32QJugvjl7BXVWCa3fbTy5o0ld9yDnM20Hk0suK0BOESYzvAJQdhd+ nUy68dsaJZP4qc+2xEu1Jw6xqpeA1pkP2n4YfdPWT0zRzxwDimAgc9xDw87ThahnCGeH S1CZWDIEEMbqMCVt8YSqZlrx20jKfbANEttDLjJTQ49nzy8smR1krBSPWqsX1KeEYKvq WNVqZlYVQ9XPvqlKlrhYQUZJXTorGGVWUvRdCnHnYxJ2Zfzc6HGKgMvBQWeleNf253UZ iVF708gl8/jFmpG8ZP/Lfmf2tftNHJ8WjTul54bxpihV2SOfeoZt/j8VeL7C4I7Ax3xz wyww== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UX5DI7Ds; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q62si5424763ywb.137.2018.11.23.06.56.05 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 06:56:06 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UX5DI7Ds; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52810 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCsH-0001ff-Eu for patch@linaro.org; Fri, 23 Nov 2018 09:56:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj1-0000EA-LF for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCiw-0003Xa-4u for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:30 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41035) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCiu-0003T4-29 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:25 -0500 Received: by mail-wr1-x443.google.com with SMTP id x10so12591707wrs.8 for ; Fri, 23 Nov 2018 06:46:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2kjkOBwc36m3JzNrOy40V8NSFyoaC4yO+K9bCMPV9ck=; b=UX5DI7DshmBua7hZKefFU1DfJOwZYnhQAeuD8RwbqAVvRdPz1n1WaKYJqxb4UPpnrP UrzR2oWanT11/kCauIDhFP+VZX4/mCOLp5WfFmScNNOv+OWdgZDjPOoSYHv9jhCj/urQ 6BM3is+uy44U8rcG0F/kRj8ZdCkStENAvv4Cw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2kjkOBwc36m3JzNrOy40V8NSFyoaC4yO+K9bCMPV9ck=; b=FptfohtlXxvNbcuW++pQo5rq5qOO1Qa31CiPBHx2ZFAo+ovfWjKQWszFvgztSTryhR 28OZJJRHdZQS2i7cMfr+4yinrrsHntXd6WepV/H6eX069EF7Tbsnv5t/eMrQFgLoyCyb XNVk6HbasI5YsE+mm+GCuvZw7oj10Ko7UhmnoLwkTZC+yZbQno3HDbWFUIbZxUNAcpX4 Dw4gY/TjgCuQfmq8wUsO6WYC7ADha/wTo1wGEBb1SDS4rij4agn9VYa3qcQXdrNfPybT vumO1kdykO8yQsO7K+mSRy2M2mNbi26teIvEdH+TPfP4y4sqt7qAjFcDzgpGALu0yBnN 3BWQ== X-Gm-Message-State: AA+aEWZBlMU9puOw6wj8n2cqq94bzPiL5StP9qKCU5xHEm8MVtMI2/KQ WTETsG9mG733wVmYjxVQqoAR/G5U4ByIkg== X-Received: by 2002:adf:f903:: with SMTP id b3mr14726177wrr.82.1542984382198; Fri, 23 Nov 2018 06:46:22 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:43 +0100 Message-Id: <20181123144558.5048-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 v2 22/37] tcg/ppc: Add constraints for R7-R8 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are function call arguments that we will need soon. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) -- 2.17.2 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 6377e3a829..484d90ead2 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -236,10 +236,11 @@ static inline void tcg_out_bc_noaddr(TCGContext *s, int insn) static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType type) { - switch (*ct_str++) { - case 'A': case 'B': case 'C': case 'D': + char c = *ct_str++; + switch (c) { + case 'A': case 'B': case 'C': case 'D': case 'E': case 'F': ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A'); + tcg_regset_set_reg(ct->u.regs, 3 + c - 'A'); break; case 'r': ct->ct |= TCG_CT_REG; From patchwork Fri Nov 23 14:45:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151891 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2218490ljp; Fri, 23 Nov 2018 06:56:38 -0800 (PST) X-Google-Smtp-Source: AJdET5dgFgvhOeN1KBDVHL6TEFE69M1FK5jL2/0j/cUnmSCHwYui6TYOI3intDE19YtrnDcMwcHE X-Received: by 2002:a81:6c51:: with SMTP id h78mr16633697ywc.116.1542984998256; Fri, 23 Nov 2018 06:56:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984998; cv=none; d=google.com; s=arc-20160816; b=FMLckrso+V8v/OmOZn0Fe0OV4A6rTD7PdBCCiGoTSrLWlhghjoKrh7wQ/6bWY7hahd wUIJgvOs12ET6qC1+qVUkT1Xm68EPL0CtTuG4U5ItEeiZVuZf36JXc3ecpiXwG3BHn3F osipGCfm633ycTQFonTky4CRZ/6tFOp90vMC9OtJeMeKqBRBbEzZr31utTeXLdgCvB+v hUAXsHQD9jfsOtNB7QGwXs+r7GihHcOLP0WX2RiRm9cqFICMr156hghOqK/slZmoglr7 fTaWkqBKpNJlcX136huoCPwQRO1wsIAlQrw6WTMBMA/IlxmknI8y1RgSpGu/4k+/QvpI yNtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=vcnioQXCG048QsIG8yjmBWpdApnTjYfBp7eDl5pVV3c=; b=o6nSP2f8AKRBISNCscVPi7id/SeVzzNwqeI2yOZkPfzDNt02YqYJEcYzqEJNWUb5Cz 6FqZzoHkaX1ysfI+4JYSv7txmFCkq9zijyVwIkbYLjA6hgtIMO6NiLAIkHX3Yr8PZuY2 6A9zhCZC9CmZEPXkYtii+YY/TRyeyGjDlGu2SoVl5TTmeKuIs/fYnXDty3Sd1HZIq5BZ 6m/k0jiAcoWy/RJb37kqk/+wwTu1okDer/k0KNXJHeRWxDg09T4J0MBZp+hYFOo2iR5L e8aceXtgCwYt/e8cUM3J3T0jfizqN7xbHN+9Ykytd5RI088r8YLA/Q0EQWxhS7wMtwwA G21g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BFdz5YCx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 23/37] tcg/ppc: Change TCG_TARGET_CALL_ALIGN_ARGS to bool X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cleaner not to treat this as #ifdef. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) -- 2.17.2 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 484d90ead2..f7c33f3b7f 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -30,6 +30,8 @@ #endif #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ALIGN_ARGS 1 +#else +# define TCG_TARGET_CALL_ALIGN_ARGS 0 #endif /* For some memory operations, we need a scratch that isn't R0. For the AIX @@ -1675,9 +1677,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) lo = lb->addrlo_reg; hi = lb->addrhi_reg; if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |= 1; -#endif + arg |= TCG_TARGET_CALL_ALIGN_ARGS; tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); } else { @@ -1720,9 +1720,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) lo = lb->addrlo_reg; hi = lb->addrhi_reg; if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |= 1; -#endif + arg |= TCG_TARGET_CALL_ALIGN_ARGS; tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); } else { @@ -1736,9 +1734,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) if (TCG_TARGET_REG_BITS == 32) { switch (s_bits) { case MO_64: -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |= 1; -#endif + arg |= TCG_TARGET_CALL_ALIGN_ARGS; tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); /* FALLTHRU */ case MO_32: From patchwork Fri Nov 23 14:45:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151900 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2231330ljp; Fri, 23 Nov 2018 07:05:57 -0800 (PST) X-Google-Smtp-Source: AJdET5cmB8emhih5Wg8UChmNQGxamJlkWBweQLVKTagltzmiOlCydINco0u3jiHr/vuAloCs1/4J X-Received: by 2002:a67:2f81:: with SMTP id v123mr6871122vsv.12.1542985556940; Fri, 23 Nov 2018 07:05:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985556; cv=none; d=google.com; s=arc-20160816; b=tVSLLI+vJW7M9e+ewf62wXLUK9G1L+pwJTDy5B4ETsLAanbLuKEE5I73dfEtlJZHGe 2OcYccBmyxw26Vu/rcCrLn38NrfX7S7B+RTzkSFQdHr6qqgDoPHVg6JqszZH/jasKb4f nzxMbErvA+kRbKe1DFsO7l28hG/FhpT+o2w82ytY66qXPrLeCzcV4I/UJYb5nXXVW+mg 1LP1q7MAAEza1CQ8gY0Y7lvjsT/vcJfNciySeHSAU9nwMmaj9HfDBJbtAMA+FaBs90oe i/QoW87o6mS4qvJwAauB8YDqoIqhYERxWcHjJhpWheRN/m6Kq0yx0nYew163JUkVzEgT ckHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=vw53NxlkIM0aRxCvl+l6ZZoxsk+nWK7e+ZpN0X1cy0Y=; b=yv6O08NeE+tolcCSedRkDPRYUbPvYyVYdK6TyZ4HysyvMT8Y/8ZuRSqzD9ulAtdgQm Ojf8ZIBC0mZWgBU1FD+/p6ojez08JOyQJKADKycPA5VI36MOASGGPHtZr/AXVstAtma8 0xpOw4CETN2hfXmGzJQtYa6vQjVLcmDdjwJIj/TqBcxkhUtUKrI9MmsoVKiMtSxIDOo/ SOzvcRdoAMR2KwSJjKDN2AQ8FjTIi0SC1KE8Ox7yky5P9VPxFSQOET4z9K8sUvCc+J6d 2tmAMX0ftZyRxEaYN7a4qWZDt1ocnDrmi9MZO66bcrqS8R3Xo+q8JKqEEuY3G88Smvnf 4Jng== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Sp4SHAVv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 24/37] tcg/ppc: Force qemu_ld/st arguments into fixed registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is an incremental step toward moving the qemu_ld/st code sequence out of line. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 151 ++++++++++++++++++++++++++++----------- 1 file changed, 111 insertions(+), 40 deletions(-) -- 2.17.2 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index f7c33f3b7f..c706b2cf53 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -248,25 +248,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, ct->ct |= TCG_CT_REG; ct->u.regs = 0xffffffff; break; - case 'L': /* qemu_ld constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); -#endif - break; - case 'S': /* qemu_st constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); -#endif - break; case 'I': ct->ct |= TCG_CT_CONST_S16; break; @@ -1759,6 +1740,21 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) tcg_out_b(s, 0, lb->raddr); } + +static TCGReg softmmu_args_2(TCGReg reg, TCGReg *lo, TCGReg *hi) +{ +#ifdef HOST_WORDS_BIGENDIAN + static bool is_be = true; +#else + static bool is_be = false; +#endif + + assert(TCG_TARGET_REG_BITS == 32); + reg |= TCG_TARGET_CALL_ALIGN_ARGS; + *(is_be ? hi : lo) = reg; + *(is_be ? lo : hi) = reg + 1; + return reg + 2; +} #endif /* SOFTMMU */ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) @@ -1782,9 +1778,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) #ifdef CONFIG_SOFTMMU mem_index = get_mmuidx(oi); - rbase = TCG_REG_R3; + rbase = TCG_REG_R9; addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true, - rbase, TCG_REG_R4); + rbase, TCG_REG_R10); /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr = s->code_ptr; @@ -1858,9 +1854,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #ifdef CONFIG_SOFTMMU mem_index = get_mmuidx(oi); - rbase = TCG_REG_R3; + rbase = TCG_REG_R9; addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false, - rbase, TCG_REG_R4); + rbase, TCG_REG_R10); /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr = s->code_ptr; @@ -2627,13 +2623,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } }; static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } }; static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } }; @@ -2644,10 +2635,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) = { .args_ct_str = { "r", "rI", "rT" } }; static const TCGTargetOpDef r_r_rZW = { .args_ct_str = { "r", "r", "rZW" } }; - static const TCGTargetOpDef L_L_L_L - = { .args_ct_str = { "L", "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S_S - = { .args_ct_str = { "S", "S", "S", "S" } }; static const TCGTargetOpDef movc = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } }; static const TCGTargetOpDef dep @@ -2660,6 +2647,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } }; static const TCGTargetOpDef sub2 = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } }; +#ifdef CONFIG_SOFTMMU + static const char * const arg_letter[] = { + NULL, NULL, NULL, "A", "B", "C", "D", "E", "F", NULL, NULL + }; + TCGReg hi, lo, arg; +#else + static const TCGTargetOpDef r_r_r_r + = { .args_ct_str = { "r", "r", "r", "r" } }; +#endif switch (op) { case INDEX_op_goto_ptr: @@ -2782,18 +2778,93 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sub2_i32: return &sub2; +#ifdef CONFIG_SOFTMMU case INDEX_op_qemu_ld_i32: - return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &r_L : &r_L_L); + { + static TCGTargetOpDef ld32; + ld32.args_ct_str[0] = arg_letter[tcg_target_call_oarg_regs[0]]; + if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { + ld32.args_ct_str[1] = arg_letter[tcg_target_call_iarg_regs[1]]; + } else { + arg = tcg_target_call_iarg_regs[1]; + arg = softmmu_args_2(arg, &lo, &hi); + ld32.args_ct_str[1] = arg_letter[lo]; + ld32.args_ct_str[2] = arg_letter[hi]; + } + return &ld32; + } case INDEX_op_qemu_st_i32: - return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &S_S : &S_S_S); + { + static TCGTargetOpDef st32; + arg = tcg_target_call_iarg_regs[1]; + if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { + st32.args_ct_str[0] = arg_letter[arg + 1]; + st32.args_ct_str[1] = arg_letter[arg]; + } else { + arg = softmmu_args_2(arg, &lo, &hi); + st32.args_ct_str[0] = arg_letter[arg]; + st32.args_ct_str[1] = arg_letter[lo]; + st32.args_ct_str[2] = arg_letter[hi]; + } + return &st32; + } case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L); + { + static TCGTargetOpDef ld64; + if (TCG_TARGET_REG_BITS == 64) { + ld64.args_ct_str[0] = arg_letter[tcg_target_call_oarg_regs[0]]; + ld64.args_ct_str[1] = arg_letter[tcg_target_call_iarg_regs[1]]; + } else { + arg = tcg_target_call_oarg_regs[1]; + arg = softmmu_args_2(arg, &lo, &hi); + ld64.args_ct_str[0] = arg_letter[lo]; + ld64.args_ct_str[1] = arg_letter[hi]; + arg = tcg_target_call_iarg_regs[1]; + if (TARGET_LONG_BITS == 32) { + ld64.args_ct_str[2] = arg_letter[arg]; + } else { + arg = softmmu_args_2(arg, &lo, &hi); + ld64.args_ct_str[2] = arg_letter[lo]; + ld64.args_ct_str[3] = arg_letter[hi]; + } + } + return &ld64; + } case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &S_S - : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S); + { + static TCGTargetOpDef st64; + if (TCG_TARGET_REG_BITS == 64) { + st64.args_ct_str[1] = arg_letter[tcg_target_call_iarg_regs[1]]; + st64.args_ct_str[0] = arg_letter[tcg_target_call_iarg_regs[2]]; + } else { + arg = tcg_target_call_iarg_regs[1]; + if (TARGET_LONG_BITS == 32) { + st64.args_ct_str[2] = arg_letter[arg++]; + } else { + arg = softmmu_args_2(arg, &lo, &hi); + st64.args_ct_str[2] = arg_letter[lo]; + st64.args_ct_str[3] = arg_letter[hi]; + } + arg = softmmu_args_2(arg, &lo, &hi); + st64.args_ct_str[0] = arg_letter[lo]; + st64.args_ct_str[1] = arg_letter[hi]; + } + return &st64; + } +#else + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r : &r_r_r; + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: + if (TCG_TARGET_REG_BITS == 64) { + return &r_r; + } else if (TARGET_LONG_BITS == 32) { + return &r_r_r; + } else { + return &r_r_r_r; + } +#endif default: return NULL; From patchwork Fri Nov 23 14:45:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151894 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2222425ljp; Fri, 23 Nov 2018 07:00:13 -0800 (PST) X-Google-Smtp-Source: AJdET5f3/aa8/X7aAcwmM2+5m2lN1kxQAQ0M/ESyQEzZS6EsVmJEVnJDEhiTVTb4uFTaEH2tLSpr X-Received: by 2002:a81:cb0d:: with SMTP id q13-v6mr16644295ywi.298.1542985212777; Fri, 23 Nov 2018 07:00:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985212; cv=none; d=google.com; s=arc-20160816; b=dKVxi66/7y+91qitL2t6khfWcKyhXGjPoGPEwQ55A0gSJKDOTTZepOpaPJf1zhSOZS mSCPYzWTFmgHVBqbm9AkdT6Kte5mnZfX6A85jUUNdGIqA/pq5mwGjvSLeHG9zI3keWVF YBlda169ec+2e3o/YeRhFP/wcWQEQQCNL2MjLDrPTZ1c014aBu72SOtsKpwRtBhs2E4B xk9L1yE3d1GCUVg4kh/2auo4GS5Sxdul5n47T+8usrtkx4Goi0wdE2hNJ3oJgoyfHvVM 6MGrvoTb2umYKOmwm+SfO3Ne/smVYpElFiYlbkVLfjc7tRHLwFWlOpKpEFoGVdPeijuR gbPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4SK9gU8naH9sM9NW9c9OPn3r+aLaMwI873v6N6J6XYs=; b=ZMMgnoz62wPN9A//ICYKQoVPPjFKk7xxZYc2OYP0C5cOj4UT28IB4hDJzKoB4kIlzl mZci4ASrypInTH+sRwLPzwIXaI7s8g7yYe/yZ//FRASk6+D4IQtckmOqYP1Cf2wgkd9T i0QqbqV3zlmPEcyOY+l9fUP0/cGJfSrTusxMkEBNBtjS45yV8ILt7W4GrvxTGDci54eA VFWvR5LUb/K3h4JflwTxg27Q7BXr/NkogHxjNmSCsXNizG4DF+S4zKnQMILSAHJsJQbE vGTM1pl2XjCAv3zKOuYwF14/IO39tvpHsdtJKIMsOjjh8DqNxblhzoaBp49EAdbIT6Vy jrog== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bXr8TcCx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 v2 25/37] tcg/ppc: Use TCG_TARGET_NEED_LDST_OOL_LABELS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 326 +++++++++++++++++---------------------- 2 files changed, 141 insertions(+), 187 deletions(-) -- 2.17.2 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be52ad1d2e..bbc49bb1be 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -130,7 +130,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) #ifdef CONFIG_SOFTMMU -#define TCG_TARGET_NEED_LDST_LABELS +#define TCG_TARGET_NEED_LDST_OOL_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index c706b2cf53..fed7f5fe6e 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1476,7 +1476,7 @@ static const uint32_t qemu_exts_opc[4] = { }; #if defined (CONFIG_SOFTMMU) -#include "tcg-ldst.inc.c" +#include "tcg-ldst-ool.inc.c" /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1489,6 +1489,14 @@ static void * const qemu_ld_helpers[16] = { [MO_BEUW] = helper_be_lduw_mmu, [MO_BEUL] = helper_be_ldul_mmu, [MO_BEQ] = helper_be_ldq_mmu, + + [MO_SB] = helper_ret_ldsb_mmu, + [MO_LESW] = helper_le_ldsw_mmu, + [MO_BESW] = helper_be_ldsw_mmu, +#if TCG_TARGET_REG_BITS == 64 + [MO_LESL] = helper_le_ldsl_mmu, + [MO_BESL] = helper_be_ldsl_mmu, +#endif }; /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, @@ -1526,9 +1534,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS == 64) { if (TARGET_LONG_BITS == 32) { - /* Zero-extend the address into a place helpful for further use. */ - tcg_out_ext32u(s, t1, addrlo); - addrlo = t1; + /* Zero-extend the address now. */ + tcg_out_ext32u(s, addrlo, addrlo); } else { tcg_out_rld(s, RLDICL, t0, addrlo, 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS); @@ -1625,122 +1632,6 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, return addrlo; } -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGReg datalo_reg, TCGReg datahi_reg, - TCGReg addrlo_reg, TCGReg addrhi_reg, - tcg_insn_unit *raddr, tcg_insn_unit *lptr) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->datalo_reg = datalo_reg; - label->datahi_reg = datahi_reg; - label->addrlo_reg = addrlo_reg; - label->addrhi_reg = addrhi_reg; - label->raddr = raddr; - label->label_ptr[0] = lptr; -} - -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi = lb->oi; - TCGMemOp opc = get_memop(oi); - TCGReg hi, lo, arg = TCG_REG_R3; - - reloc_pc14(lb->label_ptr[0], s->code_ptr); - - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo = lb->addrlo_reg; - hi = lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |= TCG_TARGET_CALL_ALIGN_ARGS; - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - lo = lb->datalo_reg; - hi = lb->datahi_reg; - if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); - tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); - } else if (opc & MO_SIGN) { - uint32_t insn = qemu_exts_opc[opc & MO_SIZE]; - tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3)); - } else { - tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3); - } - - tcg_out_b(s, 0, lb->raddr); -} - -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi = lb->oi; - TCGMemOp opc = get_memop(oi); - TCGMemOp s_bits = opc & MO_SIZE; - TCGReg hi, lo, arg = TCG_REG_R3; - - reloc_pc14(lb->label_ptr[0], s->code_ptr); - - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo = lb->addrlo_reg; - hi = lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |= TCG_TARGET_CALL_ALIGN_ARGS; - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - lo = lb->datalo_reg; - hi = lb->datahi_reg; - if (TCG_TARGET_REG_BITS == 32) { - switch (s_bits) { - case MO_64: - arg |= TCG_TARGET_CALL_ALIGN_ARGS; - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - /* FALLTHRU */ - case MO_32: - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - break; - default: - tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31); - break; - } - } else { - if (s_bits == MO_64) { - tcg_out_mov(s, TCG_TYPE_I64, arg++, lo); - } else { - tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits)); - } - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - tcg_out_b(s, 0, lb->raddr); -} - static TCGReg softmmu_args_2(TCGReg reg, TCGReg *lo, TCGReg *hi) { #ifdef HOST_WORDS_BIGENDIAN @@ -1757,44 +1648,10 @@ static TCGReg softmmu_args_2(TCGReg reg, TCGReg *lo, TCGReg *hi) } #endif /* SOFTMMU */ -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg rbase, TCGMemOp opc) { - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - TCGMemOpIdx oi; - TCGMemOp opc, s_bits; -#ifdef CONFIG_SOFTMMU - int mem_index; - tcg_insn_unit *label_ptr; -#endif - - datalo = *args++; - datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); - addrlo = *args++; - addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - s_bits = opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index = get_mmuidx(oi); - rbase = TCG_REG_R9; - addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true, - rbase, TCG_REG_R10); - - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr = s->code_ptr; - tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - -#else /* !CONFIG_SOFTMMU */ - rbase = guest_base ? TCG_GUEST_BASE_REG : 0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - addrlo = TCG_REG_TMP1; - } -#endif - - if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { + if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { if (opc & MO_BSWAP) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); @@ -1811,7 +1668,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); } } else { - uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; + uint32_t insn = qemu_ldx_opc[opc & (MO_SSIZE | MO_BSWAP)]; if (!HAVE_ISA_2_06 && insn == LDBRX) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); @@ -1822,55 +1679,45 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) } else { insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); - insn = qemu_exts_opc[s_bits]; + insn = qemu_exts_opc[opc & MO_SIZE]; tcg_out32(s, insn | RA(datalo) | RS(datalo)); } } - -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#endif } -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { - TCGReg datalo, datahi, addrlo, rbase; + TCGReg datalo __attribute__((unused)); + TCGReg datahi __attribute__((unused)); + TCGReg addrlo __attribute__((unused)); TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc, s_bits; -#ifdef CONFIG_SOFTMMU - int mem_index; - tcg_insn_unit *label_ptr; -#endif datalo = *args++; datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); addrlo = *args++; addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); oi = *args++; - opc = get_memop(oi); - s_bits = opc & MO_SIZE; #ifdef CONFIG_SOFTMMU - mem_index = get_mmuidx(oi); - rbase = TCG_REG_R9; - addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false, - rbase, TCG_REG_R10); + add_ldst_ool_label(s, true, is_64, oi, R_PPC_REL24, 0); + tcg_out_b_noaddr(s, B | LK); +#else + TCGMemOp opc = get_memop(oi); + TCGReg rbase = guest_base ? TCG_GUEST_BASE_REG : 0; - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr = s->code_ptr; - tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - -#else /* !CONFIG_SOFTMMU */ - rbase = guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); addrlo = TCG_REG_TMP1; } + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, rbase, opc); #endif +} - if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg rbase, TCGMemOp opc) +{ + if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { if (opc & MO_BSWAP) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); @@ -1894,10 +1741,34 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) tcg_out32(s, insn | SAB(datalo, rbase, addrlo)); } } +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg datalo __attribute__((unused)); + TCGReg datahi __attribute__((unused)); + TCGReg addrlo __attribute__((unused)); + TCGReg addrhi __attribute__((unused)); + TCGMemOpIdx oi; + + datalo = *args++; + datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addrlo = *args++; + addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_ldst_ool_label(s, false, is_64, oi, R_PPC_REL24, 0); + tcg_out_b_noaddr(s, B | LK); +#else + TCGMemOp opc = get_memop(oi); + TCGReg rbase = guest_base ? TCG_GUEST_BASE_REG : 0; + + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); + addrlo = TCG_REG_TMP1; + } + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, rbase, opc); #endif } @@ -1909,6 +1780,89 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) } } +#ifdef CONFIG_SOFTMMU +static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, + bool is_64, TCGMemOpIdx oi) +{ + TCGMemOp opc = get_memop(oi); + int mem_index = get_mmuidx(oi); + TCGReg addrlo, addrhi, datalo, datahi, rbase, nextarg; + tcg_insn_unit *thunk, *label; + + /* Since we're amortizing the cost, align the thunk. */ + thunk = QEMU_ALIGN_PTR_UP(s->code_ptr, 16); + if (thunk != s->code_ptr) { + tcg_out_nop_fill(s->code_ptr, thunk - s->code_ptr); + s->code_ptr = thunk; + } + + /* Discover where the inputs are held. */ + if (TCG_TARGET_REG_BITS == 64) { + addrhi = addrlo = tcg_target_call_iarg_regs[1]; + if (is_ld) { + datahi = datalo = tcg_target_call_oarg_regs[0]; + nextarg = addrlo + 1; + } else { + datahi = datalo = addrlo + 1; + nextarg = addrlo + 2; + } + } else { + nextarg = tcg_target_call_iarg_regs[1]; + if (TARGET_LONG_BITS == 64) { + nextarg = softmmu_args_2(nextarg, &addrlo, &addrhi); + } else { + addrhi = addrlo = nextarg++; + } + if (is_ld) { + TCGReg arg = tcg_target_call_oarg_regs[0]; + if (is_64) { + softmmu_args_2(arg, &datalo, &datahi); + } else { + addrhi = addrlo = arg; + } + } else { + if (is_64) { + nextarg = softmmu_args_2(nextarg, &datalo, &datahi); + } else { + addrhi = addrlo = nextarg++; + } + } + } + + rbase = TCG_REG_R9; + tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, + is_ld, rbase, TCG_REG_R10); + + label = s->code_ptr; + tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE); + + /* TLB Hit */ + if (is_ld) { + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, rbase, opc); + } else { + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, rbase, opc); + } + tcg_out32(s, BCLR | BO_ALWAYS); + + /* TLB Miss */ + reloc_pc14(label, s->code_ptr); + + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + /* The addrhi, addrlo, datahi, datalo registers are already in place. */ + tcg_out_movi(s, TCG_TYPE_I32, nextarg++, oi); + tcg_out32(s, MFSPR | RT(nextarg) | LR); + + /* Tail call to the helper. */ + if (is_ld) { + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], 0); + } else { + tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], 0); + } + + return thunk; +} +#endif + /* Parameters for function call generation, used in tcg.c. */ #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_EXTEND_ARGS 1 From patchwork Fri Nov 23 14:45:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151907 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2239194ljp; Fri, 23 Nov 2018 07:11:17 -0800 (PST) X-Google-Smtp-Source: AFSGD/Uhv3e+yfsF+n3IxzGUSPyS7kf8cRIRPXSqhBLHbG5TlvsKqWqDURoO8M5W4NOKMrPrSi2i X-Received: by 2002:a25:5e83:: with SMTP id s125-v6mr13498399ybb.368.1542985877095; Fri, 23 Nov 2018 07:11:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985877; cv=none; d=google.com; s=arc-20160816; b=Dp1Jc6YodccEOMAbpJvWAMqtqIvQiq1zPaiE3QfD1EopAJnmH4JGyn3eDRFVhFTMsj Vso5RpNx5//VjOmMzN1oexYb3Ckr/qk2x/b2PC4Lj0tDhIfo7FytBOpqmyGQLxpj5Iq5 A3hY1f8mN0qieMJYPgEDCJpR+Lr/fVAN2mxmRKRhRwyvktQWMmVmI8LFQRukf8TwFkAC uAoEdxN24BiUZtAOigbHhDoM6lqRGl0YZOUazRd60acI/ANioCMZgsyEBgI4A6xyb46f KT2fzQH/PZLNstHiwVKDUURR1si0OkwNkwFNr7IqNCnP8YTB0KF9+xBlfrk3n5W/vy62 qVAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ZdFhnUufyrFc19z7ViZt8Wb0ZHqiPUdjffxN+QTai+8=; b=edwgF71ncNsnvEI6obzXYVfRDYjnbyBZcPhu6ff/AS48jEbiTemHoZ+0/GHTknCoIr WKJxRvfTTZk5MC/b9UbsYyDY0CpnxpsTGhgU6KnRwd5DxaPYyHYrp4TQvfipAtTP+B6K gDfZoC8xxHxN05vn7o0Pz/Gb77De4P9hZuDSWfD51Hv8o4ELJnxsaccZCvskCrYBxLjI q9iRkVsdXtcRA57ItSi4EGL7YIcFMH+bjdC/kvS4CinSB4NEyxEYlI6vcl/btvGN7Y3e ffloQB5S/o7VwVatjZ1CGLgYt8YR1p89/KrKUaU8/XEPfz2QmkmxwpjdocyQX2urtFuY elyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UgW6PcqB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 26/37] tcg: Clean up generic bswap32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Based on the only current user, Sparc: New code uses 1 constant that takes 2 insns to create, plus 8. Old code used 2 constants that took 2 insns to create, plus 9. The result is a new total of 10 vs an old total of 13. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 54 ++++++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 27 deletions(-) -- 2.17.2 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7a8015c5a9..a956499e46 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1012,22 +1012,22 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) if (TCG_TARGET_HAS_bswap32_i32) { tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); } else { - TCGv_i32 t0, t1; - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_const_i32(0x00ff00ff); - tcg_gen_shli_i32(t0, arg, 24); + /* arg = abcd */ + tcg_gen_shri_i32(t0, arg, 8); /* t0 = .abc */ + tcg_gen_and_i32(t1, arg, t2); /* t1 = .b.d */ + tcg_gen_and_i32(t0, t0, t2); /* t0 = .a.c */ + tcg_temp_free_i32(t2); + tcg_gen_shli_i32(t1, t1, 8); /* t1 = b.d. */ + tcg_gen_or_i32(ret, t0, t1); /* ret = badc */ - tcg_gen_andi_i32(t1, arg, 0x0000ff00); - tcg_gen_shli_i32(t1, t1, 8); - tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t0, ret, 16); /* t0 = ..ba */ + tcg_gen_shli_i32(t1, ret, 16); /* t1 = dc.. */ + tcg_gen_or_i32(ret, t0, t1); /* ret = dcba */ - tcg_gen_shri_i32(t1, arg, 8); - tcg_gen_andi_i32(t1, t1, 0x0000ff00); - tcg_gen_or_i32(t0, t0, t1); - - tcg_gen_shri_i32(t1, arg, 24); - tcg_gen_or_i32(ret, t0, t1); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); } @@ -1638,23 +1638,23 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) } else if (TCG_TARGET_HAS_bswap32_i64) { tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); } else { - TCGv_i64 t0, t1; - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_const_i64(0x00ff00ff); - tcg_gen_shli_i64(t0, arg, 24); - tcg_gen_ext32u_i64(t0, t0); + /* arg = ....abcd */ + tcg_gen_shri_i64(t0, arg, 8); /* t0 = .....abc */ + tcg_gen_and_i64(t1, arg, t2); /* t1 = .....b.d */ + tcg_gen_and_i64(t0, t0, t2); /* t0 = .....a.c */ + tcg_temp_free_i64(t2); + tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. */ + tcg_gen_or_i64(ret, t0, t1); /* ret = ....badc */ - tcg_gen_andi_i64(t1, arg, 0x0000ff00); - tcg_gen_shli_i64(t1, t1, 8); - tcg_gen_or_i64(t0, t0, t1); + tcg_gen_shli_i64(t1, ret, 48); /* t1 = dc...... */ + tcg_gen_shri_i64(t0, ret, 16); /* t0 = ......ba */ + tcg_gen_shri_i64(t1, ret, 32); /* t1 = ....dc.. */ + tcg_gen_or_i64(ret, t0, t1); /* ret = ....dcba */ - tcg_gen_shri_i64(t1, arg, 8); - tcg_gen_andi_i64(t1, t1, 0x0000ff00); - tcg_gen_or_i64(t0, t0, t1); - - tcg_gen_shri_i64(t1, arg, 24); - tcg_gen_or_i64(ret, t0, t1); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); } From patchwork Fri Nov 23 14:45:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151899 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2230513ljp; Fri, 23 Nov 2018 07:05:23 -0800 (PST) X-Google-Smtp-Source: AJdET5fDf7bq3XHzYg6Yl2cY/dI/wPU3xEmWvrwBZGrrGEmu1WumOaOkQhG5LQC5riVJZShgcNUg X-Received: by 2002:a81:a1c2:: with SMTP id y185mr16283218ywg.323.1542985523110; Fri, 23 Nov 2018 07:05:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985523; cv=none; d=google.com; s=arc-20160816; b=H+a+KEUUTpvzBArQeP8VGUEasqbw00SoNm3nu8UBQugnGkMyXAAtCis5kYz3M97xOB ZXCpWI4J9AJ86+bhQu1oE+xMmpUiBDU4mhnJDuqFAj7iSPqDiDzWjxtrxngn+Q997Uq/ 6dueJ/JMqvXSCEjpMIxKGmyFQkvssowfX73Lryb5ZdmDbq3dH1atrdymS0HlGSW3mxpk InAKutKZ6IsSLMwGy8hloxVGrUAqTItTP1kczJVpQzPNbv8YxpukhHxptzx8h89tyGyk pehqkneEWLSm840nFnzI70d7oNMUsuOSfrfSBeMQLnrpNEJO6tS6rGQf2XnIrt4xJPSJ LKkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=U/S7zmMlyfjLiA6mFcj5+nW10ojCNetN9JvrDZkZZc8=; b=v2XZMJLTwJL2xZP/F3YBgPq+MggWle9LJd/MNVoP4NotJDoG012lN4/L4hhV2Vgfua 3P3WhTp2ZJjJhRLZQ0C9HZXtv+EmXHxIfG34ViCXAAA7MxbrFESSm5laRwSmHHnIYlKQ OCS4IRILse99hDDHFOMbrzcHVIhTQmy8J7rTGp6+3BfTPV9ZPv5C0FUgOBLd8oPhkNIU XcSqVFKQWspmcCrPr66DCv5lxCrFXp6EiUTWJkb/zyW6IP6RZ6WrAVA/vCuA7AX7IzT5 PTKlxe2OfaP9bKGlLHyGJdRfApgs3l7ib8X3EvAT61ujUPs77s+0YQrR4sgwJmxoG6N5 c+iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eVx5hERW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s4-v6si10351405ywd.283.2018.11.23.07.05.22 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 07:05:23 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eVx5hERW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52863 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD1G-0001M7-95 for patch@linaro.org; Fri, 23 Nov 2018 10:05:22 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44145) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj1-0000EH-Mb for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCiz-0003da-OJ for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:31 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:44384) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCiy-0003ZO-0I for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:29 -0500 Received: by mail-wr1-x444.google.com with SMTP id z5so8281528wrt.11 for ; Fri, 23 Nov 2018 06:46:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U/S7zmMlyfjLiA6mFcj5+nW10ojCNetN9JvrDZkZZc8=; b=eVx5hERWeDN6cgl78AOSxjgjzuKL148atgXH5RpR62+L73c69Z2Zso0t9eoEJVHFph tSSq00gMokiBDw12PVrHktM4GMWvMdxebx5fe2YIjKB8nCeZ/CvtxcyTIxwN99TXhofj zmPoZzIa1YIBcxZOPMMXeo4SyPH30RUhU9pYY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U/S7zmMlyfjLiA6mFcj5+nW10ojCNetN9JvrDZkZZc8=; b=OsYpC/3hG7GwMyfCxHmQi0YGF82B5iQNI3UP3DUw5Wqt451O//oZ4axC9OKq1WEYnZ 1xTCN1gc5m8iWU/BzUMfkYgvFz8BqzsmnNCYvpN9vLyQ4pXYvAb8fzomvjYsfLD42aZ6 bJ6UGNEusexIRkLcQPIkEudkPzI1UNVWTdgu2NMEskZu3cE2JDTi/6nqCTd/BcyvTOXf MQrw3ZLsDx/j6NAvrpDADcg4dnj/oPbWkRhxvjBhnRAm5VeMeA0EtyyFOzNuD+2Ss3Rl RmpOOs/pDIf6yfxiq9gyO3Jd1bbS0jHY2lhuYpodD2V1hwJzf2XNXKRUIa8kKqkc5pv/ ly9g== X-Gm-Message-State: AA+aEWbPSxSmfjEEhJDvgLKZEVEjaE2j6qLkKuX+g5qxI+b62tAQMgJn 8kK4lxiYuUun9CipwOpKeiv0/2HSV6Zj4g== X-Received: by 2002:adf:fa91:: with SMTP id h17mr15253153wrr.320.1542984386577; Fri, 23 Nov 2018 06:46:26 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:48 +0100 Message-Id: <20181123144558.5048-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 27/37] tcg: Clean up generic bswap64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Based on the only current user, Sparc: New code uses 2 constants that take 2 insns to load from constant pool, plus 13. Old code used 6 constants that took 1 or 2 insns to create, plus 21. The result is a new total of 17 vs an old total of 29. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 43 ++++++++++++++++++------------------------- 1 file changed, 18 insertions(+), 25 deletions(-) -- 2.17.2 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a956499e46..887b371a81 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1678,37 +1678,30 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) } else { TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); - tcg_gen_shli_i64(t0, arg, 56); + /* arg = abcdefgh */ + tcg_gen_movi_i64(t2, 0x00ff00ff00ff00ffull); + tcg_gen_shri_i64(t0, arg, 8); /* t0 = .abcdefg */ + tcg_gen_and_i64(t1, arg, t2); /* t1 = .b.d.f.h */ + tcg_gen_and_i64(t0, t0, t2); /* t0 = .a.c.e.g */ + tcg_gen_shli_i64(t1, t1, 8); /* t1 = b.d.f.h. */ + tcg_gen_or_i64(ret, t0, t1); /* ret = badcfehg */ - tcg_gen_andi_i64(t1, arg, 0x0000ff00); - tcg_gen_shli_i64(t1, t1, 40); - tcg_gen_or_i64(t0, t0, t1); + tcg_gen_movi_i64(t2, 0x0000ffff0000ffffull); + tcg_gen_shri_i64(t0, ret, 16); /* t0 = ..badcfe */ + tcg_gen_and_i64(t1, ret, t2); /* t1 = ..dc..hg */ + tcg_gen_and_i64(t0, t0, t2); /* t0 = ..ba..fe */ + tcg_gen_shli_i64(t1, t1, 16); /* t1 = dc..hg.. */ + tcg_gen_or_i64(ret, t0, t1); /* ret = dcbahgfe */ - tcg_gen_andi_i64(t1, arg, 0x00ff0000); - tcg_gen_shli_i64(t1, t1, 24); - tcg_gen_or_i64(t0, t0, t1); + tcg_gen_shri_i64(t0, ret, 32); /* t0 = ....dcba */ + tcg_gen_shli_i64(t1, ret, 32); /* t1 = hgfe.... */ + tcg_gen_or_i64(ret, t0, t1); /* ret = hgfedcba */ - tcg_gen_andi_i64(t1, arg, 0xff000000); - tcg_gen_shli_i64(t1, t1, 8); - tcg_gen_or_i64(t0, t0, t1); - - tcg_gen_shri_i64(t1, arg, 8); - tcg_gen_andi_i64(t1, t1, 0xff000000); - tcg_gen_or_i64(t0, t0, t1); - - tcg_gen_shri_i64(t1, arg, 24); - tcg_gen_andi_i64(t1, t1, 0x00ff0000); - tcg_gen_or_i64(t0, t0, t1); - - tcg_gen_shri_i64(t1, arg, 40); - tcg_gen_andi_i64(t1, t1, 0x0000ff00); - tcg_gen_or_i64(t0, t0, t1); - - tcg_gen_shri_i64(t1, arg, 56); - tcg_gen_or_i64(ret, t0, t1); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); } } From patchwork Fri Nov 23 14:45:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151901 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2231734ljp; Fri, 23 Nov 2018 07:06:13 -0800 (PST) X-Google-Smtp-Source: AFSGD/Upb+mYhR6r6xOO1JC1VqM7q5nQM+13mqnjxEOYua60W2n7QEO0VOIjgGpuPLv+ON/JApED X-Received: by 2002:ab0:6446:: with SMTP id j6mr6602640uap.2.1542985573395; Fri, 23 Nov 2018 07:06:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985573; cv=none; d=google.com; s=arc-20160816; b=BLhM9fT03s/ZWrAAmYT2770zuRCOOch2vVsm94cyvHOnyQ9GAYwKAbgESEpeCM7fOk JfgOBCrLYenuMMbJuRMd1wrOm6ypkl3AGj2axcsa4itjPYsJXY38n2LIxXQCIvaQZ85C uEs9OZ1Ke+VjPnrgOl4PfcfMlWOOkFuAPfVaokQP6bF7u62xK3y8+zwB58BSGnPdq7hr aeVyVnZP3qEFp0SsFzG7MyaOY8PQJtP9GZBnHXEOI0Y3W/8H1W/FLL5u4xjNSeVJvWNh YXV7oB6EzE6DaCbImy63rkew01SmeNp5kOJpNU+XiCJB06cOAp71833PI04oXOUcCMjw 7QcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=tusyFviTXg3Z07DzPNMpcS9w3/27t1wRBGHj82A/Eoc=; b=TxncIIBdbWKhXydRl4XrQICyvyAkpDJhIzIjMCaevywXREG/kUJeIWURweEtfnqdbz 0HX4fZLix9UuVhGWeBSxnDaPNVYt6xM3swjJSiK/j0Efng4eWvAzfkJAKN0ybiO1IW1w Xiiu8nMNgcr9GMYmU4sokPlUm9KTckVabpGAhdao329yKF3b6VkaGQsMWD0qLNpIsh6+ 6xK//bVP6f/HAeGrGpNOXets+5q9Nq5Jubf9d4MvIlkVe8VnulM2lvwluNxvgpwDKtwO G5aUiaDT1ePHefDKHZzVNl2AwAFbnRQrSnyJB04TdZ71WYUFraITzPqDiLU3BQ8NIsqs 4SlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X8pX7XW2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::32b Subject: [Qemu-devel] [PATCH for-4.0 v2 28/37] tcg/optimize: Optimize bswap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Somehow we forgot these operations, once upon a time. This will allow immediate stores to have their bswap optimized away. Signed-off-by: Richard Henderson --- tcg/optimize.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.17.2 diff --git a/tcg/optimize.c b/tcg/optimize.c index 5dbe11c3c8..6b98ec13e6 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -353,6 +353,15 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) CASE_OP_32_64(ext16u): return (uint16_t)x; + CASE_OP_32_64(bswap16): + return bswap16(x); + + CASE_OP_32_64(bswap32): + return bswap32(x); + + case INDEX_op_bswap64_i64: + return bswap64(x); + case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: return (int32_t)x; @@ -1105,6 +1114,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(ext16s): CASE_OP_32_64(ext16u): CASE_OP_32_64(ctpop): + CASE_OP_32_64(bswap16): + CASE_OP_32_64(bswap32): + case INDEX_op_bswap64_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: From patchwork Fri Nov 23 14:45:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151897 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2229282ljp; Fri, 23 Nov 2018 07:04:35 -0800 (PST) X-Google-Smtp-Source: AFSGD/XD0QtuhS2D0uMGldVWgFcfFXLMz5m7DU47Voy8p9o/8HDL+H177SI1tvcKzNBVOczyRA15 X-Received: by 2002:a25:504e:: with SMTP id e75-v6mr16261790ybb.41.1542985475629; Fri, 23 Nov 2018 07:04:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985475; cv=none; d=google.com; s=arc-20160816; b=Qc8IIvJR4p4GYG0tR9/+8L6k2siw9P7cWfIPRHOroscmI0GMasq7cqRoIfh2tXx111 k5NzPMo9XGySK3s3ngqXXX400Wc+JCPkuxEWZTG7xPYuiM4N6wEPtSiwXpMoBkrGtQyn BPvVcCWLXAN4hx62cX4V6L6esJldbOuz9Chsnynw52asQlnxnkLTV5OdSA4TuV6xEwTd o1W53MJQUzfLKN7nEwV4slH7E/fH6kmDVZhw2UTYA0XxJfg58gA4JQtu6ByVebezgF7d BsaT8++64mhQozstiAz2kXrowfEXNlQkgXj05EW4AeI4KLKfhSPbCB36ravcwB6VY7pv S7PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=iWb2bt6sblF41jXuHpGYj8BfGGXw2Ubf5D8PGYLewXs=; b=TaRQjuDD5vNEEHqWfSRFhI72SaS9A+jwvNOVkDyBZDjuWVZeSI+nwWUbjRLhoCo+Hm 0kE5eG0KxXR0CG6MOEITU4c0OCiaGg/eTXFJEuxVfatb3riVNhr1DiIowRd27aURftAe kITOwkeTzrDDlqcM3+thzaXku7hn99hqJPM197ZvabUpnzNB0pOk+LiDoFbb7bJQhzDn 3sqmFN1FYRRu23XgUb4pNg0rlmVdAf9hAU2mZ5amqwM47x6YUAv3WG8jY+ODy2x8Zu9r 4AwL727V7d2C+OWlzI1uCGOZLPV4dPQw41AyqP4sDtaCSpIRzlRe/4oY/RNRo2VOTcHM 3OnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a8sTexFt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id x126si5244485ywe.25.2018.11.23.07.04.35 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 07:04:35 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a8sTexFt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52850 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD0V-0000h7-14 for patch@linaro.org; Fri, 23 Nov 2018 10:04:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44237) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj4-0000He-S3 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj3-0003ji-FJ for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:34 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38780) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj2-0003dG-LD for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:33 -0500 Received: by mail-wm1-x343.google.com with SMTP id k198so12262516wmd.3 for ; Fri, 23 Nov 2018 06:46:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iWb2bt6sblF41jXuHpGYj8BfGGXw2Ubf5D8PGYLewXs=; b=a8sTexFtSq0vS5HD/6YKoW8iwnDPqy7lqMiQn2QATxs7ABGIsKQnsVjrM1q5cebAc1 BVlADQMTTOwEI5zH7K1Jad1TuB3J5mtRE0EeaoE2TzOKQjpHk/mCnCEjkA2o2po10g3o /1bjNbPs29ElXV4onRvoj9u+Ljqnip4XCuifE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iWb2bt6sblF41jXuHpGYj8BfGGXw2Ubf5D8PGYLewXs=; b=uezoqNzNytYJZNg2AOUnBMur9jNrFxdt+AQ381jbtqcO7RLOG/SF2hhACONhZ8LnD1 ZSLxDbjQcgV2nfdhV02EYAAqo1QDemJvOoADSIfiNLfjkotR/x0aZMtmuav+xSc77s/G v+edKqMGKfZjDn6LD2Qm7PN5YdTCGC/hGHkr+fQQQomcgBvbZtSK600iMqYd00BKHJv9 o0KdoqoRfh0xLZJ68RitKj85C/U8TnMBgeww/NsQqf6/nbXbuB9lZgZWN2LraQbBxlgk 7PBIa0BKXvNVW5xMp6LBV50brrwHl9xbp9kuFtux/xKBbKe4NqIcQh9tOqxET2jacIoX 6Gkw== X-Gm-Message-State: AGRZ1gIv4MiLaeHcgdnwzURtKfnnm/+mP2ljmeZ6MYoxndK71aoy73ZE +F/V3eZ+ZT3R7KBvm1LM+GZTxxcGQEcodQ== X-Received: by 2002:a1c:4406:: with SMTP id r6mr14245953wma.151.1542984388703; Fri, 23 Nov 2018 06:46:28 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:50 +0100 Message-Id: <20181123144558.5048-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 29/37] tcg: Add TCG_TARGET_HAS_MEMORY_BSWAP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For now, defined universally as true, since we previously required backends to implement swapped memory operations. Future patches may now remove that support where it is onerous. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 2 + tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + tcg/tci/tcg-target.h | 2 + tcg/tcg-op.c | 118 ++++++++++++++++++++++++++++++++++++++- 9 files changed, 126 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index d1bd77c41d..0788f2eecb 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -137,6 +137,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 02981abdcc..7a4c55d66d 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -131,6 +131,7 @@ enum { }; #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 1b2d4e1b0d..212ba554e9 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -219,6 +219,8 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 + #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_OOL_LABELS #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index a8222476f0..5cb8672470 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -203,6 +203,7 @@ extern bool use_mips32r2_instructions; #endif #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index bbc49bb1be..6f587010fb 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -128,6 +128,7 @@ void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_OOL_LABELS diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 6f2b06a7d1..853ed6e7aa 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -135,6 +135,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_CALL_STACK_OFFSET 160 #define TCG_TARGET_EXTEND_ARGS 1 +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index d8339bf010..a0ed2a3342 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -164,6 +164,7 @@ extern bool use_vis3_instructions; #define TCG_AREG0 TCG_REG_I0 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 26140d78cb..086f34e69a 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -198,6 +198,8 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) We prefer consistency across hosts on this. */ #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 + static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 887b371a81..1ad095cc35 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2694,25 +2694,78 @@ static void tcg_gen_req_mo(TCGBar type) void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + TCGMemOp orig_memop; + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop = tcg_canonicalize_memop(memop, 0, 0); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); + + orig_memop = memop; + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + memop &= ~MO_BSWAP; + /* The bswap primitive requires zero-extended input. */ + if ((memop & MO_SSIZE) == MO_SW) { + memop &= ~MO_SIGN; + } + } + gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); + + if ((orig_memop ^ memop) & MO_BSWAP) { + switch (orig_memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16_i32(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext16s_i32(val, val); + } + break; + case MO_32: + tcg_gen_bswap32_i32(val, val); + break; + default: + g_assert_not_reached(); + } + } } void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + TCGv_i32 swap = NULL; + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop = tcg_canonicalize_memop(memop, 0, 1); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); + + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + swap = tcg_temp_new_i32(); + switch (memop & MO_SIZE) { + case MO_16: + tcg_gen_ext16u_i32(swap, val); + tcg_gen_bswap16_i32(swap, swap); + break; + case MO_32: + tcg_gen_bswap32_i32(swap, val); + break; + default: + g_assert_not_reached(); + } + val = swap; + memop &= ~MO_BSWAP; + } + gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); + + if (swap) { + tcg_temp_free_i32(swap); + } } void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + TCGMemOp orig_memop; + if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); if (memop & MO_SIGN) { @@ -2723,24 +2776,85 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) return; } + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop = tcg_canonicalize_memop(memop, 1, 0); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); + + orig_memop = memop; + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + memop &= ~MO_BSWAP; + /* The bswap primitive requires zero-extended input. */ + if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) { + memop &= ~MO_SIGN; + } + } + gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); + + if ((orig_memop ^ memop) & MO_BSWAP) { + switch (orig_memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16_i64(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext16s_i64(val, val); + } + break; + case MO_32: + tcg_gen_bswap32_i64(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext32s_i64(val, val); + } + break; + case MO_64: + tcg_gen_bswap64_i64(val, val); + break; + default: + g_assert_not_reached(); + } + } } void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { - tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + TCGv_i64 swap = NULL; + if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); return; } + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop = tcg_canonicalize_memop(memop, 1, 1); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); + + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + swap = tcg_temp_new_i64(); + switch (memop & MO_SIZE) { + case MO_16: + tcg_gen_ext16u_i64(swap, val); + tcg_gen_bswap16_i64(swap, swap); + break; + case MO_32: + tcg_gen_ext32u_i64(swap, val); + tcg_gen_bswap32_i64(swap, swap); + break; + case MO_64: + tcg_gen_bswap64_i64(swap, val); + break; + default: + g_assert_not_reached(); + } + val = swap; + memop &= ~MO_BSWAP; + } + gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); + + if (swap) { + tcg_temp_free_i64(swap); + } } static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) From patchwork Fri Nov 23 14:45:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151911 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2243166ljp; Fri, 23 Nov 2018 07:13:58 -0800 (PST) X-Google-Smtp-Source: AFSGD/XXwiv5OZTMQKYYhPEhdmbxsh2Gw3SFAMQl0V8smej5w+qGSCZIDBNG6Gr1pT0JCZY53G9A X-Received: by 2002:a5b:3d2:: with SMTP id t18-v6mr16059663ybp.225.1542986038801; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 13-v6si13159035ybn.155.2018.11.23.07.13.58 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 07:13:58 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GbT+Q6zH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52911 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD9a-0001YB-6E for patch@linaro.org; Fri, 23 Nov 2018 10:13:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj5-0000Hf-8C for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj3-0003k5-Ld for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:35 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:42971) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj3-0003f9-BL for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:33 -0500 Received: by mail-wr1-x441.google.com with SMTP id q18so12568773wrx.9 for ; Fri, 23 Nov 2018 06:46:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nvPNeDEgNAmGH6OK9GoFq3Wh/emxWAbo55JDKYLtF40=; b=GbT+Q6zHF2T4JZeM/PTL9xgcXwdWHmnnLg1ZlXGbo8BOnl//wQ2y/+MJqnF7wCuM43 3Y6goWEck/UBWvySUiFPy5bufgBJ0TKbE4eob4LHlWlz/Ggi+7NLyB19M/wrruSmvW93 i7bCjwHlDgXc9hDY4si+j6zLvmXJC2IYyYjsM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nvPNeDEgNAmGH6OK9GoFq3Wh/emxWAbo55JDKYLtF40=; b=kkKsC0B/ct9kAgbmdj0Rk8TB9CBeLc20alL1k1OxysYWv2PUNSyvWddfQZA3NkLP9V nEiv6CHYK3LgDzIENBCqNt4PsCBnqFDQQezk9v3dKVbrNN51FtIbci6fGt7k8kttEVkY V0vJXAByx5vCLp5j0TxDulfWLTSrQ1YiVVBQslBiqUpbdUgQPX5vl7NtxOWR3dlMa907 8ClDu5sVgioSOCRil4RSPCtJfTKIsr/UrIfNRIo9CIxzMTCYtBd4gZwYkBkuwcgox4vF 3KaDl4JFZM7TgeZTIGwmW/LNrValuUyja67G2AEGmFBB0u+q56jnAGKZTwTfRY/VptJL vOGQ== X-Gm-Message-State: AA+aEWZBcPaWFKnqMuFbhg0IvoFyeMp9S+eFh9m/w4VPDzVHGZltKL2G 2pCiyVLlJKzkiB6hTj/WnxbnauckSH3phg== X-Received: by 2002:adf:f091:: with SMTP id n17mr14306816wro.292.1542984389462; Fri, 23 Nov 2018 06:46:29 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:51 +0100 Message-Id: <20181123144558.5048-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.0 v2 30/37] tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Always true for softmmu and when movbe is available. In the softmmu case we always have call-clobbered scratch registers available, and having the bswap in the softmmu thunk maximizes code sharing. For user-only and without movbe, leave this to generic code. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 5 ++ tcg/i386/tcg-target.inc.c | 122 ++++++++++++++++++++++++-------------- 2 files changed, 82 insertions(+), 45 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 212ba554e9..2d7cbb5dd6 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -101,6 +101,7 @@ extern bool have_bmi1; extern bool have_popcnt; extern bool have_avx1; extern bool have_avx2; +extern bool have_movbe; /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 @@ -219,7 +220,11 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) +#ifdef CONFIG_SOFTMMU #define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#else +#define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe +#endif #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_OOL_LABELS diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5c68cbd43d..76235e90c9 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -158,13 +158,12 @@ bool have_bmi1; bool have_popcnt; bool have_avx1; bool have_avx2; +bool have_movbe; #ifdef CONFIG_CPUID_H -static bool have_movbe; static bool have_bmi2; static bool have_lzcnt; #else -# define have_movbe 0 # define have_bmi2 0 # define have_lzcnt 0 #endif @@ -1818,13 +1817,24 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, int seg, TCGMemOp memop) { - const TCGMemOp real_bswap = memop & MO_BSWAP; - TCGMemOp bswap = real_bswap; + bool use_bswap = memop & MO_BSWAP; + bool use_movbe = false; int movop = OPC_MOVL_GvEv; - if (have_movbe && real_bswap) { - bswap = 0; - movop = OPC_MOVBE_GyMy; + /* + * Do big-endian loads with movbe or softmmu. + * User-only without movbe will have its swapping done generically. + */ + if (use_bswap) { + if (have_movbe) { + use_bswap = false; + use_movbe = true; + movop = OPC_MOVBE_GyMy; + } else { +#ifndef CONFIG_SOFTMMU + g_assert_not_reached(); +#endif + } } switch (memop & MO_SSIZE) { @@ -1837,40 +1847,52 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, base, index, 0, ofs); break; case MO_UW: - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); - if (real_bswap) { - tcg_out_rolw_8(s, datalo); - } - break; - case MO_SW: - if (real_bswap) { - if (have_movbe) { + if (use_movbe) { + /* There is no extending movbe; only low 16-bits are modified. */ + if (datalo != base && datalo != index) { + /* XOR breaks zeros while breaking dependency chains. */ + tgen_arithr(s, ARITH_XOR, datalo, datalo); tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, datalo, base, index, 0, ofs); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, + datalo, base, index, 0, ofs); + tcg_out_ext16u(s, datalo, datalo); + } + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, + base, index, 0, ofs); + if (use_bswap) { tcg_out_rolw_8(s, datalo); } - tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo); + } + break; + case MO_SW: + if (use_movbe) { + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, + datalo, base, index, 0, ofs); + tcg_out_ext16s(s, datalo, datalo, P_REXW); } else { tcg_out_modrm_sib_offset(s, OPC_MOVSWL + P_REXW + seg, datalo, base, index, 0, ofs); + if (use_bswap) { + tcg_out_rolw_8(s, datalo); + tcg_out_ext16s(s, datalo, datalo, P_REXW); + } } break; case MO_UL: tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); - if (bswap) { + if (use_bswap) { tcg_out_bswap32(s, datalo); } break; #if TCG_TARGET_REG_BITS == 64 case MO_SL: - if (real_bswap) { + if (use_bswap || use_movbe) { tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); - if (bswap) { + if (use_bswap) { tcg_out_bswap32(s, datalo); } tcg_out_ext32s(s, datalo, datalo); @@ -1884,12 +1906,12 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, if (TCG_TARGET_REG_BITS == 64) { tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, base, index, 0, ofs); - if (bswap) { + if (use_bswap) { tcg_out_bswap64(s, datalo); } } else { - if (real_bswap) { - int t = datalo; + if (use_bswap || use_movbe) { + TCGReg t = datalo; datalo = datahi; datahi = t; } @@ -1904,14 +1926,14 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); } - if (bswap) { + if (use_bswap) { tcg_out_bswap32(s, datalo); tcg_out_bswap32(s, datahi); } } break; default: - tcg_abort(); + g_assert_not_reached(); } } @@ -1991,24 +2013,34 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, intptr_t ofs, int seg, TCGMemOp memop) { - /* ??? Ideally we wouldn't need a scratch register. For user-only, - we could perform the bswap twice to restore the original value - instead of moving to the scratch. But as it is, the L constraint - means that TCG_REG_L0 is definitely free here. */ const TCGReg scratch = TCG_REG_L0; - const TCGMemOp real_bswap = memop & MO_BSWAP; - TCGMemOp bswap = real_bswap; + bool use_bswap = memop & MO_BSWAP; + bool use_movbe = false; int movop = OPC_MOVL_EvGv; - if (have_movbe && real_bswap) { - bswap = 0; - movop = OPC_MOVBE_MyGy; + /* + * Do big-endian stores with movbe or softmmu. + * User-only without movbe will have its swapping done generically. + */ + if (use_bswap) { + if (have_movbe) { + use_bswap = false; + use_movbe = true; + movop = OPC_MOVBE_MyGy; + } else { +#ifndef CONFIG_SOFTMMU + g_assert_not_reached(); +#endif + } } switch (memop & MO_SIZE) { case MO_8: - /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. - Use the scratch register if necessary. */ + /* + * In 32-bit mode, 8-bit stores can only happen from [abcd]x. + * ??? Adjust constraints such that this is is forced, then + * we won't need a scratch at all for user-only. + */ if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); datalo = scratch; @@ -2017,7 +2049,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, datalo, base, ofs); break; case MO_16: - if (bswap) { + if (use_bswap) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); tcg_out_rolw_8(s, scratch); datalo = scratch; @@ -2025,7 +2057,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, tcg_out_modrm_offset(s, movop + P_DATA16 + seg, datalo, base, ofs); break; case MO_32: - if (bswap) { + if (use_bswap) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); tcg_out_bswap32(s, scratch); datalo = scratch; @@ -2034,13 +2066,13 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, break; case MO_64: if (TCG_TARGET_REG_BITS == 64) { - if (bswap) { + if (use_bswap) { tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo); tcg_out_bswap64(s, scratch); datalo = scratch; } tcg_out_modrm_offset(s, movop + P_REXW + seg, datalo, base, ofs); - } else if (bswap) { + } else if (use_bswap) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); tcg_out_bswap32(s, scratch); tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, ofs); @@ -2048,8 +2080,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, tcg_out_bswap32(s, scratch); tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, ofs+4); } else { - if (real_bswap) { - int t = datalo; + if (use_movbe) { + TCGReg t = datalo; datalo = datahi; datahi = t; } @@ -2058,7 +2090,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, } break; default: - tcg_abort(); + g_assert_not_reached(); } } From patchwork Fri Nov 23 14:45:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151893 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2221644ljp; Fri, 23 Nov 2018 06:59:31 -0800 (PST) X-Google-Smtp-Source: AJdET5d8gp1eoINMnJBljsvXEYPIcUPYuynOqw0iQSBAuKK/HVhv0yBTErCRY+RYov7ukptguLne X-Received: by 2002:a81:33c4:: with SMTP id z187mr16927847ywz.294.1542985171233; Fri, 23 Nov 2018 06:59:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985171; cv=none; d=google.com; s=arc-20160816; b=nkCsSAjIIbickuIkhcTwttXucg/x5Hd7A/Zv3WMxFrxFCiYcjeCX5X3QxZdayv3igV N6QeXHtYKwpifVWxTv6ZMgNaqdOGvAsoPKTOpAoNgConuv22gfuUgnKGrs6cQbPdeyjb CoMB6tE5Jgiz8c5jiltibYOzP0mjVCmMjzD3p9Rajk7zef6HUulj4e4rogQIduyxW6BY 9Zra9PVqx8xXIwne/H4XTiC6DXDSb/FL/HuFzXvxfTZ8hdvDPUXJwYBZgFhxIC0f41LV wh/wq89d2LQSRZTiGTvFnp5FCwwzn8hxwNVQaZlet7MXwh7cXTVKbYJ4ABSCCywVxeks us4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=YsfD7bGBwOuFfa/KmNIqjSeHrUGXixpyPRKCYYVgwws=; b=M5kIM7WOmXg6GUi+urfgwzeeoCzTdxqZ5mGiLxGzEIO5eAp3fZ5lGo4ZbsIpF46MKU FHoxxeEGmTT1cYDaWqO/zVQQClFxeaCdiB/8krJL5+ZwhhAbbbxUJmubYAACRYna09uO z6Mmu2PM9UmJA8DQXQbBci1wdziV+bxKga9QFKz40Ee0FkND+Hw0hf3YNc+WwFuViC8/ oEFD+g72/WbAqB540zoCcE0E45mYNQ7S9O3xCWOV7f1Gdx51S6egCYSGLvYeJxBiEX1b y9Wl0xixqdh2yQYbURUTeoZDvxrxSb6fHxP6p2wTS3p0e9coabNvpkib/eGNrU+PzHR5 GJPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VxBJdg0h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 138si12713160ywn.1.2018.11.23.06.59.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 06:59:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VxBJdg0h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52823 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCva-00051e-Le for patch@linaro.org; Fri, 23 Nov 2018 09:59:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44220) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj4-0000Hc-J9 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj3-0003jY-Dy for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:34 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:50879) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj1-0003fW-Od for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:32 -0500 Received: by mail-wm1-x343.google.com with SMTP id 125so12200375wmh.0 for ; Fri, 23 Nov 2018 06:46:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YsfD7bGBwOuFfa/KmNIqjSeHrUGXixpyPRKCYYVgwws=; b=VxBJdg0h0LcJdWxFQ8PwIcT2N1FLWAXxjqUiM/twpeTrWiQF4kO2wEu9rp5b/1Ujq0 fg9JKXmc/HP0hRKR9rx7eEZq5vD0mludMZcprfbH0xIvi9xumfMrg9fRc4GdIJZWCVV3 bgkrV+uK4tHYiNaqwaNyXaaxrF3GT9LsK2sRA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YsfD7bGBwOuFfa/KmNIqjSeHrUGXixpyPRKCYYVgwws=; b=W4iZZ6FgADE8cqPGH4NovONVv5bFe4IoFJ+h4AhJPx6CtH0D6npsd8G8vzZgW2Usdh UuBqFNy6U/TZIEKrs2r+6dBImXBG5+uG2IyAHIlpIHb/ya9TKXiVrgdfaOPc3ZXN8Fmi QVSxFkCEOyad0bMjtWlhNecfGxvvOKaymhP80colgfVb593pKsVWjgjNMd0sg4pcRcD9 ACvYYqzEB0Zrf3kpr1gh3VF++ynjAhAw3F72QxX72SxiZLrMAGROAufCp7iYR9o1lYVu sXg05gwIKeF1MchQK6X9Fr4L3adf26xVHqFh0vj2SvIRxx9EC4sFpzegGCJGjykdsJIL bivA== X-Gm-Message-State: AA+aEWY0iHBt5DNyQv5CygM+HyPZU/yCMM81PFHXasTMzL0pPAodJPG9 yje5C6QIrjl2RRSoIkqr0L9F5SNfooXq5g== X-Received: by 2002:a1c:aecb:: with SMTP id x194mr13021798wme.96.1542984390174; Fri, 23 Nov 2018 06:46:30 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:52 +0100 Message-Id: <20181123144558.5048-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 v2 31/37] tcg/aarch64: Set TCG_TARGET_HAS_MEMORY_BSWAP to false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows us to remove some code from the backend, allowing the generic code to emit any extra bswaps. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 51 +++++++----------------------------- 2 files changed, 10 insertions(+), 43 deletions(-) -- 2.17.2 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 0788f2eecb..7f55d50400 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -137,7 +137,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 8edea527f7..34f9347cdf 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1485,8 +1485,6 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - const TCGMemOp bswap = memop & MO_BSWAP; - switch (memop & MO_SSIZE) { case MO_UB: tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); @@ -1497,43 +1495,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext, break; case MO_UW: tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev16(s, data_r, data_r); - } break; case MO_SW: - if (bswap) { - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); - tcg_out_rev16(s, data_r, data_r); - tcg_out_sxt(s, ext, MO_16, data_r, data_r); - } else { - tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), - data_r, addr_r, otype, off_r); - } + tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), + data_r, addr_r, otype, off_r); break; case MO_UL: tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev32(s, data_r, data_r); - } break; case MO_SL: - if (bswap) { - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); - tcg_out_rev32(s, data_r, data_r); - tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r); - } else { - tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); - } + tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); break; case MO_Q: tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev64(s, data_r, data_r); - } break; default: - tcg_abort(); + g_assert_not_reached(); } } @@ -1541,35 +1518,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - const TCGMemOp bswap = memop & MO_BSWAP; - switch (memop & MO_SIZE) { case MO_8: tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); break; case MO_16: - if (bswap && data_r != TCG_REG_XZR) { - tcg_out_rev16(s, TCG_REG_TMP, data_r); - data_r = TCG_REG_TMP; - } tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r); break; case MO_32: - if (bswap && data_r != TCG_REG_XZR) { - tcg_out_rev32(s, TCG_REG_TMP, data_r); - data_r = TCG_REG_TMP; - } tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r); break; case MO_64: - if (bswap && data_r != TCG_REG_XZR) { - tcg_out_rev64(s, TCG_REG_TMP, data_r); - data_r = TCG_REG_TMP; - } tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); break; default: - tcg_abort(); + g_assert_not_reached(); } } @@ -1578,6 +1541,8 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, { TCGMemOp memop = get_memop(oi); + tcg_debug_assert(!(memop & MO_BSWAP)); + #ifdef CONFIG_SOFTMMU /* Ignore the requested "ext". We get the same correct result from * a 16-bit sign-extended to 64-bit as we do sign-extended to 32-bit, @@ -1608,6 +1573,8 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, { TCGMemOp memop = get_memop(oi); + tcg_debug_assert(!(memop & MO_BSWAP)); + #ifdef CONFIG_SOFTMMU bool is_64 = (memop & MO_SIZE) == MO_64; From patchwork Fri Nov 23 14:45:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151912 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2248975ljp; Fri, 23 Nov 2018 07:18:21 -0800 (PST) X-Google-Smtp-Source: AFSGD/V2TkTS7Cy0w9fHx70dxnJJ10tnlqSSh7j6WBp0Oaer2jA/ZLArTAUQZkqT59LhJ/BhQJjy X-Received: by 2002:a81:e40b:: with SMTP id r11mr7370305ywl.56.1542986301330; Fri, 23 Nov 2018 07:18:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542986301; cv=none; d=google.com; s=arc-20160816; b=tqA/A9cd/gLOor537QvByCT82RDoStE0+PF65WbeGtN1NCwy8D8LuaZtEyUKSj60eX F6dyIGza6tgg8uiwzn7SjRe5b5SiimFaXxN+61J+8vJJ0YmetbNhLFBGr1VJXOi0oaOy eKt4/io6ApkS6/dUYbjvEmU4poo98sgAmqqIu0j7jhkC3BoEub9fHF5wTwfI77+Bs1L/ tBVGa/ivJoIwqv1dRtpRiGqW1RQBSdrtRVKv9ZjT/faYQdgwW1ZlgufoZqK6xvsGCAjp 7Qv81NZ/aXah7UUOSdP2zBUC4EksfdDaTtQKk/2NuT9iwliTOmd/4X2GRG7261JEIRjH p4ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=HTYkvsG0udVGuawIRsgNi33ekLoZkN1Kc95kEWex73U=; b=kFJKyKjwQyeyewd6WeLnHLdPXAMX7WTfNwP8PHg51hG0YqviEJKrnvgL6giV4BUXmf S8PCN1bpy3V+X0WUyI7CJKKga7ed2KMWjcS6KFF9l8XUbbah0MJDHfEUuBqR12oXoI0y X2XehAFi8IXJuJZNUkbZOTDkHVGDcD5L3IxSiVMJQg5pJW9+t29YyiRfoCOe7KdTS5c6 G4uNdUvxxEvAFdcGeq1v9PyS5/vex8HgjUhfvPNOAJj9IY/u6Xs6INYkxAWzaySskHDi KRrem5rqHcP499GFjT77UYJMDu6ZCouH+2IDfZ4QIaU6fvAk+Z6qHuycAwzW7LhNfzvr L6Yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Jv5aw1gX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.0 v2 32/37] tcg/arm: Set TCG_TARGET_HAS_MEMORY_BSWAP to false for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Letting the generic code emit any bswaps allows us to avoid reserving an extra register for CONFIG_USER_ONLY. For SOFTMMU, where we have free call-clobbered registers anyway, leaving the bswap in the out-of-line thunk maximizes code sharing. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 4 ++ tcg/arm/tcg-target.inc.c | 129 +++++++++++++-------------------------- 2 files changed, 48 insertions(+), 85 deletions(-) -- 2.17.2 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 7a4c55d66d..a05310a684 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -131,7 +131,11 @@ enum { }; #define TCG_TARGET_DEFAULT_MO (0) +#ifdef CONFIG_SOFTMMU #define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#else +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#endif static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 5a15f6a546..898701f105 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -270,15 +270,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, ct->u.regs = 0xffff; break; - /* qemu_st address & data */ - case 's': - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; - /* r0-r1 doing the byte swapping, so don't use these */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); - break; - default: return NULL; } @@ -1363,6 +1354,7 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc, TCGReg addrlo, TCGReg addend) { TCGMemOp bswap = opc & MO_BSWAP; + assert(USING_SOFTMMU || !bswap); switch (opc & MO_SSIZE) { case MO_UB: @@ -1386,7 +1378,6 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc, } break; case MO_UL: - default: tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); if (bswap) { tcg_out_bswap32(s, COND_AL, datalo, datalo); @@ -1416,6 +1407,8 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc, } } break; + default: + g_assert_not_reached(); } } @@ -1424,6 +1417,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg addrlo) { TCGMemOp bswap = opc & MO_BSWAP; + assert(!USING_SOFTMMU && !bswap); switch (opc & MO_SSIZE) { case MO_UB: @@ -1434,47 +1428,24 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, break; case MO_UW: tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - if (bswap) { - tcg_out_bswap16(s, COND_AL, datalo, datalo); - } break; case MO_SW: - if (bswap) { - tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - tcg_out_bswap16s(s, COND_AL, datalo, datalo); - } else { - tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); - } + tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); break; case MO_UL: - default: tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - if (bswap) { - tcg_out_bswap32(s, COND_AL, datalo, datalo); - } break; case MO_Q: - { - TCGReg dl = (bswap ? datahi : datalo); - TCGReg dh = (bswap ? datalo : datahi); - - /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions - && (dl & 1) == 0 && dh == dl + 1) { - tcg_out_ldrd_8(s, COND_AL, dl, addrlo, 0); - } else if (dl == addrlo) { - tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4); - tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0); - } else { - tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0); - tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4); - } - if (bswap) { - tcg_out_bswap32(s, COND_AL, dl, dl); - tcg_out_bswap32(s, COND_AL, dh, dh); - } + if (datalo == addrlo) { + tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); + tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); + } else { + tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); } break; + default: + g_assert_not_reached(); } } @@ -1485,19 +1456,18 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) TCGReg datalo __attribute__((unused)); TCGReg datahi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc; datalo = *args++; datahi = (is64 ? *args++ : 0); addrlo = *args++; addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0); oi = *args++; - opc = get_memop(oi); #ifdef CONFIG_SOFTMMU add_ldst_ool_label(s, true, is64, oi, R_ARM_PC24, 0); tcg_out_bl_noaddr(s, COND_AL); #else + TCGMemOp opc = get_memop(oi); if (guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP); @@ -1512,6 +1482,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc, TCGReg addrlo, TCGReg addend) { TCGMemOp bswap = opc & MO_BSWAP; + assert(USING_SOFTMMU || !bswap); switch (opc & MO_SIZE) { case MO_8: @@ -1526,7 +1497,6 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc, } break; case MO_32: - default: if (bswap) { tcg_out_bswap32(s, cond, TCG_REG_R0, datalo); tcg_out_st32_r(s, cond, TCG_REG_R0, addrlo, addend); @@ -1535,20 +1505,32 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc, } break; case MO_64: - /* Avoid strd for user-only emulation, to handle unaligned. */ if (bswap) { - tcg_out_bswap32(s, cond, TCG_REG_R0, datahi); - tcg_out_st32_rwb(s, cond, TCG_REG_R0, addend, addrlo); - tcg_out_bswap32(s, cond, TCG_REG_R0, datalo); - tcg_out_st32_12(s, cond, TCG_REG_R0, addend, 4); - } else if (USING_SOFTMMU && use_armv6_instructions - && (datalo & 1) == 0 && datahi == datalo + 1) { + /* + * Assert inputs are where I think, for the softmmu thunk. + * One pair of R0/R1 or R2/R3 will be free and call-clobbered, + * which allows the use of STRD below. Note the bswaps also + * reverse the lo/hi registers to swap the two words. + */ + tcg_debug_assert(addend == TCG_REG_TMP); + tcg_debug_assert(datalo == TCG_REG_R4); + tcg_debug_assert(datahi == TCG_REG_R5); + datalo = addrlo == TCG_REG_R1 ? TCG_REG_R2 : TCG_REG_R0; + datahi = datalo + 1; + tcg_out_bswap32(s, cond, datalo, TCG_REG_R5); + tcg_out_bswap32(s, cond, datahi, TCG_REG_R4); + } + /* Avoid strd for user-only emulation, to handle unaligned. */ + if (USING_SOFTMMU && use_armv6_instructions + && (datalo & 1) == 0 && datahi == datalo + 1) { tcg_out_strd_r(s, cond, datalo, addrlo, addend); } else { tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); tcg_out_st32_12(s, cond, datahi, addend, 4); } break; + default: + g_assert_not_reached(); } } @@ -1557,43 +1539,25 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg addrlo) { TCGMemOp bswap = opc & MO_BSWAP; + assert(!USING_SOFTMMU && !bswap); switch (opc & MO_SIZE) { case MO_8: tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0); break; case MO_16: - if (bswap) { - tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0); - } else { - tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); - } + tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); break; case MO_32: - default: - if (bswap) { - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0); - } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - } + tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); break; case MO_64: /* Avoid strd for user-only emulation, to handle unaligned. */ - if (bswap) { - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0); - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 4); - } else if (USING_SOFTMMU && use_armv6_instructions - && (datalo & 1) == 0 && datahi == datalo + 1) { - tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); - } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); - } + tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); break; + default: + g_assert_not_reached(); } } @@ -1604,19 +1568,18 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) TCGReg datalo __attribute__((unused)); TCGReg datahi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc; datalo = *args++; datahi = (is64 ? *args++ : 0); addrlo = *args++; addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0); oi = *args++; - opc = get_memop(oi); #ifdef CONFIG_SOFTMMU add_ldst_ool_label(s, false, is64, oi, R_ARM_PC24, 0); tcg_out_bl_noaddr(s, COND_AL); #else + TCGMemOp opc = get_memop(oi); if (guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); tcg_out_qemu_st_index(s, COND_AL, opc, datalo, @@ -2055,11 +2018,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } }; static const TCGTargetOpDef a_b = { .args_ct_str = { "a", "b" } }; static const TCGTargetOpDef c_b = { .args_ct_str = { "c", "b" } }; static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } }; static const TCGTargetOpDef a_c_d = { .args_ct_str = { "a", "c", "d" } }; static const TCGTargetOpDef a_b_b = { .args_ct_str = { "a", "b", "b" } }; static const TCGTargetOpDef e_c_d = { .args_ct_str = { "e", "c", "d" } }; @@ -2072,8 +2033,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) = { .args_ct_str = { "r", "r", "rIK" } }; static const TCGTargetOpDef r_r_r_r = { .args_ct_str = { "r", "r", "r", "r" } }; - static const TCGTargetOpDef s_s_s_s - = { .args_ct_str = { "s", "s", "s", "s" } }; static const TCGTargetOpDef a_b_c_d = { .args_ct_str = { "a", "b", "c", "d" } }; static const TCGTargetOpDef e_f_c_d @@ -2175,7 +2134,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) } case INDEX_op_qemu_st_i32: if (!USING_SOFTMMU) { - return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s; + return TARGET_LONG_BITS == 32 ? &r_r : &r_r_r; } else if (TARGET_LONG_BITS == 32) { return &c_b; /* temps available r0, r3, r12 */ } else { @@ -2183,7 +2142,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) } case INDEX_op_qemu_st_i64: if (!USING_SOFTMMU) { - return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s; + return TARGET_LONG_BITS == 32 ? &r_r_r : &r_r_r_r; } else if (TARGET_LONG_BITS == 32) { return &e_f_b; /* temps available r0, r2, r3, r12 */ } else { From patchwork Fri Nov 23 14:45:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151913 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2249361ljp; Fri, 23 Nov 2018 07:18:39 -0800 (PST) X-Google-Smtp-Source: AFSGD/Ui9e2tuCITbRPBBLHA0omH3z2ltwmt0QcmFfcoBq3RRcQJk6YGF513kmUzugUZCO669OPZ X-Received: by 2002:a81:4506:: with SMTP id s6mr12246932ywa.200.1542986319560; Fri, 23 Nov 2018 07:18:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542986319; cv=none; d=google.com; s=arc-20160816; b=qxIRAtCx5SZyOcCEIoYOQ1qzeF1Yj701oslpzJ/tVx5GUMVo0RALVkvrrLLvbE4C52 ULDydAFsNBdoPFsELVsbbhSaAQmhU4M0uPX+Gh/FEzQrIkmKG502Cuj/gdcjd3ap7VEA H5lvCxECCyFxnnQtrJGv6BQgdYz/2ZdPdYzqeBNCUZR1ka5cHHU+T+DBhinsbdauyw9x OxvpJ/f6WLVRuse0ad97zR8ZPkmbREsH4sNWo4tMGhX/Q8dRnb7P/tdgr3PsWepG7w4I t3zo35P9a0cSMq4EUMfKpinUj9gEZtq85AK7eXkyVkNpm9J3Z7Qi1AKQYr55rAQce8L/ pBQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ftMZ3fz35dYKoMc8uTCKp7fh8kUWUt+B2yZR69ArZfM=; b=Xja7UjuqCSBnEX31g37RLouHMV5EF+6SS+cDL/jcb8ZUGqXrgZPaQg/oR0p4XaNMyo jc49kwAfsOuXzJu0JsoykDx9e8PgtNxG/xRuZRtohLLPuKW70usTmYofjwgjSiZ8I7yx oP5Q4RaPOp8kw/yulE1eLOY2vtFoHkJtuysQWKjbJYbq4U3rnvVKieHJOw2R/UCWd74d EyfO9DBs9XdcFRdkgQqmCWGqSFjpOuPbkeKFSWDUyepJDIs5/kT+tSrP2UKbeYN/Apl6 KQH0N0sxTOyZMf9B9ZAoZ9ctB4516rnbQ3Zb2xgeebLx7EncuvkvZbFsSo+rgEfXGF0c OwJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C0BGPmG6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.0 v2 33/37] tcg/i386: Propagate is64 to tcg_out_qemu_ld_direct X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This can save a few rex prefixes for qemu_ld_i32. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 76235e90c9..5cad31cfe5 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1815,10 +1815,11 @@ static inline void setup_guest_base_seg(void) { } static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, - int seg, TCGMemOp memop) + int seg, bool is64, TCGMemOp memop) { bool use_bswap = memop & MO_BSWAP; bool use_movbe = false; + int rexw = is64 * P_REXW; int movop = OPC_MOVL_GvEv; /* @@ -1843,7 +1844,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, base, index, 0, ofs); break; case MO_SB: - tcg_out_modrm_sib_offset(s, OPC_MOVSBL + P_REXW + seg, datalo, + tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, base, index, 0, ofs); break; case MO_UW: @@ -1871,14 +1872,15 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, if (use_movbe) { tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, datalo, base, index, 0, ofs); - tcg_out_ext16s(s, datalo, datalo, P_REXW); - } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSWL + P_REXW + seg, + tcg_out_ext16s(s, datalo, datalo, rexw); + } else if (use_bswap) { + tcg_out_modrm_sib_offset(s, OPC_MOVSWL + seg, + datalo, base, index, 0, ofs); + tcg_out_rolw_8(s, datalo); + tcg_out_ext16s(s, datalo, datalo, rexw); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, datalo, base, index, 0, ofs); - if (use_bswap) { - tcg_out_rolw_8(s, datalo); - tcg_out_ext16s(s, datalo, datalo, P_REXW); - } } break; case MO_UL: @@ -2004,7 +2006,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) } tcg_out_qemu_ld_direct(s, datalo, datahi, - base, index, offset, seg, opc); + base, index, offset, seg, is64, opc); } #endif } @@ -2202,7 +2204,7 @@ static tcg_insn_unit *tcg_out_qemu_ldst_ool(TCGContext *s, bool is_ld, /* TLB Hit. */ if (is_ld) { - tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, opc); + tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, is_64, opc); } else { tcg_out_qemu_st_direct(s, datalo, datahi, base, 0, 0, opc); } From patchwork Fri Nov 23 14:45:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151908 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2239577ljp; Fri, 23 Nov 2018 07:11:32 -0800 (PST) X-Google-Smtp-Source: AFSGD/VeeLCwHVMni8VjlYDUClGzEe9V1XbnMX7zMnGWkTQ4en7dAWYe1Gqa+Aa2aMVLS30ld+0E X-Received: by 2002:a25:2317:: with SMTP id j23-v6mr9898021ybj.457.1542985891966; Fri, 23 Nov 2018 07:11:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985891; cv=none; d=google.com; s=arc-20160816; b=n32f0tm1olAGyyuCJwaKg7j662HicV5z3B/GAC2SCRX/58bW0q4wZfaPgE+cQQIr09 7tOr1sKLBq12F+noAgMCjqZ2XIGphAZXYXM6YxLDd8ah9G27o1aJWmqWKg1iyVWhrfrN ql9oaudJNxsvMABbzrj+UhKddDP6QV/Ixg5RoQaScK8ti5mbdM87Nr72TvE4FlhTZBNL E8yY+gDBpI31HqF2xD6Ojw2/UtoAB3K1AJqrBbY4pA/3cvSQCwMZy+FP4dtDNXQQLEX7 iRViDGEGB3LKRhNtdGxr5uiUj6a4js/HAbc2sezaR3iCphX17oXG8atY+us3yPvB4zfT tS4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=rRT9/p5Z5WH4Z+cvxcGe8HvxMvUgIXvOL8XKXtOdL3Q=; b=O9wDM5bkTiqwsLGz8LuhjWfpbCQueaSxG38gJdiyoec6MmoQT11rUjHPpNs+xgwPDH MdDiEWOoYrGxqj+DiHHGjeSjniS04xQjTgwNiZKPIJ6yGyA973CGDCwtyIm9ELQEFqdI 0s77tRixH8eB62hf7+Wz2m74AflOH9gO60xr1smnNK07u0w1WQDnprqZQx6l0bRbAVW8 +L/DZCkjelO6uu+2aHga2mnCXSODVficgjFjEHDZhzvnLlcqu7VTUxPvxbwBgEbQ8Hzj NMP6yoHnrLiGI+8sk/MoHXuNDPvTHlL7TacBlTEnoUWgysziocePhMmzYQX5FE6mpVBw ejVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NMrK4yOj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a2-v6si3299975yba.55.2018.11.23.07.11.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 07:11:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NMrK4yOj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52897 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD7D-0007jh-1r for patch@linaro.org; Fri, 23 Nov 2018 10:11:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44269) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj6-0000Hi-RH for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj4-0003le-QU for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:35 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:37567) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj4-0003kD-IY for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:34 -0500 Received: by mail-wr1-x444.google.com with SMTP id j10so12586691wru.4 for ; Fri, 23 Nov 2018 06:46:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rRT9/p5Z5WH4Z+cvxcGe8HvxMvUgIXvOL8XKXtOdL3Q=; b=NMrK4yOjLkiSLE8TME8a3eXKO3wvsG2NKYSed76gz+LY0Wgy0FYRkGT/LtXsu3TCzw UFF1MxZ/UCPXZayKUwFA9ghpt0jXmf2WdcFn4wYL/JohGFva9LppwUeKj+9dg3ganEVz 1Z9/xWV1wQwKbfWsRTayc4ZEbeyZSa+rsUcm0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rRT9/p5Z5WH4Z+cvxcGe8HvxMvUgIXvOL8XKXtOdL3Q=; b=Ym6PfzApAuFeceUJHglleYjeZXLHgRRd1VeP7Fx3oaJ95jG9IwH04kKarllhp3OdaG wZO1/JZqx1V8L+MNqiQV7VVP6WNnowzphx16zWKN7I/6SEMQzUhhHdn3hdKYKc3McKS9 OsuDu4aQKdnkkICEpHSiGldo34u/ZyJNwVXkq4YwtSolZ6Pbu+uT2gx5uXHZmEBzbdYU X0LJ85fibLJ2SAIGFv8ayvF33nTAVn2URTzqxP9kJVQB2utjxn0akAfPgmv3CYaAY4Ez F92sn7NlbVSRonezt6hTnTZg14+i7TdrSP+qlUMQsw2cT8CQO5xJ90nlxoJg+7cabpzY sdeQ== X-Gm-Message-State: AA+aEWbp82PA9VGm1u2/mYxV91383nnbhETV3q6mS0D26OalKEHNUcit 5RHPOa/5HuS2OVpdXHwP57lv90jqGvL0bg== X-Received: by 2002:adf:d0c9:: with SMTP id z9mr13797760wrh.317.1542984393079; Fri, 23 Nov 2018 06:46:33 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:55 +0100 Message-Id: <20181123144558.5048-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 34/37] tcg/i386: Restrict user-only qemu_st_i32 values to q-regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is one more step toward the removal of all scratch registers during user-only guest memory operations. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5cad31cfe5..79de8d0cd2 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -240,7 +240,17 @@ static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, int hi) #else static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, int hi) { - return "L"; + if (TCG_TARGET_REG_BITS == 64) { + /* Temps are still needed for guest_base && !guest_base_flags. */ + return "L"; + } else if (type == ARG_STVAL && !is_64) { + /* Byte stores must happen from q-regs. Because of this, we must + * constrain all INDEX_op_qemu_st_i32 to use q-regs. + */ + return "q"; + } else { + return "r"; + } } #endif /* CONFIG_SOFTMMU */ @@ -2038,15 +2048,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, switch (memop & MO_SIZE) { case MO_8: - /* - * In 32-bit mode, 8-bit stores can only happen from [abcd]x. - * ??? Adjust constraints such that this is is forced, then - * we won't need a scratch at all for user-only. - */ - if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - datalo = scratch; - } + /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. */ + tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4); tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, datalo, base, ofs); break; From patchwork Fri Nov 23 14:45:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151906 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2238812ljp; Fri, 23 Nov 2018 07:11:01 -0800 (PST) X-Google-Smtp-Source: AJdET5dZV/piOAsinl/jEgb2IuHeiJyhoG2vExPiaJgaoTqQCS67PwdyFuVz3+xOzW88ELc3GYBj X-Received: by 2002:a0d:dc42:: with SMTP id f63-v6mr16994887ywe.62.1542985861405; Fri, 23 Nov 2018 07:11:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542985861; cv=none; d=google.com; s=arc-20160816; b=QrCurDaD4zwjSsWQRIkklyM9TnWTZeQW8/D7UWwrivkfYAtvMB2xrEOtqLUGJvKU+F 5wUOk2lK2ydzCTV79MZltN5lfb37NtlbVTdGMifgZrpRiUzb/lJb5fZohuQDa7vS7fS9 TiAHqgEv2sKedqUdcHsXNVZUvxeB1lbF8aarnPIxb8KdhcMrpT980dj9Qa+6Ksk0gIRD j5yGxTBxK2OjvQoql3YKaxgrYldoxPUDBfEnDKeBTG7k7UJOFCVf6zWFYx8el/6Rga23 Amc8AqG7Z2/pLOiJwfePCfdVdIldA4KIEmExxm6Rkb7oZ1QF+Ep1utbmGS3rL7aTBKlk yVrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=pjRtmlyYSb1VLkGjhaHARmsTCgNRA8M6YYDKvLblOwM=; b=U5tnjpjRcE1wtk+0rN4xD2KAmJNCBfeJh9kErpmtniPIrsY++ZYiKVf0/+FODELyh1 4pmx6T/66dl0uJBoCuWDXaQf8HQLrncmdXvdxfG8BJK4uCdsm6sf/QbEy5lzQ5nCnGL4 UHZPFsn9ysA9k5tUR+2F4IbvCEcJWi0vUUgBgnJZk9CKE2d630HnZaBaOxkXgSiJGhPo TX9BJ3O/mnMUSLtky+XYlcnhRWXJPr+gyt84PRFE0QpoercYuPb/BxyuMYSTZYFLiJYl 4p+hZU98EHzh4Ee5E0TZQODlGAst4Ez5ec3jdMIcHfCRzcK+67gpTgVP0gy0NXe3UT4C 0ToA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IW95SJNH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 35/37] tcg/i386: Add setup_guest_base_seg for FreeBSD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 79de8d0cd2..55c5a8516c 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1818,6 +1818,16 @@ static inline void setup_guest_base_seg(void) guest_base_flags = P_GS; } } +#elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) +# include + +static int guest_base_flags; +static inline void setup_guest_base_seg(void) +{ + if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { + guest_base_flags = P_GS; + } +} #else # define guest_base_flags 0 static inline void setup_guest_base_seg(void) { } From patchwork Fri Nov 23 14:45:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151910 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2242832ljp; Fri, 23 Nov 2018 07:13:47 -0800 (PST) X-Google-Smtp-Source: AFSGD/WS/8+TceHPO16X9ANMKdm0WnMi17LMPHWaMSf0V2oP3rUTbyJdovEBhrr2hqi5MhOlGyG8 X-Received: by 2002:a25:aae2:: with SMTP id t89-v6mr16172523ybi.200.1542986027322; Fri, 23 Nov 2018 07:13:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542986027; cv=none; d=google.com; s=arc-20160816; b=kZabEf8XbFOzFJNu4H7rOohAkMhrtXVFtlqdiReUnTzb5lyofWUw63uIPenPOVecJY sBKIjKgUjuf89pl3xaMvew8jrWIJ4HxXaalEpZCVc/HoRDHVKzRFkxgcPgGkArRsQks2 kVcIZxblNi6yvAcfV7HcE+WyZ2r/iyZhRgn+VzXpDJTnTFZYY8VQFljzDuQ5d3WUShNe OIOKY9ePIFwwzd/zT8ZRVRdQOArBj9PnK6B9rWWcZr9VkJ9OV5+Bzak7OJ201ZVJF9Yk 8ObeWtHavRoXswpR+2/JdQQGrNrqRjw3UxFIhhPwabSISeCQl8oGa27Hzy95hKGcSBwY T8WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=V/tj+x4QtHxVBYlyQISxW8ufV35sYtEtQxxPmnqUysE=; b=sK1dqzNx2rn1vLNP8TCqlYKnKu1frhJDfPV5dk3KmApxY7okhjYrNsQ+WOOOd+9pzM SAcgbR+NXtotUXmCj3Vu52TdcJmrTC93Ib36pAuyYsrfF4uuQjo4ZhEBhuZlTP3guX9g hquCsS3FsXWjhO3nuobYjkNBYAzzGuWS7ap2Saf282aR5AF30GrRv87WGE2rVsaVayMc nDFAKhg09ecwhvQHpjq8Fgjx+fR2KCgGCw325vkolzyOwdJHuqtN8vv7j3S8hSFK3xTp j7kj18k4WEzvRjpg3NvA+aua4NfsJr9sS2CC8dEmsr4Uliso4Rl/ravI0fD3t+x+Tt6b fjrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hP4OZGZe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s126-v6si35449366yba.267.2018.11.23.07.13.47 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 07:13:47 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hP4OZGZe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52909 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD9O-0001MZ-J9 for patch@linaro.org; Fri, 23 Nov 2018 10:13:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44334) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj9-0000LT-Cq for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj6-0003pH-MU for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:39 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:50879) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj6-0003nu-GY for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:36 -0500 Received: by mail-wm1-x341.google.com with SMTP id 125so12200616wmh.0 for ; Fri, 23 Nov 2018 06:46:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V/tj+x4QtHxVBYlyQISxW8ufV35sYtEtQxxPmnqUysE=; b=hP4OZGZei8NzZOZZq4OPeDcY7xKz+fnV+V8ZUI2IFJgMMxQFCl4aFt9+Pnk1jN+5MM 9edwPiTSgUfUZGbPjy2UrxpDXuvsaePSOoN0zWCOUD6jRBEWBqg1qB//ha+8tw3KlxJ2 sfaaf91mDBLV1b6+1maMx1N1hIObKag3EF/3k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V/tj+x4QtHxVBYlyQISxW8ufV35sYtEtQxxPmnqUysE=; b=J0VTvWygSs60QWMc8E6WKNqTvoNEX0tQuhDRghUyWgRfP/FvO53JdZv1PQFeRx2Gtl fb43jd9XkgpZb+R2S3KfeuRGSOJzWPbTyM3kF0kbgGp8PueCPJLkSzLyczbV5V7ipET9 3vUBRk5d3c8xNdgnITmXXRVrjvsOw8nE8cHuPG6MZqF83zHac/4okp4YdF9Di7ebfSvC f6PysLl3K3IljhUhX0lqEyMHPVZny/U7dMqhwilr/xuzFlchGry1wVDRa41U0+r45mby lkv3DIT8HX4p69JtDKn78O+UHlJEOAi9N5AsDcxWDpEoV3iHhJntY0Z/QL0UsSuRj3Wa Uc1g== X-Gm-Message-State: AGRZ1gLNVYAUvGzFFB5mpKvue/AsyGXkcHCqiBeUUR/z9dAWk82Cnsyp jvmwGoxK9eSnC6ucsDIht05B1O2tBnp/lg== X-Received: by 2002:a1c:a754:: with SMTP id q81mr13200585wme.132.1542984395154; Fri, 23 Nov 2018 06:46:35 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:57 +0100 Message-Id: <20181123144558.5048-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 36/37] tcg/i386: Require segment syscalls to succeed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There ought be no reason they should ever fail. If we don't know how to set a segment base register for user-only (NetBSD, OpenBSD?), then error out if we cannot proceed. This is one more step toward the removal of all scratch registers during user-only guest memory operations. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 54 +++++++++++++++++---------------------- 1 file changed, 23 insertions(+), 31 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 55c5a8516c..19a0fa8a03 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1814,9 +1814,12 @@ int arch_prctl(int code, unsigned long addr); static int guest_base_flags; static inline void setup_guest_base_seg(void) { - if (arch_prctl(ARCH_SET_GS, guest_base) == 0) { - guest_base_flags = P_GS; + /* There is no reason this syscall should fail. */ + if (arch_prctl(ARCH_SET_GS, guest_base) < 0) { + perror("arch_prctl(ARCH_SET_GS)"); + exit(1); } + guest_base_flags = P_GS; } #elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) # include @@ -1824,13 +1827,28 @@ static inline void setup_guest_base_seg(void) static int guest_base_flags; static inline void setup_guest_base_seg(void) { - if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { - guest_base_flags = P_GS; + /* There is no reason this syscall should fail. */ + if (sysarch(AMD64_SET_GSBASE, &guest_base) < 0) { + perror("sysarch(AMD64_SET_GSBASE)"); + exit(1); } + guest_base_flags = P_GS; } #else # define guest_base_flags 0 -static inline void setup_guest_base_seg(void) { } +static inline void setup_guest_base_seg(void) +{ + /* + * Verify we can proceed without scratch registers. + * If guest_base > INT32_MAX, then it would need to be loaded. + * If 32-bit guest, the address would need to be zero-extended. + */ + if (TCG_TARGET_REG_BITS == 64 + && (TARGET_LONG_BITS == 32 || guest_base > INT32_MAX)) { + error_report("Segment base register not supported on this OS"); + exit(1); + } +} #endif /* SOFTMMU */ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, @@ -2013,16 +2031,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { seg |= P_ADDR32; } - } else if (TCG_TARGET_REG_BITS == 64) { - if (TARGET_LONG_BITS == 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base = TCG_REG_L0; - } - if (offset != guest_base) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index = TCG_REG_L1; - offset = 0; - } } tcg_out_qemu_ld_direct(s, datalo, datahi, @@ -2156,22 +2164,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { seg |= P_ADDR32; } - } else if (TCG_TARGET_REG_BITS == 64) { - /* ??? Note that we can't use the same SIB addressing scheme - as for loads, since we require L0 free for bswap. */ - if (offset != guest_base) { - if (TARGET_LONG_BITS == 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base = TCG_REG_L0; - } - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base); - base = TCG_REG_L1; - offset = 0; - } else if (TARGET_LONG_BITS == 32) { - tcg_out_ext32u(s, TCG_REG_L1, base); - base = TCG_REG_L1; - } } tcg_out_qemu_st_direct(s, datalo, datahi, base, offset, seg, opc); From patchwork Fri Nov 23 14:45:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151914 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2251817ljp; Fri, 23 Nov 2018 07:20:40 -0800 (PST) X-Google-Smtp-Source: AFSGD/V8+jB413K6RZnZRiNB/eAB6mVOolY4Zh+11wNYI02qycchcVOyt/05L74qT8VpSRw66CyE X-Received: by 2002:a81:e903:: with SMTP id d3mr6183308ywm.53.1542986440659; Fri, 23 Nov 2018 07:20:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542986440; cv=none; d=google.com; s=arc-20160816; b=CLPSOLio4t2yQC6Z7/AN7gSTU1TM+u4ldBT9nzsaK5FyVWiBu4eUkYMjxenLWET6lR Ixof1cjL3NsyKDups4qeW+B1lIjiKq/cW9Q1rBFIaAii3uwrt0CcsQuKNaAajefptuDc eBH1GbJT0yTXpl+YrNrfvbmv4CNowno1MmaVlLCh3+dPck1R6ZpAnWWla6jAvcU4/6iS HGGXX0/wKqRu4ToqMhel/1adt8fYDfjhApjcyXBK3/M9LcRHaS6du/8657spBLM/9+Qf HZyesJk6VoXgHVVG5rZW/Nz+ekXPF7Wq3LveqUUF2W+ic7Pu2wxBQ+WFofKsuGjiAert GTCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=b79TMT1xsQ1kNxl+TOgvq76GlDxOHE/SHes3qAZINQQ=; b=igeD95R0Y+XtxLf2vrUQPTRcSiETpMITt2YAR1oABZ/6qzFhNwhfkUCo28z0T8nla7 73Lc9OQG0yO9kTPbtSxLhw47H5kxhyb3bUdBXmoqPi+T6cLu2eavdomE3Vc5aH1HltTp Ugjqc5csN8MGP7jGXUf+0GRY9b92B6KVN96cjxQCZHRCtLEpBSsiDiZ8bBZDr2fTQuga h9DKFr8WAAAG5CdyLERTXiOysL/9a6V3MSP0lq2ahZipt7OXbtBrKPq/KcUmcxTLL1EJ xKzuw8V1wgxmzfW7JskwXhyAJNlQofzOWomcRzOTRw6QvPEbEI9rSvsoxGHk1U1tKe0G Znww== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XDdC8TkT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 37/37] tcg/i386: Remove L constraint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We no longer need any scratch registers for user-only memory ops. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 19a0fa8a03..2815dd25a0 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -240,10 +240,7 @@ static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, int hi) #else static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, int hi) { - if (TCG_TARGET_REG_BITS == 64) { - /* Temps are still needed for guest_base && !guest_base_flags. */ - return "L"; - } else if (type == ARG_STVAL && !is_64) { + if (TCG_TARGET_REG_BITS == 32 && type == ARG_STVAL && !is_64) { /* Byte stores must happen from q-regs. Because of this, we must * constrain all INDEX_op_qemu_st_i32 to use q-regs. */ @@ -353,14 +350,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, ct->u.regs |= ALL_VECTOR_REGS; break; - /* qemu_ld/st address constraint */ - case 'L': - ct->ct |= TCG_CT_REG; - ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); - break; - case 'e': ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32); break;