From patchwork Fri Feb 4 14:46:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 539929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38795C4321E for ; Fri, 4 Feb 2022 14:46:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359408AbiBDOqu (ORCPT ); Fri, 4 Feb 2022 09:46:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345529AbiBDOqu (ORCPT ); Fri, 4 Feb 2022 09:46:50 -0500 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9C34C061744 for ; Fri, 4 Feb 2022 06:46:49 -0800 (PST) Received: by mail-lj1-x22a.google.com with SMTP id q22so8814650ljh.7 for ; Fri, 04 Feb 2022 06:46:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rPkuuzEWFvZ+7dgk9RSn0ku3pRGEa9D7Qqz+AeteWoE=; b=o0+wFNvAqkVME/NNoGbBG+koZHoFJAo6KpsL0Pry9/W9mmuH9ydDbTopaaOMkLFvhX jSXlKNhOxMIcn1DLwYxR1bNZylCL3hFolh+cfybIES9AB6jEylsjGADe4F+dfUgEpeZI 7Zor5enMD0rHRP2eBPlYnImXEkLpF6ln7C0R8BbxjI3VYbjaXnSqV+GF3sjV1O2J5pKM OWJOnFiGT0FooU47Ns5KVhpyOp3B3AfAS5KZq3QFDBxWBAZx2B2CtJbZ2s8nuM5X78q9 8aD3c44ZJLWAwH29fWZDwC5jNFCfQxEPmSOFqWYxEgOISmu+LrWCdUok9xxAfADWUM1G psLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rPkuuzEWFvZ+7dgk9RSn0ku3pRGEa9D7Qqz+AeteWoE=; b=5yLIiYd8MZqoNkgOtDQVayfuhbHxIzPIAjK/bhlcE0y75GRX/+eqkUrHGUj9jXg2pV xgiAkm1Y9pYQzpg61ldbPyx2lUm+oLInvm5ZPpsyqXsMghIbEDrAMlCUlt7wlyCpu7E+ 1iqphGCMxAqx4eatNX4McY7Uq56l3KZY6nxeYVzjXHp/gWjsx+k7RWF85xsDZ+TyyiUb Q7zEHsSdeyVACWHfUeKijfvajNMmIjOK03Y/b3Q0RmCdGumZLqmfxEAsuKAGvjk68Lsk bPBcTggTu7/jUN0lqDPxsH0MePcwNeH0pD/LwmGaSmcKVM7Kvk5eHvvbCMXNcJpT+y52 ZqOA== X-Gm-Message-State: AOAM531+kocNhCZ7hPOXGwA1UzACfZ3Gse0gyouay6H0HBOjsdiKHIVC 0614W7JajVccNouJ3QIb0Tr/lg== X-Google-Smtp-Source: ABdhPJyI52y6JCeoGwpRWzLaR3ogw2OKjlHYJLAxqhMrrL9Jsd86ueIxfVPjkzHz2V+eWSt9nobd/w== X-Received: by 2002:a2e:9f54:: with SMTP id v20mr2090108ljk.438.1643986007968; Fri, 04 Feb 2022 06:46:47 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y23sm348222lfb.2.2022.02.04.06.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 06:46:47 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 01/11] dt-bindings: pci: qcom,pcie: drop unused "pipe" clocks Date: Fri, 4 Feb 2022 17:46:35 +0300 Message-Id: <20220204144645.3016603-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The "pipe" clock is now unused by the PCIe driver. Drop it from the bindings. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index a0ae024c2d0c..da08f0f9de96 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -154,7 +154,6 @@ - "bus_slave" Slave AXI clock - "slave_q2a" Slave Q2A clock - "tbu" PCIe TBU clock - - "pipe" PIPE clock - clock-names: Usage: required for sc8180x and sm8250 @@ -167,7 +166,6 @@ - "slave_q2a" Slave Q2A clock - "tbu" PCIe TBU clock - "ddrss_sf_tbu" PCIe SF TBU clock - - "pipe" PIPE clock - resets: Usage: required From patchwork Fri Feb 4 14:46:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 540101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB6F3C41535 for ; Fri, 4 Feb 2022 14:46:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359411AbiBDOqv (ORCPT ); Fri, 4 Feb 2022 09:46:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345529AbiBDOqu (ORCPT ); Fri, 4 Feb 2022 09:46:50 -0500 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9235CC06173D for ; Fri, 4 Feb 2022 06:46:50 -0800 (PST) Received: by mail-lf1-x134.google.com with SMTP id a28so13053295lfl.7 for ; Fri, 04 Feb 2022 06:46:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MEdow9qddiDDi5ISDFCGH7oeKbC5mGu6c1RrTKNWX/Y=; b=pxis1hg/jlw5nQXur7Gh7MiTW2H9lfVjjHk8A47b24zGh1f7tHppvK+MIUPUY4OY8n Dx05ufn+XyCnJZbceeUFgovtuRPY2k1gDGOhq2ioYQHyomz3Rnp0h9kd5hKVSvBQzfPP PL3F0T6kZ2h58IXCz9UMvkAG7VlLVxmBXuQ1KfiIpmjj3DOuDJd9/C+fGcN1xkhG86Ai TViDoAn5mTZwF7UdV7ijPvQfKfKC3cSfVYeIiEeWyoHH5RSU23DC7rjz/r1XPqN+1QxX 8WTg7EHgjBkAbSs/ydMNae2elZdfh8ERGf9tdm9zE+8RPl2czDFrvQk3Ls7ik/DBEYu0 r/5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MEdow9qddiDDi5ISDFCGH7oeKbC5mGu6c1RrTKNWX/Y=; b=skwU4kmHRQnt5mNAP89vP9Bv63iiaBl07+96HpmVDwFCGSSMa6jOPc7npKALy6aA55 ijsyWSmg3HZCSPqNYj56/+avwgW3nQ3AMBIUnMnm2v/5SKjiuG4WpuLMSO+SRcYpTH1w tQQgScvj1RgYUcRIByj0iFXXK/MK9L4bGVoRFSlDjKuGzxngohbom/RBp5wKSRQrrL2O A4HvFZ9uUfHf6u9SdSCCN//pXjmz60xrgyJge0COlB/MXki8/nS115+vRx3bqT7r9N2y c2I22m6Wq5hGLF2jcXSrjp0MmiaPtOKwBwhSf1T/Fgei3vmrWYqUXgP73VydHMrWEFEd 0ARw== X-Gm-Message-State: AOAM531TydW7NmMIOaG8psD38Qc8L6gH0HCCNn0RvgAXccCbq7iIHtYX Nj0GqzAnLwy2vYPoWZi+bMOqQg== X-Google-Smtp-Source: ABdhPJxuroIeSr4dcdPBz5jQ7IC0iZSdzhMqVc+7fGNygeMObTcH4hddM7moDZztQ897nFdhKsNRFw== X-Received: by 2002:ac2:5095:: with SMTP id f21mr2484888lfm.20.1643986008900; Fri, 04 Feb 2022 06:46:48 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y23sm348222lfb.2.2022.02.04.06.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 06:46:48 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v2 02/11] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Date: Fri, 4 Feb 2022 17:46:36 +0300 Message-Id: <20220204144645.3016603-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use different set of clocks, so two compatible entries are required. Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.txt | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index da08f0f9de96..65a1fa74e4eb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -15,6 +15,8 @@ - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 - "qcom,pcie-ipq6018" for ipq6018 - reg: @@ -167,6 +169,20 @@ - "tbu" PCIe TBU clock - "ddrss_sf_tbu" PCIe SF TBU clock +- clock-names: + Usage: required for sm8450-pcie0 and sm8450-pcie1 + Value type: + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock + - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 + - "aggre1" Aggre NoC PCIe1 AXI clock + - resets: Usage: required Value type: @@ -244,7 +260,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sc8180x, sdm845 and sm8250 + Usage: required for sc8180x, sdm845, sm8250 and sm8450 Value type: Definition: Should contain the following entries - "pci" PCIe core reset From patchwork Fri Feb 4 14:46:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 539928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4320C433F5 for ; Fri, 4 Feb 2022 14:46:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345529AbiBDOqw (ORCPT ); Fri, 4 Feb 2022 09:46:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348235AbiBDOqv (ORCPT ); Fri, 4 Feb 2022 09:46:51 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76186C061714 for ; Fri, 4 Feb 2022 06:46:51 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id i34so13174745lfv.2 for ; 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Fri, 04 Feb 2022 06:46:49 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y23sm348222lfb.2.2022.02.04.06.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 06:46:49 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 03/11] clk: qcom: gdsc: add support for clocks tied to the GDSC Date: Fri, 4 Feb 2022 17:46:37 +0300 Message-Id: <20220204144645.3016603-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On newer Qualcomm platforms GCC_PCIE_n_PIPE_CLK_SRC should be controlled together with the PCIE_n_GDSC. The clock should be fed from the TCXO before switching the GDSC off and can be fed from PCIE_n_PIPE_CLK once the GDSC is on. Since commit aa9c0df98c29 ("PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280") PCIe controller driver tries to manage this on it's own, resulting in the non-optimal code. Furthermore, if the any of the drivers will have the same requirements, the code would have to be dupliacted there. Move handling of such clocks to the GDSC code, providing special GDSC type. Cc: Prasad Malisetty Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gdsc.c | 41 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 14 ++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 7e1dd8ccfa38..9913d1b70947 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -45,6 +45,7 @@ #define TIMEOUT_US 500 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd) +#define domain_to_pipe_clk_gdsc(domain) container_of(domain, struct pipe_clk_gdsc, base.pd) enum gdsc_status { GDSC_OFF, @@ -549,3 +550,43 @@ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) return 0; } EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable); + +/* + * Special operations for GDSCs with attached pipe clocks. + * The clock should be parked to safe source (tcxo) before turning off the GDSC + * and can be switched on as soon as the GDSC is on. + * + * We remove respective clock sources from clocks map and handle them manually. + */ +int gdsc_pipe_enable(struct generic_pm_domain *domain) +{ + struct pipe_clk_gdsc *sc = domain_to_pipe_clk_gdsc(domain); + int i, ret; + + ret = gdsc_enable(domain); + if (ret) + return ret; + + for (i = 0; i< sc->num_clocks; i++) + regmap_update_bits(sc->base.regmap, sc->clocks[i].reg, + BIT(sc->clocks[i].shift + sc->clocks[i].width) - BIT(sc->clocks[i].shift), + sc->clocks[i].on_value << sc->clocks[i].shift); + + return 0; +} +EXPORT_SYMBOL_GPL(gdsc_pipe_enable); + +int gdsc_pipe_disable(struct generic_pm_domain *domain) +{ + struct pipe_clk_gdsc *sc = domain_to_pipe_clk_gdsc(domain); + int i; + + for (i = sc->num_clocks - 1; i >= 0; i--) + regmap_update_bits(sc->base.regmap, sc->clocks[i].reg, + BIT(sc->clocks[i].shift + sc->clocks[i].width) - BIT(sc->clocks[i].shift), + sc->clocks[i].off_value << sc->clocks[i].shift); + + /* In case of an error do not try turning the clocks again. We can not be sure about the GDSC state. */ + return gdsc_disable(domain); +} +EXPORT_SYMBOL_GPL(gdsc_pipe_disable); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index d7cc4c21a9d4..b1a2f0abe41c 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -68,11 +68,25 @@ struct gdsc_desc { size_t num; }; +struct pipe_clk_gdsc { + struct gdsc base; + int num_clocks; + struct { + u32 reg; + u32 shift; + u32 width; + u32 off_value; + u32 on_value; + } clocks[]; +}; + #ifdef CONFIG_QCOM_GDSC int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, struct regmap *); void gdsc_unregister(struct gdsc_desc *desc); int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain); +int gdsc_pipe_enable(struct generic_pm_domain *domain); +int gdsc_pipe_disable(struct generic_pm_domain *domain); #else static inline int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *rcdev, From patchwork Fri Feb 4 14:46:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 540100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C8D2C4707A for ; Fri, 4 Feb 2022 14:46:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359427AbiBDOqx (ORCPT ); Fri, 4 Feb 2022 09:46:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359420AbiBDOqw (ORCPT ); Fri, 4 Feb 2022 09:46:52 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 482EFC06174A for ; Fri, 4 Feb 2022 06:46:52 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id z19so13017487lfq.13 for ; Fri, 04 Feb 2022 06:46:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4itJXUtYogtLjP/C5kuslRrxl4UhvqybVmRTOjqgGzk=; b=MHe9zlCFy+vkTW3PBcu6vL52zJprEi+YLERBnYbQKhGcQyBGJ/Pq8GfhJCt6Rx9dOA lxqnBlgHmrdy76qvZgMFaRbnkd/fjqyefS9sRQXkoSFfc2JtOH642XKXU313ThMzzdAw gGIMPTP3mQR0HRA6RdkXkRe8gzRThvh7RB/ODO0Wxw6gI84GSr6R2o2msPpgTtLyDAy8 dW6QhGmmiJ/toOFDCjuuuCQda1HsjY7vGXleRZ+PkTzeKAhliYR61kpU1WqjMVibRTC6 +dAeLqgHkrDTMTrB9mrvj/81rK5sMki13dH7CC7lb5uhKhfzZ1/s0stJCb9Lcvv9/dRx Xaug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4itJXUtYogtLjP/C5kuslRrxl4UhvqybVmRTOjqgGzk=; b=H9NfXuSPXH/0Mma4mGYmoop9+rDG2I/1VJ+0GXqcIEV8LFpRjIVhIgPu0r/4DFx5Sr F0KTEi6wMaulwIQg4dOyoZJlzITmAdpW1BfVxywsBdONPi0DMpwruMR8/1Jn8Z2dSR1D BJS+2Wav2k8TxiFVxktQqQLYo8CEplvzESmfuLS2U8AJdg+CqhBfwQHKxzL+kV01ykfO 3Vb5Zw9NxBk7S4As8mqcboxXWWl5nwdCohIz+2B9wXNNJ5CN6gzQJPprd1RiSK5idKE/ 3ljfJ4rmPyTOj8/OwRWPpFX0dV4VldCxKXjuf25xyLrKZ8CAPgzUdgcA8IcSh/rtSdv3 KHAw== X-Gm-Message-State: AOAM530/m6D+BgDJVbkjAd5KKdhoFhA7c8QXb79ZoBpBQTYCufDtD9/G oNFBPkhRx6Ec7dX3SwMVV/4RHg== X-Google-Smtp-Source: ABdhPJxP9osAP8Paagwb19g2FhSJKpP3HNDj150cw/KJOYE6z151czlCbpyDUrW8QSsUZ9Q0f4gKUg== X-Received: by 2002:a05:6512:33d2:: with SMTP id d18mr2596891lfg.370.1643986010575; Fri, 04 Feb 2022 06:46:50 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y23sm348222lfb.2.2022.02.04.06.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 06:46:50 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 04/11] clk: qcom: gcc-sc7280: switch PCIe GDSCs to pipe_clk_gdsc Date: Fri, 4 Feb 2022 17:46:38 +0300 Message-Id: <20220204144645.3016603-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change sc7280's PCIe GDSCs to use new API for managing corresponding pipe clock sources. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-sc7280.c | 114 ++++++++++++---------------------- 1 file changed, 40 insertions(+), 74 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 423627d49719..e88a2a2416ff 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -255,26 +255,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = { { .hw = &gcc_gpll0_out_even.clkr.hw }, }; -static const struct parent_map gcc_parent_map_6[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_6[] = { - { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - -static const struct parent_map gcc_parent_map_7[] = { - { P_PCIE_1_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_7[] = { - { .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - static const struct parent_map gcc_parent_map_8[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -369,36 +349,6 @@ static const struct clk_parent_data gcc_parent_data_15[] = { { .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { - .reg = 0x6b054, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_6, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, - }, - }, -}; - -static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { - .reg = 0x8d054, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_7, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_pipe_clk_src", - .parent_data = gcc_parent_data_7, - .num_parents = ARRAY_SIZE(gcc_parent_data_7), - .ops = &clk_regmap_mux_closest_ops, - }, - }, -}; - static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { .reg = 0x77058, .shift = 0, @@ -1757,10 +1707,6 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk", - .parent_hws = (const struct clk_hw*[]){ - &gcc_pcie_0_pipe_clk_src.clkr.hw, - }, - .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, @@ -1847,10 +1793,6 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { .enable_mask = BIT(30), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk", - .parent_hws = (const struct clk_hw*[]){ - &gcc_pcie_1_pipe_clk_src.clkr.hw, - }, - .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, @@ -3113,22 +3055,48 @@ static struct clk_branch gcc_wpss_rscp_clk = { }, }; -static struct gdsc gcc_pcie_0_gdsc = { - .gdscr = 0x6b004, - .pd = { - .name = "gcc_pcie_0_gdsc", +static struct pipe_clk_gdsc gcc_pcie_0_gdsc = { + .base = { + .gdscr = 0x6b004, + .pd = { + .name = "gcc_pcie_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, + }, + .num_clocks = 1, + .clocks = { + { + /* gcc_pcie_0_pipe_clk_src */ + .reg = 0x6b054, + .shift = 0, + .width = 2, + .on_value = 0, + .off_value = 2, + }, }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, }; -static struct gdsc gcc_pcie_1_gdsc = { - .gdscr = 0x8d004, - .pd = { - .name = "gcc_pcie_1_gdsc", +static struct pipe_clk_gdsc gcc_pcie_1_gdsc = { + .base = { + .gdscr = 0x8d004, + .pd = { + .name = "gcc_pcie_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, + }, + .num_clocks = 1, + .clocks = { + { + /* gcc_pcie_1_pipe_clk_src */ + .reg = 0x8d054, + .shift = 0, + .width = 2, + .on_value = 0, + .off_value = 2, + }, }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, }; static struct gdsc gcc_ufs_phy_gdsc = { @@ -3244,7 +3212,6 @@ static struct clk_regmap *gcc_sc7280_clocks[] = { [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, - [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, @@ -3253,7 +3220,6 @@ static struct clk_regmap *gcc_sc7280_clocks[] = { [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, - [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, [GCC_PCIE_THROTTLE_CORE_CLK] = &gcc_pcie_throttle_core_clk.clkr, @@ -3391,8 +3357,8 @@ static struct clk_regmap *gcc_sc7280_clocks[] = { }; static struct gdsc *gcc_sc7280_gdscs[] = { - [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc, - [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc, + [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc.base, + [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc.base, [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc, From patchwork Fri Feb 4 14:46:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 539927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 308E6C433FE for ; Fri, 4 Feb 2022 14:46:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359406AbiBDOqy (ORCPT ); Fri, 4 Feb 2022 09:46:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359428AbiBDOqx (ORCPT ); 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Fri, 04 Feb 2022 06:46:50 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 05/11] clk: qcom: gcc-sm8450: switch PCIe GDSCs to pipe_clk_gdsc Date: Fri, 4 Feb 2022 17:46:39 +0300 Message-Id: <20220204144645.3016603-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change sm8450's PCIe GDSCs to use new API for managing corresponding pipe clock sources. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-sm8450.c | 104 ++++++++++++++-------------------- 1 file changed, 42 insertions(+), 62 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 593a195467ff..a81456598b28 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -153,16 +153,6 @@ static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_4[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_4[] = { - { .fw_name = "pcie_0_pipe_clk", }, - { .fw_name = "bi_tcxo", }, -}; - static const struct parent_map gcc_parent_map_5[] = { { P_PCIE_1_PHY_AUX_CLK, 0 }, { P_BI_TCXO, 2 }, @@ -239,21 +229,6 @@ static const struct clk_parent_data gcc_parent_data_11[] = { { .fw_name = "bi_tcxo" }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { - .reg = 0x7b060, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_4, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_4, - .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_regmap_mux_closest_ops, - }, - }, -}; - static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { .reg = 0x9d080, .shift = 0, @@ -269,21 +244,6 @@ static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { }, }; -static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { - .reg = 0x9d064, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_6, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_pipe_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, - }, - }, -}; - static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { .reg = 0x87060, .shift = 0, @@ -1546,10 +1506,6 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw, - }, - .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, @@ -1687,10 +1643,6 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { .enable_mask = BIT(30), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw, - }, - .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, @@ -2952,20 +2904,50 @@ static struct clk_branch gcc_video_axi1_clk = { }, }; -static struct gdsc pcie_0_gdsc = { - .gdscr = 0x7b004, - .pd = { - .name = "pcie_0_gdsc", +static struct pipe_clk_gdsc pcie_0_gdsc = { + .base = { + .gdscr = 0x7b004, + .pd = { + .name = "pcie_0_gdsc", + .power_on = gdsc_pipe_enable, + .power_off = gdsc_pipe_disable, + }, + .pwrsts = PWRSTS_OFF_ON, + }, + .num_clocks = 1, + .clocks = { + { + /* gcc_pcie_0_pipe_clk_src */ + .reg = 0x7b060, + .shift = 0, + .width = 2, + .on_value = 0, + .off_value = 2, + }, }, - .pwrsts = PWRSTS_OFF_ON, }; -static struct gdsc pcie_1_gdsc = { - .gdscr = 0x9d004, - .pd = { - .name = "pcie_1_gdsc", +static struct pipe_clk_gdsc pcie_1_gdsc = { + .base = { + .gdscr = 0x9d004, + .pd = { + .name = "pcie_1_gdsc", + .power_on = gdsc_pipe_enable, + .power_off = gdsc_pipe_disable, + }, + .pwrsts = PWRSTS_OFF_ON, + }, + .num_clocks = 1, + .clocks = { + { + /* gcc_pcie_1_pipe_clk_src */ + .reg = 0x9d064, + .shift = 0, + .width = 2, + .on_value = 0, + .off_value = 2, + }, }, - .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc ufs_phy_gdsc = { @@ -3022,7 +3004,6 @@ static struct clk_regmap *gcc_sm8450_clocks[] = { [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, - [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, @@ -3035,7 +3016,6 @@ static struct clk_regmap *gcc_sm8450_clocks[] = { [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, - [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, @@ -3216,8 +3196,8 @@ static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { }; static struct gdsc *gcc_sm8450_gdscs[] = { - [PCIE_0_GDSC] = &pcie_0_gdsc, - [PCIE_1_GDSC] = &pcie_1_gdsc, + [PCIE_0_GDSC] = &pcie_0_gdsc.base, + [PCIE_1_GDSC] = &pcie_1_gdsc.base, [UFS_PHY_GDSC] = &ufs_phy_gdsc, [USB30_PRIM_GDSC] = &usb30_prim_gdsc, }; From patchwork Fri Feb 4 14:46:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 539925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52C41C47081 for ; Fri, 4 Feb 2022 14:46:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359419AbiBDOqz (ORCPT ); Fri, 4 Feb 2022 09:46:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359434AbiBDOqy (ORCPT ); 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Fri, 04 Feb 2022 06:46:51 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 06/11] PCI: qcom: Balance pm_runtime_foo() calls Date: Fri, 4 Feb 2022 17:46:40 +0300 Message-Id: <20220204144645.3016603-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fix the error path in qcom_pcie_probe(): remove extra calls to pm_runtime_disable() (which will be called at the end of error path anyway). Replace a call to pm_runtime_get_sync() with pm_runtime_resume_and_get() to end up with cleaner code. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index c19cd506ed3f..85c2ad8c551c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1549,9 +1549,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) return -ENOMEM; pm_runtime_enable(dev); - ret = pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); if (ret < 0) - goto err_pm_runtime_put; + goto err_pm_runtime_disable; pci->dev = dev; pci->ops = &dw_pcie_ops; @@ -1594,7 +1594,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) ret = phy_init(pcie->phy); if (ret) { - pm_runtime_disable(&pdev->dev); goto err_pm_runtime_put; } @@ -1603,7 +1602,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "cannot initialize host\n"); - pm_runtime_disable(&pdev->dev); goto err_pm_runtime_put; } @@ -1611,6 +1609,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) err_pm_runtime_put: pm_runtime_put(dev); +err_pm_runtime_disable: pm_runtime_disable(dev); return ret; From patchwork Fri Feb 4 14:46:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 540099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 876ECC4167B for ; Fri, 4 Feb 2022 14:46:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359453AbiBDOq4 (ORCPT ); Fri, 4 Feb 2022 09:46:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359441AbiBDOqz (ORCPT ); Fri, 4 Feb 2022 09:46:55 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBF4AC061748 for ; Fri, 4 Feb 2022 06:46:54 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id u6so13045876lfm.10 for ; Fri, 04 Feb 2022 06:46:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wBgyM0ueC3YQnagy7358MhVbMFS9K44N5LwppvV4cJw=; b=OLh/L8svS1wtY2uPkCq8tELru5lt+F0f9Kj/kX6QOEwPxStaNSpvpRSE9YYsxSn+CA xxeigfCNT1ToVG1kuj+3c1sDnZcKQebxTyepsFdG20Ac2CJJqupoV9idBaVNb3ozWi7x nO33GILp2bpuhzadvkjzP1m3nBjbQRXHheNFdLOXHDvQPoGMsratpvCM/WtzSDXjZcq/ l4HOjc3REjcRoLfZRJD/nL7EWASITs8V4JgMk0RU/aj/oFXF+gVNt26NQvx7VG/cCSwG AiQ04K9jDlztN9fP0j1dJApehPSBgrQcG8o3hpKBxFJUubRpV+jtCl+Cga1Au3WD8k6E MW0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wBgyM0ueC3YQnagy7358MhVbMFS9K44N5LwppvV4cJw=; b=mSjuEdcsr9L5uC71vFd7u1Ud+efw3rGOzoRoBG1RxTXfVJqiasNzLS2aSgMOPpBqY1 QXRlwoaOQ6pSe6/Gs8qXJGU7hOhvEpSycAou27hYvwCBV7jaoR8+VJyZW/d91EvGI/vk aWRu+mFRIMnRN5zwGM0Yn/Fxg1Ymv1yZNF2bsQUd9BQLqcBT0XK9pUAnFvuhH0BScu0W wj9juoNvJHCMXZFUpKQcyrClcA5KvS8TVxhD1ga2JNTP/JHaDMquctEVSTLR3hRxFqWK Dz81mCXw6MURi0FK0yNYWP4JCTrqcQ/NWjQrMKWfZK0x8sLQdiE6Nph4x55d2ifiiF8j zhsg== X-Gm-Message-State: AOAM532Vb6sozxn0cpd4lWqmYAWJ/MhKfuaEKNXMPgYsVHfstnF4LA16 TZzuDtEwgwVUZWiNbo0fcvdfzA== X-Google-Smtp-Source: ABdhPJxrukbQNC+FZLqa/yJD+BzXVfO3Qv1E7UOK7NVSNvEWx9z68+VVlS11SIFkcVYfjfbGW1NGQQ== X-Received: by 2002:ac2:44ac:: with SMTP id c12mr2590865lfm.589.1643986013185; Fri, 04 Feb 2022 06:46:53 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y23sm348222lfb.2.2022.02.04.06.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 06:46:52 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 07/11] PCI: qcom: Remove unnecessary pipe_clk handling Date: Fri, 4 Feb 2022 17:46:41 +0300 Message-Id: <20220204144645.3016603-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org QMP PHY driver already does clk_prepare_enable()/_disable() pipe_clk. Remove extra calls to enable/disable this clock from the PCIe driver, so that the PHY driver can manage the clock on its own. Fixes: aa9c0df98c29 ("PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280") Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 53 ++------------------------ 1 file changed, 3 insertions(+), 50 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 85c2ad8c551c..85e84b621dbc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -128,7 +128,6 @@ struct qcom_pcie_resources_2_3_2 { struct clk *master_clk; struct clk *slave_clk; struct clk *cfg_clk; - struct clk *pipe_clk; struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; @@ -165,7 +164,6 @@ struct qcom_pcie_resources_2_7_0 { int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; - struct clk *pipe_clk; struct clk *pipe_clk_src; struct clk *phy_pipe_clk; struct clk *ref_clk_src; @@ -591,11 +589,7 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) return PTR_ERR(res->master_clk); res->slave_clk = devm_clk_get(dev, "bus_slave"); - if (IS_ERR(res->slave_clk)) - return PTR_ERR(res->slave_clk); - - res->pipe_clk = devm_clk_get(dev, "pipe"); - return PTR_ERR_OR_ZERO(res->pipe_clk); + return PTR_ERR_OR_ZERO(res->slave_clk); } static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) @@ -610,13 +604,6 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } -static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - - clk_disable_unprepare(res->pipe_clk); -} - static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; @@ -691,22 +678,6 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) return ret; } -static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - struct dw_pcie *pci = pcie->pci; - struct device *dev = pci->dev; - int ret; - - ret = clk_prepare_enable(res->pipe_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable pipe clock\n"); - return ret; - } - - return 0; -} - static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; @@ -1190,8 +1161,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) return PTR_ERR(res->ref_clk_src); } - res->pipe_clk = devm_clk_get(dev, "pipe"); - return PTR_ERR_OR_ZERO(res->pipe_clk); + return 0; } static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) @@ -1230,12 +1200,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) goto err_disable_clocks; } - ret = clk_prepare_enable(res->pipe_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable pipe clock\n"); - goto err_disable_clocks; - } - /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); @@ -1287,14 +1251,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) if (pcie->pipe_clk_need_muxing) clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); - return clk_prepare_enable(res->pipe_clk); -} - -static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - - clk_disable_unprepare(res->pipe_clk); + return 0; } static int qcom_pcie_link_up(struct dw_pcie *pci) @@ -1444,9 +1401,7 @@ static const struct qcom_pcie_ops ops_1_0_0 = { static const struct qcom_pcie_ops ops_2_3_2 = { .get_resources = qcom_pcie_get_resources_2_3_2, .init = qcom_pcie_init_2_3_2, - .post_init = qcom_pcie_post_init_2_3_2, .deinit = qcom_pcie_deinit_2_3_2, - .post_deinit = qcom_pcie_post_deinit_2_3_2, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; @@ -1473,7 +1428,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, - .post_deinit = qcom_pcie_post_deinit_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1483,7 +1437,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, - .post_deinit = qcom_pcie_post_deinit_2_7_0, .config_sid = qcom_pcie_config_sid_sm8250, }; From patchwork Fri Feb 4 14:46:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 540097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10CB3C47085 for ; Fri, 4 Feb 2022 14:47:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359440AbiBDOq7 (ORCPT ); Fri, 4 Feb 2022 09:46:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359435AbiBDOq4 (ORCPT ); Fri, 4 Feb 2022 09:46:56 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 946D2C061751 for ; Fri, 4 Feb 2022 06:46:55 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id bu18so13109113lfb.5 for ; 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Fri, 04 Feb 2022 06:46:53 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y23sm348222lfb.2.2022.02.04.06.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 06:46:53 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 08/11] PCI: qcom: Remove pipe_clk_src reparenting Date: Fri, 4 Feb 2022 17:46:42 +0300 Message-Id: <20220204144645.3016603-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SC7280 platform has switched to using GDSC wrapper for setting pipe_clk_src parent clock. Remove supporting code from the pcie-qcom driver. Cc: Prasad Malisetty Cc: Stephen Boyd Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 38 -------------------------- 1 file changed, 38 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 85e84b621dbc..7df8632a21a8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -164,9 +164,6 @@ struct qcom_pcie_resources_2_7_0 { int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; - struct clk *pipe_clk_src; - struct clk *phy_pipe_clk; - struct clk *ref_clk_src; }; union qcom_pcie_resources { @@ -192,7 +189,6 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; - unsigned int pipe_clk_need_muxing:1; }; struct qcom_pcie { @@ -203,7 +199,6 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; - unsigned int pipe_clk_need_muxing:1; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -1147,20 +1142,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; - if (pcie->pipe_clk_need_muxing) { - res->pipe_clk_src = devm_clk_get(dev, "pipe_mux"); - if (IS_ERR(res->pipe_clk_src)) - return PTR_ERR(res->pipe_clk_src); - - res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe"); - if (IS_ERR(res->phy_pipe_clk)) - return PTR_ERR(res->phy_pipe_clk); - - res->ref_clk_src = devm_clk_get(dev, "ref"); - if (IS_ERR(res->ref_clk_src)) - return PTR_ERR(res->ref_clk_src); - } - return 0; } @@ -1178,10 +1159,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - /* Set TCXO as clock source for pcie_pipe_clk_src */ - if (pcie->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->ref_clk_src); - ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1243,17 +1220,6 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } -static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - - /* Set pipe clock as clock source for pcie_pipe_clk_src */ - if (pcie->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); - - return 0; -} - static int qcom_pcie_link_up(struct dw_pcie *pci) { u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -1427,7 +1393,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1436,7 +1401,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, .config_sid = qcom_pcie_config_sid_sm8250, }; @@ -1470,7 +1434,6 @@ static const struct qcom_pcie_cfg sm8250_cfg = { static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, - .pipe_clk_need_muxing = true, }; static const struct dw_pcie_ops dw_pcie_ops = { @@ -1513,7 +1476,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) pcie->pci = pci; pcie->ops = pcie_cfg->ops; - pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing; pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); if (IS_ERR(pcie->reset)) { From patchwork Fri Feb 4 14:46:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 539926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAD7BC35274 for ; Fri, 4 Feb 2022 14:46:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348235AbiBDOq5 (ORCPT ); Fri, 4 Feb 2022 09:46:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359439AbiBDOq4 (ORCPT ); Fri, 4 Feb 2022 09:46:56 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62472C061758 for ; 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Fri, 04 Feb 2022 06:46:54 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y23sm348222lfb.2.2022.02.04.06.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 06:46:54 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 09/11] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Date: Fri, 4 Feb 2022 17:46:43 +0300 Message-Id: <20220204144645.3016603-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation to adding more flags to configuration data, use pointer to struct qcom_pcie_cfg directly inside struct qcom_pcie, rather than duplicating all its fields. This would save us from the boilerplate code that just copies flag values from one struct to another one. Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 37 ++++++++++++-------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 7df8632a21a8..3a0da577b75d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -198,7 +198,7 @@ struct qcom_pcie { union qcom_pcie_resources res; struct phy *phy; struct gpio_desc *reset; - const struct qcom_pcie_ops *ops; + const struct qcom_pcie_cfg *cfg; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -222,8 +222,8 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) struct qcom_pcie *pcie = to_qcom_pcie(pci); /* Enable Link Training state machine */ - if (pcie->ops->ltssm_enable) - pcie->ops->ltssm_enable(pcie); + if (pcie->cfg->ops->ltssm_enable) + pcie->cfg->ops->ltssm_enable(pcie); return 0; } @@ -1307,7 +1307,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp) qcom_ep_reset_assert(pcie); - ret = pcie->ops->init(pcie); + ret = pcie->cfg->ops->init(pcie); if (ret) return ret; @@ -1315,16 +1315,16 @@ static int qcom_pcie_host_init(struct pcie_port *pp) if (ret) goto err_deinit; - if (pcie->ops->post_init) { - ret = pcie->ops->post_init(pcie); + if (pcie->cfg->ops->post_init) { + ret = pcie->cfg->ops->post_init(pcie); if (ret) goto err_disable_phy; } qcom_ep_reset_deassert(pcie); - if (pcie->ops->config_sid) { - ret = pcie->ops->config_sid(pcie); + if (pcie->cfg->ops->config_sid) { + ret = pcie->cfg->ops->config_sid(pcie); if (ret) goto err; } @@ -1333,12 +1333,12 @@ static int qcom_pcie_host_init(struct pcie_port *pp) err: qcom_ep_reset_assert(pcie); - if (pcie->ops->post_deinit) - pcie->ops->post_deinit(pcie); + if (pcie->cfg->ops->post_deinit) + pcie->cfg->ops->post_deinit(pcie); err_disable_phy: phy_power_off(pcie->phy); err_deinit: - pcie->ops->deinit(pcie); + pcie->cfg->ops->deinit(pcie); return ret; } @@ -1447,15 +1447,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct pcie_port *pp; struct dw_pcie *pci; struct qcom_pcie *pcie; - const struct qcom_pcie_cfg *pcie_cfg; int ret; - pcie_cfg = of_device_get_match_data(dev); - if (!pcie_cfg || !pcie_cfg->ops) { - dev_err(dev, "Invalid platform data\n"); - return -EINVAL; - } - pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; @@ -1475,7 +1468,11 @@ static int qcom_pcie_probe(struct platform_device *pdev) pcie->pci = pci; - pcie->ops = pcie_cfg->ops; + pcie->cfg = of_device_get_match_data(dev); + if (!pcie->cfg || !pcie->cfg->ops) { + dev_err(dev, "Invalid platform data\n"); + return -EINVAL; + } pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); if (IS_ERR(pcie->reset)) { @@ -1501,7 +1498,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } - ret = pcie->ops->get_resources(pcie); + ret = pcie->cfg->ops->get_resources(pcie); if (ret) goto err_pm_runtime_put; From patchwork Fri Feb 4 14:46:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 540098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2584C35275 for ; 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Fri, 04 Feb 2022 06:46:55 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 10/11] PCI: qcom: Add ddrss_sf_tbu flag Date: Fri, 4 Feb 2022 17:46:44 +0300 Message-Id: <20220204144645.3016603-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm PCIe driver uses compatible string to check if the ddrss_sf_tbu clock should be used. Since sc7280 support has added flags, switch to the new mechanism to check if this clock should be used. Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 3a0da577b75d..6034a933814d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -189,6 +189,7 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; + bool has_ddrss_sf_tbu_clk; }; struct qcom_pcie { @@ -1131,7 +1132,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[3].id = "bus_slave"; res->clks[4].id = "slave_q2a"; res->clks[5].id = "tbu"; - if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) { + if (pcie->cfg->has_ddrss_sf_tbu_clk) { res->clks[6].id = "ddrss_sf_tbu"; res->num_clks = 7; } else { @@ -1430,6 +1431,7 @@ static const struct qcom_pcie_cfg sdm845_cfg = { static const struct qcom_pcie_cfg sm8250_cfg = { .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { From patchwork Fri Feb 4 14:46:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 539924 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DF40C3527A for ; Fri, 4 Feb 2022 14:47:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359445AbiBDOq7 (ORCPT ); Fri, 4 Feb 2022 09:46:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359457AbiBDOq6 (ORCPT ); Fri, 4 Feb 2022 09:46:58 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F3DAC06173E for ; Fri, 4 Feb 2022 06:46:58 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id a28so13054017lfl.7 for ; Fri, 04 Feb 2022 06:46:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NscpyK0buF1esZkGVw7YGC7D0IZRioFEiEIVQa9+trk=; b=wbrZgVCHOlYdehazV9tmDN39xAHuYi+3rNFSrkcCq9VN01OvR2OTPSZPG8CyIiKA8G DSNHTLRYtsQvq+cXV+9v4ApX5ffBBzhqWhIG9g0JMz3ekQsAPADL5OifjqkIiA4DVIHN JhJZ0MNFw7g4ChZDDTvbhYvB1wi0/gGciHVY6fUDT/u0J1oAH1IsL+jMy62Zs986z7gq dlS4joOzvAE6h+xri4w9QS2H2/ss2fX1tYkn7aBHojoI0UE/29KAsRa54ZIw2ikpcyJS ySjHb2XHrYO/qSNK0lm01Hi/DYNWQDFBAnb4HJvCO67EuObEL1GumW+C0dnOVfeYW7j6 Roiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NscpyK0buF1esZkGVw7YGC7D0IZRioFEiEIVQa9+trk=; b=bS9bhp4CE0uuC89nU05j7YcOpRv2Js8aNCR9TF0nF6FWHoTYvK8CuykEQbHl4XaFrJ mqF8r23wV7IUWiLPX1cjeaysUOfyeIvMtIg2cFHGzxIoGaXtwrIuwqFm67JY6rmJUXa5 +miE9prfbF9ZiLnLRriP9qZG0rih5UoBsnyRpIodxrnYoSioNFUsxsqNgoKJyCSuvWhx BG+pWtGC52C6DqXisb/NjjL8Nwmy4dnFrhzqxARorlqd4PiW63Wtpxk2fs3TLIDfehUG nNNdgmEfSPL7mnGeYm3O3aXc6MB4wS0qNkG76Z3Fj2tTI1Z7JsuxqgE12C6O0R+J/5sj Bjhg== X-Gm-Message-State: AOAM532XOGNE8A/ZAT5O39f0WlXON7HWezq529qSCvRyL2xA2P9yNVqt 4pAFJJVOU0G8FfqNNi6Mj8FmsA== X-Google-Smtp-Source: ABdhPJxS9geMjJJ4T0bw6fthvvK2zsIEnWkglafbati+yS00A5lLdU81L665O92HzIUDSHK+IBye+w== X-Received: by 2002:a05:6512:2804:: with SMTP id cf4mr2498975lfb.412.1643986016828; Fri, 04 Feb 2022 06:46:56 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y23sm348222lfb.2.2022.02.04.06.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 06:46:56 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 11/11] PCI: qcom: Add SM8450 PCIe support Date: Fri, 4 Feb 2022 17:46:45 +0300 Message-Id: <20220204144645.3016603-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SM8450 platform PCIe hosts do not use all the clocks (and add several additional clocks), so expand the driver to handle these requirements. PCIe0 and PCIe1 hosts use different sets of clocks, so separate entries are required. Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 55 ++++++++++++++++++++------ 1 file changed, 42 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 6034a933814d..174a650ffbbb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -160,7 +160,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[7]; + struct clk_bulk_data clks[9]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -189,7 +189,10 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; + bool has_tbu_clk; bool has_ddrss_sf_tbu_clk; + bool has_aggre0_clk; + bool has_aggre1_clk; }; struct qcom_pcie { @@ -1113,6 +1116,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + unsigned int idx; int ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); @@ -1126,18 +1130,22 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret) return ret; - res->clks[0].id = "aux"; - res->clks[1].id = "cfg"; - res->clks[2].id = "bus_master"; - res->clks[3].id = "bus_slave"; - res->clks[4].id = "slave_q2a"; - res->clks[5].id = "tbu"; - if (pcie->cfg->has_ddrss_sf_tbu_clk) { - res->clks[6].id = "ddrss_sf_tbu"; - res->num_clks = 7; - } else { - res->num_clks = 6; - } + idx = 0; + res->clks[idx++].id = "aux"; + res->clks[idx++].id = "cfg"; + res->clks[idx++].id = "bus_master"; + res->clks[idx++].id = "bus_slave"; + res->clks[idx++].id = "slave_q2a"; + if (pcie->cfg->has_tbu_clk) + res->clks[idx++].id = "tbu"; + if (pcie->cfg->has_ddrss_sf_tbu_clk) + res->clks[idx++].id = "ddrss_sf_tbu"; + if (pcie->cfg->has_aggre0_clk) + res->clks[idx++].id = "aggre0"; + if (pcie->cfg->has_aggre1_clk) + res->clks[idx++].id = "aggre1"; + + res->num_clks = idx; ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) @@ -1178,6 +1186,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) goto err_disable_clocks; } + /* Wait for reset to complete, required on SM8450 */ + usleep_range(1000, 1500); + /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); @@ -1427,15 +1438,31 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, + .has_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8250_cfg = { + .ops = &ops_1_9_0, + .has_tbu_clk = true, + .has_ddrss_sf_tbu_clk = true, +}; + +static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { + .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, + .has_aggre0_clk = true, + .has_aggre1_clk = true, +}; + +static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, + .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, + .has_tbu_clk = true, }; static const struct dw_pcie_ops dw_pcie_ops = { @@ -1541,6 +1568,8 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, + { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, + { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, { } };