From patchwork Tue Feb 8 13:42:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 540916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08DA2C433FE for ; Tue, 8 Feb 2022 13:42:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359509AbiBHNmg (ORCPT ); Tue, 8 Feb 2022 08:42:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359536AbiBHNmf (ORCPT ); Tue, 8 Feb 2022 08:42:35 -0500 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 130F5C03FED5 for ; Tue, 8 Feb 2022 05:42:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1644327754; x=1675863754; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vu8zS0jczeUtbHlyjUmW7yztnVCBsWxY9V6OA0BrJLk=; b=Adq73psBnEsOzLsnkzavpS9R7rc3bRjhtAyA/CbImZtSIPRdZYHxQItd 4zkdMLb1Yr+eN6vQAm8g9JbH+1zRCrlAhs1Q2LYChqeWrax4S1QmkogZ6 jjuC6b6jmh6yRo7Auf2P+HciUgmAY9JHFcnXstA5Ul2GPciEn3fbIPM06 M8GwmIFGoCUko3VaJ6hi60N7erjBsoi6FtzGlZBL2K2ODWwyo2ouJzmM7 Z6T5ieFlwwRPkA7TlW/naQN4TvV+1gGc4oTb/i4N9iEmiHsZRaD1ELK0T Sv5TjFnUI6G9mP5PfgEIc487GXc1go3wcQQMnn/mQj+5akIwk+UVKyDlB A==; X-IronPort-AV: E=Sophos;i="5.88,352,1635199200"; d="scan'208";a="21962444" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 08 Feb 2022 14:42:30 +0100 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Tue, 08 Feb 2022 14:42:30 +0100 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Tue, 08 Feb 2022 14:42:30 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1644327750; x=1675863750; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vu8zS0jczeUtbHlyjUmW7yztnVCBsWxY9V6OA0BrJLk=; b=CqHXgxMMEXw7BS3eDqFX09YuYvlSm9iYcho4v2MIQJl+5ygrFzdBT7jF g7ueEWnN4UlH8N1Mf2R9/0GSdj6fOZTZKfZKYEKpJIvUcQC9ZHay27KPy dBkv8ZsVca9n4juxBLcBkR+iLt2U6AFr7566JRYh+b3NOI/7WkfzBTcCW JAWyN2EsjL/6msnB4CsK2ZutHKz/VCDb9X9YwtStcnYwGZPPu2wHEFFrX C9AilUnUoMawdgc3+dJDjxwYowLSBY72SdTXSeqOtFUPKy9N0oatFBsX/ X/aBz7Oc/jJGzC55Mf9KW/zLF3H0riz2Jq5EMEOFkLFhmjY9/AqTQhCz8 A==; X-IronPort-AV: E=Sophos;i="5.88,352,1635199200"; d="scan'208";a="21962443" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 08 Feb 2022 14:42:30 +0100 Received: from steina-w.tq-net.de (unknown [10.123.49.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 47FC2280075; Tue, 8 Feb 2022 14:42:30 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Matthias Schiffer , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexander Stein Subject: [PATCH 1/5] dt-bindings: arm: fsl: add TQ Systems boards based on i.MX6UL(L) Date: Tue, 8 Feb 2022 14:42:19 +0100 Message-Id: <20220208134223.908757-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220208134223.908757-1-alexander.stein@ew.tq-group.com> References: <20220208134223.908757-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Matthias Schiffer TQMa6ULx is a SOM family using NXP i.MX6UL CPU family. TQMa6ULLx is a SOM family using NXP i.MX6ULL CPU family. Both are available as a socket type as well as an LGA type. For both variants there are the mainboards MBa6ULx and MBa6ULxL, trailing 'L' is LGA version. Finally there is the possibility to use the socket module with an LGA adapter on the MBa6ULxL. The SOM needs a mainboard, therefore we provide compatibles using this naming schema: "tq,imx6ul-" for the module and "tq,imx6ul--" for when mounted on the mainboard. The i.MX6ULL version is done similar. Signed-off-by: Matthias Schiffer Signed-off-by: Alexander Stein --- .../devicetree/bindings/arm/fsl.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b50cb9b7261c..021695a82bf8 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -613,6 +613,28 @@ properties: - const: kontron,imx6ul-n6310-som - const: fsl,imx6ul + - description: TQ-Systems TQMa6UL1 SoM on MBa6ULx board + items: + - enum: + - tq,imx6ul-tqma6ul1-mba6ulx + - const: tq,imx6ul-tqma6ul1 # MCIMX6G1 + - const: fsl,imx6ul + + - description: TQ-Systems TQMa6UL2 SoM on MBa6ULx board + items: + - enum: + - tq,imx6ul-tqma6ul2-mba6ulx + - const: tq,imx6ul-tqma6ul2 # MCIMX6G2 + - const: fsl,imx6ul + + - description: TQ-Systems TQMa6ULxL SoM on MBa6ULx[L] board + items: + - enum: + - tq,imx6ul-tqma6ul2l-mba6ulx # using LGA adapter + - tq,imx6ul-tqma6ul2l-mba6ulxl + - const: tq,imx6ul-tqma6ul2l # MCIMX6G2, LGA SoM variant + - const: fsl,imx6ul + - description: i.MX6ULL based Boards items: - enum: @@ -667,6 +689,21 @@ properties: - const: kontron,imx6ull-n6411-som - const: fsl,imx6ull + - description: TQ Systems TQMa6ULLx SoM on MBa6ULx board + items: + - enum: + - tq,imx6ull-tqma6ull2-mba6ulx + - const: tq,imx6ull-tqma6ull2 # MCIMX6Y2 + - const: fsl,imx6ull + + - description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board + items: + - enum: + - tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter + - tq,imx6ull-tqma6ull2l-mba6ulxl + - const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant + - const: fsl,imx6ull + - description: i.MX6ULZ based Boards items: - enum: From patchwork Tue Feb 8 13:42:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 540914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0AECC433F5 for ; Tue, 8 Feb 2022 13:42:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359726AbiBHNmk (ORCPT ); Tue, 8 Feb 2022 08:42:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359867AbiBHNmj (ORCPT ); Tue, 8 Feb 2022 08:42:39 -0500 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FF08C03FECE for ; Tue, 8 Feb 2022 05:42:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1644327757; x=1675863757; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Tiycpxswt/F4AZWVmFikdAU78/ZExPYXtROJms15M84=; b=jn9qAJSWYVODdJ2fTVf8PPAbvO2ex0jXdyNvIrqXryjLnrPaVkOur+U6 FxqQuoDYFBiFKzGIIBjI8LeQy2/b3BySTcartXSHGPaR7R4EVl+zoed+D mn5EjcJpoLWvT7lMH67iQ/bjCMTdkiqatC+buT0hHGyWikY/U3G7RDxoE UWq5MEic1gcuGJrzCTQshhG8clk65hh9uD+t0+5TqDis2l6FGjq3bJz08 WsJFN60ZrOKdx/t24hM340bGC4gSVLfAOh46zjQVXqGmI/hyTFS+f68HF 3EpyshbecQsdC/Cmk8LiBlJ5+mc9DROjzhYO/cnSsIYdqSY/jPpEKzNPh g==; X-IronPort-AV: E=Sophos;i="5.88,352,1635199200"; d="scan'208";a="21962452" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 08 Feb 2022 14:42:31 +0100 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Tue, 08 Feb 2022 14:42:31 +0100 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Tue, 08 Feb 2022 14:42:31 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1644327751; x=1675863751; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Tiycpxswt/F4AZWVmFikdAU78/ZExPYXtROJms15M84=; b=gewaPIWhEIHN7D5s9Zul9U4v0rlVR+1BrCwjbqICllIXKBRzlBoO+/a8 g6OH67rjGJBw2Hc8eA4lJ7vIbNOsDPsIoMlUVWozbWlpiOZM0mD4oDA5F VjSQDzkyVZamluP/7zIzz2d3aEYoOmISBriNz6DSg1aiAbeYdZYO5somz 1okWQcWdYYhCJ8Tlx8h6/2N5kmzH5ukd9+hPUPFVV7dG0nIbHTIXL7vJn EUFf3Q6ro7Wj7nJ7Yoh0bfW59xsgTuasiyYWBgg4etP6Tvz5SBp81P7Mn 0oWq/pjzSswaMGOHvGwZ7qejVrTXkwoxSq1IGr6V149Kk7hwrmCsmn1EP A==; X-IronPort-AV: E=Sophos;i="5.88,352,1635199200"; d="scan'208";a="21962451" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 08 Feb 2022 14:42:31 +0100 Received: from steina-w.tq-net.de (unknown [10.123.49.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 214F9280065; Tue, 8 Feb 2022 14:42:31 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/5] ARM: dts: imx6ull: add TQ-Systems MBa6ULLxL device trees Date: Tue, 8 Feb 2022 14:42:23 +0100 Message-Id: <20220208134223.908757-6-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220208134223.908757-1-alexander.stein@ew.tq-group.com> References: <20220208134223.908757-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device trees for the MBa6ULx mainboard with TQMa6ULLxL SoMs. Signed-off-by: Alexander Stein --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi | 76 +++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3a6eccb6371a..9bf89273ae71 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -710,6 +710,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ + imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts new file mode 100644 index 000000000000..33437aae9822 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi new file mode 100644 index 000000000000..8e4d5cd18614 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM"; + compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +};