From patchwork Thu Jun 1 09:43:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 100863 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp718631qge; Thu, 1 Jun 2017 02:44:22 -0700 (PDT) X-Received: by 10.55.56.147 with SMTP id f141mr472371qka.191.1496310261551; Thu, 01 Jun 2017 02:44:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496310260; cv=none; d=google.com; s=arc-20160816; b=IcSs0gvNPmWU0s89GLYyoA8cHeh0R5h66PA7nlol7QjehtI2sp84yVrBaJfQEJXl05 GklWq84xKRrzBK85lyy6wMbByZBiapUGQGkr8R2wevWStr9GgFmtTDHuBnALEzFvPZmc n0ClgQ38rIm82dRKqsvdhjqNPMH9HGjdQqbuA8U/Wm5VBzEvOP5VEntbbsWfjv8VGMDj X00eJj3YOkYjX49MRpxZaMvqQKCjSAoK7FHN+kDf+Iifi+NA7a5FY/J6Tgu98ZZfNMRD oZ0jiGct/9ODtFlkUzD0aQC7cf7QpXJtPYV00gHyteDbxUV95tcuFZfvebqtnAiBLE7K AJUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:delivered-to:arc-authentication-results; bh=O/P5HFWn0PDpkb3d3TyblLkUWclz0+6I/uLymNfm98w=; b=nEYtneJ2Q4hqWO7F6KBqn0LMnCqZHZzMRJNWWEW4AHUjIjzzl33rKqtydu9Jj/9v1i 2hbhkpn3VFTblOfAC7Ee+BuO4QwQ+1CDobHi0jRzBZ91AM4dEs5jgx7z/Ww4BzjXXMU+ rGaKMTIsaxR9mJVQOyM/mJTrstlNzAdBKhbm70Og0pdp3BlHtQuR3FPv7NezNf2ul5+O j0x3xPqueb+GNzt2VDxndTnNWtUJr/oBIHagUmVMejhTd1l/D4rZkv1mC/boZzR7/P+g +xOv+bT9bf4BsqR1Gxpf80aJUWQODZ2CRzH1AapFKVMRU7BsjFKrOlphnmxFU5lB7gvk kvew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id r62si17783954qkr.271.2017.06.01.02.44.20; Thu, 01 Jun 2017 02:44:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 95F61609BF; Thu, 1 Jun 2017 09:44:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_SORBS_SPAM, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id CD21D609F0; Thu, 1 Jun 2017 09:44:07 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 380BE609AA; Thu, 1 Jun 2017 09:44:04 +0000 (UTC) Received: from mail-wm0-f45.google.com (mail-wm0-f45.google.com [74.125.82.45]) by lists.linaro.org (Postfix) with ESMTPS id 24D4E609A7 for ; Thu, 1 Jun 2017 09:44:03 +0000 (UTC) Received: by mail-wm0-f45.google.com with SMTP id b84so151096191wmh.0 for ; Thu, 01 Jun 2017 02:44:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=irPK59e1gsdAfH42LPAON0HjwClY99x1jVIyN12m8Hw=; b=no+LY3T07GwhhmhQ8qAx88E+Xt6qG8/B3v/ncGocT3MLmW6VJN8jVjoUl8dqyYMbUh TUVAY777s0pAkSkodOehti74gUs3Al2+mR1zDzxy/m8SWaBq1pmnUUHBrTM4/RR3TsMY SJfJcCQPLPIr/u3Dsz6CIfNfWgNn9QTqd3NB0+vQDKf/IoK5ebCNi7H17Bi2b1MJqxp1 cLH4vCFHD6Sn5EsFwSNs741JVtCk72O+7MxqEpJ5OsNcLkfqwIGeWWmo3USaY3pBMFsU LjQH1w5ULgolj0uUqhAF56LFp6BCRDwXEI4KgoQsULNepOpGSVYG8XjfQNq9YiixGOt8 tMWQ== X-Gm-Message-State: AODbwcD4JmeyfIwpx7YeN+Sl09Wyuk7gn9ZFmN0P759ZeMAJtwOvCZZP 0O8Bk4siRnA0b8CO74vK4XeL X-Received: by 10.28.145.12 with SMTP id t12mr7983946wmd.46.1496310242092; Thu, 01 Jun 2017 02:44:02 -0700 (PDT) Received: from localhost.localdomain ([196.71.200.86]) by smtp.gmail.com with ESMTPSA id 64sm23257679wmn.20.2017.06.01.02.44.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Jun 2017 02:44:01 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Thu, 1 Jun 2017 09:43:48 +0000 Message-Id: <20170601094353.16235-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170601094353.16235-1-ard.biesheuvel@linaro.org> References: <20170601094353.16235-1-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH 1/6] Platforms/AMD/Styx: remove unused PCD 'PcdStyxFdt' X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Remove the PCD 'PcdStyxFdt' which is no longer used now that we have switched to the generic DtPlatformDxe driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/AmdStyx.dec | 3 --- Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 1 - 2 files changed, 4 deletions(-) diff --git a/Platforms/AMD/Styx/AmdStyx.dec b/Platforms/AMD/Styx/AmdStyx.dec index 6624f8ca74a7..8d4b4927c6b1 100644 --- a/Platforms/AMD/Styx/AmdStyx.dec +++ b/Platforms/AMD/Styx/AmdStyx.dec @@ -46,9 +46,6 @@ # CPUID Register gAmdStyxTokenSpaceGuid.PcdCpuIdRegister|0xE0000010|UINT32|0x00000200 - # FDT support - gAmdStyxTokenSpaceGuid.PcdStyxFdt|{ 0xe4, 0x08, 0x0d, 0x04, 0x9a, 0x47, 0x4b, 0x42, 0x8c, 0x42, 0x36, 0x64, 0xdf, 0x79, 0x3f, 0x4b }|VOID*|0x00010000 - # Synopsys SATA Controller gAmdStyxTokenSpaceGuid.PcdSata0CtrlAxiSlvPort|0xE0300000|UINT32|0x00020000 gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8|UINT8|0x00020001 diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index f5ba5f1d1335..8bb6e9fa41cb 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -41,7 +41,6 @@ UefiBootServicesTableLib [Pcd] - gAmdStyxTokenSpaceGuid.PcdStyxFdt gAmdStyxTokenSpaceGuid.PcdSocCpuId gAmdStyxTokenSpaceGuid.PcdEthMacA gAmdStyxTokenSpaceGuid.PcdEthMacB From patchwork Thu Jun 1 09:43:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 100864 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp718724qge; Thu, 1 Jun 2017 02:44:39 -0700 (PDT) X-Received: by 10.55.69.72 with SMTP id s69mr513529qka.175.1496310279634; Thu, 01 Jun 2017 02:44:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496310279; cv=none; d=google.com; s=arc-20160816; b=BKy1v7iraCUUBckh9UA6n1H3AVyxz8ozjebVdRXBPzX6YZ7el9yB5jw5IpIhUWFcrY DrjRwe6b2YHE1AYggE/6jIktUmFNjPeWyDmlMTheMBeJ3lql+Fs62VI20/S7VRYgAPs0 hO2WQEiZCl3SryhjHqvpkAB8fHahbxJm1+Eu/pfVmvdkBsrGOaKc1+QIQ/VNqP6zSMtH OMebhZFstHRpF48yJ7/VHgV4sZJybQJNE8E+qIhEZrOOmJVW9rQEiZitD1tUoZp4WBr/ +FKsxDh+boIwIRWbrCX7ns8Vv85ekgMYrYtkntTKwfIWVMQdtDN1GHXj4hAM31FgPMdn w0pA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:delivered-to:arc-authentication-results; bh=McuLjM4PE1dIThRhcg0bBDEDdbiJq8G1jglfq2b1r4c=; b=q+Ddbld09nUUdlvaZfS9MmuEiLVzeqIe4cOWnv+Vf9FBkj9T6RHpNn9d84Ed6gcIAb P2ZxU8RS9TH8SwqTgdaq0KeWQRrJEHiTqnzn+cuxJJxrMzcrxIQeQjglv8lofoeIpwOs gjrbgzNxmYbFtPY2ueFgGRRxZsJ73tWpeEzgAIlq+qenzvqDKvXryBio3JxU0aGs/8rc YP5E9q4jTR1FznLdtcXhVhFRQAgmf/lh+KqPUeCmQmFmcEHwT2EXY+6XN+w7OTfuMRDH Dv54J/ytC8wrivTVWj2ypvovw8QVxQoUYmWOouMMMcQ5n3gXQqIGj0Z6qUX8golEMj4I 5YjQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id b139si19367875qka.326.2017.06.01.02.44.39; Thu, 01 Jun 2017 02:44:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 38D8C609AA; Thu, 1 Jun 2017 09:44:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 1C33E60A3D; Thu, 1 Jun 2017 09:44:25 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id A477A60A3D; Thu, 1 Jun 2017 09:44:19 +0000 (UTC) Received: from mail-wm0-f41.google.com (mail-wm0-f41.google.com [74.125.82.41]) by lists.linaro.org (Postfix) with ESMTPS id 003AE609B3 for ; Thu, 1 Jun 2017 09:44:05 +0000 (UTC) Received: by mail-wm0-f41.google.com with SMTP id 123so2634252wmg.1 for ; Thu, 01 Jun 2017 02:44:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2/VH6lWn75gmjlphUSIeVklzYb/knmKRBVGB5gyClgM=; b=odDhD860xlTBkWJ6WOAz2cT9iUol0aTCog9WuSywwTgSpWnUrfqgln+U3xMi0GqiLF +zouK7/Y3wQdauG7dTIeFLEsdJte1wtomxGVv38lB6vfp/C7Y50M08NHVIVKwup9o4J0 N2UsazHZaBA4rR3Tn9B3Kmj94vp+L1M5yh1uiERbBIDpgrsFg79SIAd9U/zrVQm/J1r8 GBQ2JFDCfZHgWctSc8AalqLfH0kj8RlPiakffWDJP3ldl62U/LDkgNxr3g26+5MCy0bZ hyrreGtlL9mXEsIt5w8aQdDJlBL6MnsrfiysgsLXXxz44PfKk/l160iZCFc8KiAYoEv+ Ha6Q== X-Gm-Message-State: AODbwcBpRi87fi7Qbk5Wc1KqxeDywSeDvzdAcYz9BqXZevCO0IvHTj5i crBOLilXMjsnPg4Q0JDnAUkT X-Received: by 10.223.139.25 with SMTP id n25mr535959wra.17.1496310243905; Thu, 01 Jun 2017 02:44:03 -0700 (PDT) Received: from localhost.localdomain ([196.71.200.86]) by smtp.gmail.com with ESMTPSA id 64sm23257679wmn.20.2017.06.01.02.44.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Jun 2017 02:44:03 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Thu, 1 Jun 2017 09:43:49 +0000 Message-Id: <20170601094353.16235-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170601094353.16235-1-ard.biesheuvel@linaro.org> References: <20170601094353.16235-1-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH 2/6] Platforms/AMD/Overdrive: add dynamic PCD to control SMMU availibility X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Introduce a PCD that can be linked to a EFI variable 'StyxEnableSmmus', controlling whether the SMMU descriptions will be exposed to the OS via the DT or ACPI tables. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/AmdStyx.dec | 7 +++++++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 4 +++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/Platforms/AMD/Styx/AmdStyx.dec b/Platforms/AMD/Styx/AmdStyx.dec index 8d4b4927c6b1..ddd5bf4c3609 100644 --- a/Platforms/AMD/Styx/AmdStyx.dec +++ b/Platforms/AMD/Styx/AmdStyx.dec @@ -35,6 +35,10 @@ gAmdStyxTokenSpaceGuid = { 0x220d9653, 0x4a0e, 0x40bc, { 0xb3, 0x65, 0x2f, 0xbb, 0xa2, 0xd9, 0x03, 0x45 } } gAmdStyxMpCoreInfoGuid = { 0x68efeabd, 0xcb77, 0x4aa5, { 0xbf, 0x0c, 0xa3, 0x31, 0xfc, 0xcf, 0x76, 0x66 } } + # 2a5e4deb-4445-4fb6-8b14-366b8e779b69 + # EFI variable scope for Styx + gAmdStyxVariableGuid = { 0x2a5e4deb, 0x4445, 0x4fb6, { 0x8b, 0x14, 0x36, 0x6b, 0x8e, 0x77, 0x9b, 0x69 } } + [PcdsDynamic] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|1|UINT32|0x00000100 gAmdStyxTokenSpaceGuid.PcdSocCpuId|1|UINT32|0x00000101 @@ -108,3 +112,6 @@ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase|0|UINT64|0x000c0000 # block size to use when invoking the ISCP FV methods gAmdStyxTokenSpaceGuid.PcdFlashNvStorageBlockSize|0x1000|UINT32|0x000c0001 + +[PcdsFixedAtBuild,PcdsDynamic] + gAmdStyxTokenSpaceGuid.PcdEnableSmmus|FALSE|BOOLEAN|0xe0000000 diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 65d229884aa7..b4893ca34587 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -515,9 +515,11 @@ DEFINE DO_KCS = 1 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0 -[PcdsDynamicExHii.common.DEFAULT] +[PcdsDynamicHii] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 + gAmdStyxTokenSpaceGuid.PcdEnableSmmus|L"StyxEnableSmmus"|gAmdStyxVariableGuid|0x0|FALSE + ################################################################################ # # Components Section - list of all EDK II Modules needed by this Platform From patchwork Thu Jun 1 09:43:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 100865 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp718829qge; Thu, 1 Jun 2017 02:45:01 -0700 (PDT) X-Received: by 10.55.184.5 with SMTP id i5mr552970qkf.141.1496310301466; Thu, 01 Jun 2017 02:45:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496310301; cv=none; d=google.com; s=arc-20160816; b=QWFRX31n/3w8zHRP0mN2L0WaqUt6ac8kCZyuYBOz3SLm9IN77olOjrpV8XV9Xkma8G dtAk0+woNOOLBHLCGVrMcF4rOXrNWfosH5HRQjAMX1lbjldk+IFRJw/vC956F74qDCw5 vrzW6fysQ+B2wmDgyB6/Op5YHA0+Fsm5maCr5NqUaHJD5wUQxAWZZzu0F1I0ZVX5tf5q xR3xXRi/QHDddja1EV+M28d7rNCIt7EcvKFXjSz+FH2naw+Bttx7ITN0/qWh8nCFHb63 Ub2kvyWYaqwsqmjrrlfgyTkSJ+hAi2u9z/CHYqFbsF/b2HjiHlDMxag+PD//Coye6WkS U+gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:delivered-to:arc-authentication-results; bh=sPdFd+BVlfekH6djbodFIdtbNt8WB6KJPc4z5Utdmhw=; b=zlIUeqXEa7UpE7ZhBh0+v7S8tksQJR4xtcyJ2g+cBzIcWhoZQaSL7Bw8Y5tzd3U1lC zwqt4YoBkdLk1RYs1t9wiet6GOf9wzf5rhod3UHsZTSex9CmN4Khpdb7DjeX7Pysv6Gv xNgMw7Gyw4g+saCH6LSxIEA2LIiUGorChxHyzCVeKpy8FzL2/NWpB4GFGhe7y0zAIAWX JCCp2a30fFUmzbinZBhWizRsREO529sqxnj1+wtAKdRaGm7NuguZEuK0n1bI+1jVIGn1 4jEDeCwSqG6lptp7FDbh+0O11+nq7DyoqoJpTqKynXjC32DCjyqIGcYOiXUvkygaMgUg pO/Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id i58si19049382qti.57.2017.06.01.02.45.01; Thu, 01 Jun 2017 02:45:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 1F70360B2D; Thu, 1 Jun 2017 09:45:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_SORBS_SPAM, UPPERCASE_50_75, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 4F4D5609B3; Thu, 1 Jun 2017 09:44:40 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id ABFC5609B1; Thu, 1 Jun 2017 09:44:32 +0000 (UTC) Received: from mail-wm0-f45.google.com (mail-wm0-f45.google.com [74.125.82.45]) by lists.linaro.org (Postfix) with ESMTPS id D365360A0F for ; Thu, 1 Jun 2017 09:44:07 +0000 (UTC) Received: by mail-wm0-f45.google.com with SMTP id 7so150492806wmo.1 for ; Thu, 01 Jun 2017 02:44:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j6cptmE33ps310mIS4cGRzokk4rQBVYbJbxi27e7esE=; b=GwDe2bXe6vT98sGrePrjDFDwFE+y5guD76lQfzISIaRSDg9N+/i4g0M0rAzUFH0XOu j7f3gOy7BIaFE6x8Nbfo0QLYLwS9MKEO5EoiuZoCHcp/Zi5eBMJJVkal+DKXA3Adg6KD 56N7KF76MbYtLx7q5NZZW9X7Apz3+GF4IOAd7Wcv6dGy0xPo0V7oslNchNWmn5QJRCZH 4gCCywGZOdnZ63/JfhAlcIhIRj/Vrh3lNCXKw5oSWBgz6hgNps+dTk02LzlwCs08bSDd xkbjk8D7nhDhjh52M2+iTlh3cfWltJ4DPIuDZChWZmzO3SELWKBg4MCpiuYF3408xFh2 Bx0w== X-Gm-Message-State: AODbwcBZ2Wr2dYxjIM9NLjv6lSvbTZ5S+Q3pbvrY4WTecxfEf4oG8E9H TvrYVRqjtR9JzepEjMZNqepx X-Received: by 10.28.103.214 with SMTP id b205mr8008120wmc.64.1496310246398; Thu, 01 Jun 2017 02:44:06 -0700 (PDT) Received: from localhost.localdomain ([196.71.200.86]) by smtp.gmail.com with ESMTPSA id 64sm23257679wmn.20.2017.06.01.02.44.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Jun 2017 02:44:05 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Thu, 1 Jun 2017 09:43:50 +0000 Message-Id: <20170601094353.16235-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170601094353.16235-1-ard.biesheuvel@linaro.org> References: <20170601094353.16235-1-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH 3/6] Platforms/AMD/Styx: enable SMMUs in the ACPI IORT table X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space. This is not a problem for the onboard devices, but it would be useful if we could support arbitrary PCIe plug-in cards, even if they are only 32-bit DMA capable. Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table. While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/AcpiTables/AcpiTables.inf | 1 + Platforms/AMD/Styx/AcpiTables/Iort.c | 375 ++++++++++++++++++++ Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h | 1 + Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 6 +- Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 6 +- 5 files changed, 387 insertions(+), 2 deletions(-) diff --git a/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf index 12e0444009ef..3615d7fc0279 100644 --- a/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf @@ -37,6 +37,7 @@ Mcfg.c Csrt.c Dsdt.c + Iort.c [Packages] ArmPkg/ArmPkg.dec diff --git a/Platforms/AMD/Styx/AcpiTables/Iort.c b/Platforms/AMD/Styx/AcpiTables/Iort.c new file mode 100644 index 000000000000..80872773ba7d --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Iort.c @@ -0,0 +1,375 @@ +/** @file + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#define STYX_PCIE_SMMU_BASE 0xE0A00000 +#define STYX_PCIE_SMMU_SIZE 0x10000 +#define STYX_PCIE_SMMU_INTERRUPT 0x16d + +#define STYX_ETH0_SMMU_BASE 0xE0600000 +#define STYX_ETH0_SMMU_SIZE 0x10000 +#define STYX_ETH0_SMMU_INTERRUPT 0x170 + +#define STYX_ETH1_SMMU_BASE 0xE0800000 +#define STYX_ETH1_SMMU_SIZE 0x10000 +#define STYX_ETH1_SMMU_INTERRUPT 0x16f + +#define STYX_SATA0_SMMU_BASE 0xE0200000 +#define STYX_SATA0_SMMU_SIZE 0x10000 +#define STYX_SATA0_SMMU_INTERRUPT 0x16c + +#define STYX_SATA1_SMMU_BASE 0xE0C00000 +#define STYX_SATA1_SMMU_SIZE 0x10000 +#define STYX_SATA1_SMMU_INTERRUPT 0x16b + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[1]; +} STYX_SMMU_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1]; +} STYX_RC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; + CONST CHAR8 Name[11]; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[32]; +} STYX_NC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + STYX_SMMU_NODE PciSmmuNode; + STYX_RC_NODE PciRcNode; + +#if DO_XGBE + STYX_SMMU_NODE Eth0SmmuNode; + STYX_NC_NODE Eth0NamedNode; + STYX_SMMU_NODE Eth1SmmuNode; + STYX_NC_NODE Eth1NamedNode; +#endif + + STYX_SMMU_NODE Sata0SmmuNode; + STYX_NC_NODE Sata0NamedNode; + STYX_SMMU_NODE Sata1SmmuNode; + STYX_NC_NODE Sata1NamedNode; +} STYX_IO_REMAPPING_STRUCTURE; + +#define __STYX_SMMU_NODE(Base, Size, Irq) \ + { \ + { \ + EFI_ACPI_IORT_TYPE_SMMUv1v2, \ + sizeof(STYX_SMMU_NODE), \ + 0x0, \ + 0x0, \ + 0x0, \ + 0x0, \ + }, \ + Base, \ + Size, \ + EFI_ACPI_IORT_SMMUv1v2_MODEL_v1, \ + EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, \ + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \ + SMMU_NSgIrpt), \ + 0x1, \ + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \ + 0x0, \ + 0x0, \ + Irq, \ + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ + 0x0, \ + 0x0, \ + }, { \ + { \ + Irq, \ + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ + }, \ + } + +#define __STYX_ID_MAPPING(In, Num, Out, Ref, Flags) \ + { \ + In, \ + Num, \ + Out, \ + FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \ + Flags \ + } + +#define __STYX_ID_MAPPING_SINGLE(Out, Ref) \ + { \ + 0x0, \ + 0x0, \ + Out, \ + FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \ + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE \ + } + +#define __STYX_NAMED_COMPONENT_NODE(Name) \ + { \ + { \ + EFI_ACPI_IORT_TYPE_NAMED_COMP, \ + sizeof(STYX_NC_NODE), \ + 0x0, \ + 0x0, \ + 0x20, \ + FIELD_OFFSET(STYX_NC_NODE, RcIdMapping), \ + }, \ + 0x0, \ + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, \ + 0x0, \ + 0x0, \ + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | \ + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, \ + 40, \ + }, \ + Name + +STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = { + { + AMD_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + STYX_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION), +#if DO_XGBE + 10, // NumNodes +#else + 6, // NumNodes +#endif + sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, { + // PciSmmuNode + __STYX_SMMU_NODE(STYX_PCIE_SMMU_BASE, + STYX_PCIE_SMMU_SIZE, + STYX_PCIE_SMMU_INTERRUPT) + }, { + // PciRcNode + { + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof(STYX_RC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x1, // NumIdMappings + FIELD_OFFSET(STYX_RC_NODE, RcIdMapping), // IdReference + }, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent + 0x0, // AllocationHints + 0x0, // Reserved + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute + 0x0, // PciSegmentNumber + }, { + __STYX_ID_MAPPING(0x0, 0xffff, 0x0, PciSmmuNode, 0x0), + } +#if DO_XGBE + }, { + // Eth0SmmuNode + __STYX_SMMU_NODE(STYX_ETH0_SMMU_BASE, + STYX_ETH0_SMMU_SIZE, + STYX_ETH0_SMMU_INTERRUPT) + }, { + // Eth0NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH0"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Eth0SmmuNode), + } + }, { + // Eth1SmmuNode + __STYX_SMMU_NODE(STYX_ETH1_SMMU_BASE, + STYX_ETH1_SMMU_SIZE, + STYX_ETH1_SMMU_INTERRUPT) + }, { + // Eth1NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH1"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Eth1SmmuNode), + } +#endif + }, { + // Sata0SmmuNode + __STYX_SMMU_NODE(STYX_SATA0_SMMU_BASE, + STYX_SATA0_SMMU_SIZE, + STYX_SATA0_SMMU_INTERRUPT) + }, { + // Sata0NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC0"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Sata0SmmuNode), + } + }, { + // Sata1SmmuNode + __STYX_SMMU_NODE(STYX_SATA1_SMMU_BASE, + STYX_SATA1_SMMU_SIZE, + STYX_SATA1_SMMU_INTERRUPT) + }, { + // Sata1NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC1"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Sata1SmmuNode), + } + } +}; + +#pragma pack() + +#define STYX_SOC_VERSION_MASK 0xFFF +#define STYX_SOC_VERSION_A0 0x000 +#define STYX_SOC_VERSION_B0 0x010 +#define STYX_SOC_VERSION_B1 0x011 + +EFI_ACPI_DESCRIPTION_HEADER * +IortHeader ( + VOID + ) +{ + if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) { + // + // Silicon revisions prior to B1 have only one SATA port, + // so omit the nodes of the second port in this case. + // + AcpiIort.Iort.NumNodes -= 2; + } + return (EFI_ACPI_DESCRIPTION_HEADER *)&AcpiIort.Iort.Header; +} diff --git a/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h index 698a5d3f90f8..9438b8b0c27e 100644 --- a/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h +++ b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h @@ -27,6 +27,7 @@ EFI_ACPI_DESCRIPTION_HEADER *McfgHeader (void); EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void); EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void); EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void); +EFI_ACPI_DESCRIPTION_HEADER *IortHeader (void); #define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'} #define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ') diff --git a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 1bad597a8eaa..15b38bbf89c6 100644 --- a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -23,8 +23,9 @@ #include #include -#include #include +#include +#include #define MAX_ACPI_TABLES 12 @@ -65,6 +66,9 @@ AcpiPlatformEntryPoint ( AcpiTableList[TableIndex++] = SpcrHeader(); AcpiTableList[TableIndex++] = McfgHeader(); AcpiTableList[TableIndex++] = CsrtHeader(); + if (PcdGetBool (PcdEnableSmmus)) { + AcpiTableList[TableIndex++] = IortHeader(); + } AcpiTableList[TableIndex++] = NULL; DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__)); diff --git a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 9f4c3eaf582d..23f1cb60903a 100644 --- a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -37,10 +37,14 @@ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec [LibraryClasses] + AmdStyxAcpiLib DebugLib + PcdLib UefiBootServicesTableLib UefiDriverEntryPoint - AmdStyxAcpiLib + +[Pcd] + gAmdStyxTokenSpaceGuid.PcdEnableSmmus [Protocols] gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED From patchwork Thu Jun 1 09:43:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space. This is not a problem for the onboard devices, but it would be useful if we could support arbitrary PCIe plug-in cards, even if they are only 32-bit DMA capable. Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table. While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 51 ++++++++++++++ Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 2 + Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 8293 -> 9357 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 72 +++++++++++++++++++- 4 files changed, 123 insertions(+), 2 deletions(-) diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index b18caf19985b..093db6517c1a 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -189,6 +190,46 @@ SetMacAddress ( #endif +STATIC +VOID +DisableSmmu ( + IN VOID *Fdt, + IN CONST CHAR8 *IommuPropName, + IN CONST CHAR8 *SmmuNodeName, + IN CONST CHAR8 *DeviceNodeName + ) +{ + INT32 Node; + INT32 Error; + + Node = fdt_path_offset (Fdt, DeviceNodeName); + if (Node <= 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n", + __FUNCTION__, DeviceNodeName, fdt_strerror (Node))); + return; + } + + Error = fdt_delprop (Fdt, Node, IommuPropName); + if (Error != 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to delete property %a: %a\n", + __FUNCTION__, IommuPropName, fdt_strerror (Error))); + return; + } + + Node = fdt_path_offset (Fdt, SmmuNodeName); + if (Node <= 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n", + __FUNCTION__, SmmuNodeName, fdt_strerror (Node))); + return; + } + + Error = fdt_del_node (Fdt, Node); + if (Error != 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to delete node %a: %a\n", + __FUNCTION__, SmmuNodeName, fdt_strerror (Error))); + } +} + #define STYX_SOC_VERSION_MASK 0xFFF #define STYX_SOC_VERSION_A0 0x000 #define STYX_SOC_VERSION_B0 0x010 @@ -216,6 +257,16 @@ SetSocIdStatus ( #else SetDeviceStatus (Fdt, "kcs@e0010000", FALSE); #endif + + if (!PcdGetBool (PcdEnableSmmus)) { + DisableSmmu (Fdt, "iommu-map", "/smb/smmu@e0a00000", "/smb/pcie@f0000000"); + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0200000", "/smb/sata@e0300000"); + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/sata@e0d00000"); +#if DO_XGBE + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0600000", "/smb/xgmac@e0700000"); + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0800000", "/smb/xgmac@e0900000"); +#endif + } } STATIC diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index 8bb6e9fa41cb..fcf2f058fbdf 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -37,6 +37,7 @@ DxeServicesLib FdtLib MemoryAllocationLib + PcdLib PrintLib UefiBootServicesTableLib @@ -44,6 +45,7 @@ gAmdStyxTokenSpaceGuid.PcdSocCpuId gAmdStyxTokenSpaceGuid.PcdEthMacA gAmdStyxTokenSpaceGuid.PcdEthMacB + gAmdStyxTokenSpaceGuid.PcdEnableSmmus gArmTokenSpaceGuid.PcdSystemMemoryBase [FixedPcd] diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb index d380ea8714b85ec14f593b3795529c952e988df3..7ec1f63aff7805a3db7efc7a9b6e3c04f3c856cd 100644 GIT binary patch delta 2262 zcmcImOK1~O6rJ~?Z4;9;X;PDZG-^w!+G;FTi;6_STG84f{&qHwv4$pXX!=nUQt-bh zh(k6I)&frHm8YDF2%NCmn{Z95#=+#;Q{1^D*oct&T*#sZ$i$-Gfq#(9@%F^XG zfOkR6XB$2k6r#GqWl}h)y|DA2K_~*IHogRa|FaHdg|zkHHtNSvdqjy9JrlN(vYUPS}YwmQS65Ulhr_R z)D*MwK%RUyPrgDI7PN`GH0t!zmjwawjKZRVLeA=GU~h6&Qp#C^mL*&pji8m;06$f@ zJktiP$_*%`7p{d?&^OmiRU+>7M*313b}R3f?&-XLx=*`uPPlkOXNm{6@nDJf)|Z+? z`qyBI$&?<48C^qXzgxaIQmT``sM@na%K6mpDVH)hlJI;M;s+fpxsXZ_9SR2n;x)AdcbnOp=|iyfe^hu>wpQ)ux;gJ> z2SWzUZa>@EQ|+f(qZ=8upJ)*jp#1&hYej8?v7eC5o6o$qo8}CDh%jr#fw(d1rjAY7&Z^%7bP^Pzri!g5 zj(d3+9y}a*^w@9$E`isx#4Z zIGU)BclX75d;3#;X{{>WgMSiwERjfSN0QNcz2{i0H`d*!>4_e_E3Fy!G;Lb^)^55c Pqp1-`XuY64OMHI-={_7_ delta 1263 zcmcIj-%C?*6hGfv&8fTlVRO#SAInMjYiMF31Q{k`52X=QPujY>xwXw*+{!@9J@ppE z4*da{Jr$^}pohTMd@`Xx=w&@fM*0|xi0quZAB~~VO9#%q-*Z0aoX_{1@Av!Y!uGkg z5AyFl0FMd)0|1TJ>EA|bBejx}9FfWI!A`q-_58E}+l{wvo8*=lVw_|P-x*sZ*v5=; z>HtuyoE4k6Q#nW9K-EGmr*mpSnQRxcRd*%GqE_wIOBBFL22<5;T&upqxZUJ!FD;86*ymwKRCndPwk!H70MBjA0SGY_sh=%Cx40xMv;^4{?nRk_FPj(AIIs*3l$B z0_^Kp{!@_)5gAJRn(nFjF2oi#*dJrC_CfB_I8%-hN&LW3N3SIIao%x~{Y#E+Lpr2I zLx7i!cHDFLI>bKPlVK&EubrosEM$uu51+i`Ob^%HlDNvtdbG8cM4Jfh#c@|%{SbNi z7PIE}2#j9EB%$0bS7ogtWhO@FaK%+8p5S}erCj+DoN!(bN3XG_n?Q#=yjS8$Z@x+YkkNQFZpQ1)0afl}Zu{#N$=1&A6 KswRT50Q>; }; + sata0_smmu: smmu@e0200000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0200000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 332 4>, + <0 332 4>; + #iommu-cells = <2>; + dma-coherent; + }; + + sata1_smmu: smmu@e0c00000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0c00000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 331 4>, + <0 331 4>; + #iommu-cells = <2>; + dma-coherent; + }; + sata@e0300000 { compatible = "snps,dwc-ahci"; reg = <0x0 0xe0300000 0x0 0xf0000>; interrupts = <0x0 0x163 0x4>; clocks = <0x2>; dma-coherent; + iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ }; sata@e0d00000 { @@ -137,6 +164,7 @@ interrupts = <0x0 0x162 0x4>; clocks = <0x2>; dma-coherent; + iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ }; i2c@e1000000 { @@ -257,6 +285,7 @@ #address-cells = <0x3>; #size-cells = <0x2>; #interrupt-cells = <0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; device_type = "pci"; bus-range = <0x0 0x7f>; msi-parent = <0x4>; @@ -283,6 +312,19 @@ <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ }; + pcie_smmu: smmu@e0a00000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0a00000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 333 4>, + <0 333 4>; + #iommu-cells = <1>; + dma-coherent; + }; + ccn@0xe8000000 { compatible = "arm,ccn-504"; reg = <0x0 0xe8000000 0x0 0x1000000>; @@ -382,6 +424,32 @@ phandle = <0xa>; }; + xgmac0_smmu: smmu@e0600000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0600000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 336 4>, + <0 336 4>; + #iommu-cells = <2>; + dma-coherent; + }; + + xgmac1_smmu: smmu@e0800000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0800000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 335 4>, + <0 335 4>; + #iommu-cells = <2>; + dma-coherent; + }; + xgmac@e0700000 { status = "disabled"; compatible = "amd,xgbe-seattle-v1a"; @@ -397,8 +465,8 @@ clock-names = "dma_clk", "ptp_clk"; phy-handle = <0x9>; phy-mode = "xgmii"; - #stream-id-cells = <0x18>; dma-coherent; + iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ linux,phandle = <0xb>; phandle = <0xb>; }; @@ -418,8 +486,8 @@ clock-names = "dma_clk", "ptp_clk"; phy-handle = <0xa>; phy-mode = "xgmii"; - #stream-id-cells = <0x18>; dma-coherent; + iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ linux,phandle = <0xc>; phandle = <0xc>; }; From patchwork Thu Jun 1 09:43:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 100866 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp719005qge; Thu, 1 Jun 2017 02:45:33 -0700 (PDT) X-Received: by 10.200.48.149 with SMTP id v21mr642846qta.84.1496310333130; Thu, 01 Jun 2017 02:45:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496310333; cv=none; d=google.com; s=arc-20160816; b=XNbpiA/4zWrhFhIWJ/chl5BicZz/xgbgWE0NCGBg58ZvOkzYo9hwJuYdK3hurrgBdh sGjEg86yeWC7ZmYW4RWzdYq3mA69AGrukvPuPqRvi72zjWgdMuIoBPu2QDeqldyUIeOS 2HKv/vsDcBr+qvlFwQvzPFrcdGXOijFlkK7bqlv7pALb5No4eGcxoAcSh8X1YmkC8f6p t35vtpdMsv9D0bQxMC/LatYjaZSAICXdmapzHWctjmhLZf0K4zApysDxfSxhK2R5eTnm hna6KKeIdZ70xy+GgiEuCcfRfl0fb5aFEQSaf2PYmtsXkLTEREkgd11hvZH97CNgT67b DJSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:delivered-to:arc-authentication-results; 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[54.225.227.206]) by mx.google.com with ESMTP id p19si18693684qtg.171.2017.06.01.02.45.32; Thu, 01 Jun 2017 02:45:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id B6055609B3; Thu, 1 Jun 2017 09:45:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_SORBS_SPAM, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 7C86F609B1; Thu, 1 Jun 2017 09:44:42 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id D0BEE60A0F; Thu, 1 Jun 2017 09:44:34 +0000 (UTC) Received: from mail-wm0-f49.google.com (mail-wm0-f49.google.com [74.125.82.49]) by lists.linaro.org (Postfix) with ESMTPS id 94307609A4 for ; Thu, 1 Jun 2017 09:44:11 +0000 (UTC) Received: by mail-wm0-f49.google.com with SMTP id 7so150495128wmo.1 for ; Thu, 01 Jun 2017 02:44:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zVe8cIJeoWaJjgiA+lh9Mh4Dcht5obk3UfB0fkLiuZM=; b=IJQnOKS6U3g/BenMUPXEPUPGf4o8Kjp/WU+anB/lMrk01AFgH2T+ZP5Kh4aLAqNQ6v 4OIpdg7T7Ih/Nh54J98Wh6kJT8/9S6eEDIMHIT+wvqxnguJDbmIR+cfki4fDFu8V2p5K A7Z4xTZkH8UyJ4b0PJ23UjKPvYX3o7pLbVYXvK814Zg8AtIZxyZENMDNjYW+gs/YA5jV WsLPNO/9cUSnOAUQCe+5eCXYuzLJ7BOZaU/AvFVJOwxmXBQFBX6jhdYIxszHcgzR/Lvn ehbKvXaEm3rnDrsdvzL4jpRHKPP+4n44wjE9pJtamP80slA42y9LY7XINyGKDC2y+yIA ht2A== X-Gm-Message-State: AODbwcDPTtzjb9MjNjEsByudc1thhyGtD8nbDPyIUu6mulvzwkfWRoRU s4UUbNrF+Wcan79cjeQ6PsqH X-Received: by 10.223.170.74 with SMTP id q10mr525997wrd.171.1496310250474; Thu, 01 Jun 2017 02:44:10 -0700 (PDT) Received: from localhost.localdomain ([196.71.200.86]) by smtp.gmail.com with ESMTPSA id 64sm23257679wmn.20.2017.06.01.02.44.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Jun 2017 02:44:09 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Thu, 1 Jun 2017 09:43:52 +0000 Message-Id: <20170601094353.16235-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170601094353.16235-1-ard.biesheuvel@linaro.org> References: <20170601094353.16235-1-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH 5/6] Platforms/AMD/Overdrive: fix GIC MMIO region sizes X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" As reported by Punit, Xen panics in the following way when booted on Overdrive when using this firmware: (XEN) **************************************** (XEN) Panic on CPU 0: (XEN) GICv2: Sizes of GICC (0x00000000002000) and GICV (0x00000000010000) don't match (XEN) (XEN) **************************************** This is due to the fact that the MMIO region sizes deviate from the Linux upstream version of the DTS for no good reason. So fix that. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm Acked-by: Punit Agrawal --- Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 9357 -> 9357 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 4 ++-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb index 7ec1f63aff7805a3db7efc7a9b6e3c04f3c856cd..c8e5fd980bce305186214aab10a7d399faa22500 100644 GIT binary patch delta 31 fcmeD6?DgERlu?L5fdK>_ih(I0p|E*7<25A!an=T} delta 31 fcmeD6?DgERlu?M00Sq3BL1+d>hRxd; reg = <0x0 0xe1110000 0x0 0x1000>, <0x0 0xe112f000 0x0 0x2000>, - <0x0 0xe1140000 0x0 0x10000>, - <0x0 0xe1160000 0x0 0x10000>; + <0x0 0xe1140000 0x0 0x2000>, + <0x0 0xe1160000 0x0 0x2000>; interrupts = <0x1 0x9 0xf04>; ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; linux,phandle = <0x1>; From patchwork Thu Jun 1 09:43:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 100867 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp719061qge; Thu, 1 Jun 2017 02:45:45 -0700 (PDT) X-Received: by 10.55.73.133 with SMTP id w127mr526639qka.4.1496310345581; Thu, 01 Jun 2017 02:45:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496310345; cv=none; d=google.com; s=arc-20160816; b=Z2g65jNQNifz8/Z3PsV9lia5Cx1G9U3CtTUXG7apDSeXdUlN7RHLH7Qeu97p973hgL o3+Zpv2zJRhFBeop+T/L8t7YUAyDQiNBh2B5pIU/f51t0P+BVFI6qejY4I8eAqcc9yjO Xyk047w2zjmqzo2TA3s6BZCCmE3KczPAImYwomJ/jdWEh9wsaXK/WU1R4J9r/kWsBa8x P3riunAViPO9fdbgUKUsiGdBEZoBE892n/riEgonGSCTs35aIsVwV7gJH8e1weDv3zBm W/IU+PfXsD7AIcsUOzOOt04RpT7XNQJCJxRtuhpW43qT09JkYhQSzxN5pI0NwSG2hyTC R/qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:delivered-to:arc-authentication-results; bh=T2yFTIQ7qQgvlY3EEbGdZQ0zVjovhwbcu0GgL16jQ88=; b=u71HqkVdLIQ7hBRW7K7vzW7enzHPA8qLpTcAzcIZUW4rD9AmJU+/lnnwfgdmjjtW9/ dbgclvlkmhdEo2zlu2e1qEBpQv0RFWlYc1s7y0s3JCg3KIYBqMQOzTXn54QK1eky7TcY D3cM5ff1LA0mSfA5tzEEkAmJrItPuTFDrOMNQ7rHxPP3wzIbrADOBn3aC0iN+jZhAhkq TnoXCS7x4aJvjYrCeq+h1ye5KD1tvTW3l6gX4ysSvZocyzBRwzDFF1tJ3n9MU3e+e3Pd kh9yxdrXEfKzEhANQiFtc8ZjHkh2XJM/EdQTd5yWdAC/zhWmbsqCctP0M02t7N6NdT7F 7xlw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id p19si18694219qtg.171.2017.06.01.02.45.45; Thu, 01 Jun 2017 02:45:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3E045609B3; Thu, 1 Jun 2017 09:45:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id A295960A2E; Thu, 1 Jun 2017 09:44:44 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 41CF3609AA; Thu, 1 Jun 2017 09:44:36 +0000 (UTC) Received: from mail-wm0-f44.google.com (mail-wm0-f44.google.com [74.125.82.44]) by lists.linaro.org (Postfix) with ESMTPS id 5F1BC609DC for ; Thu, 1 Jun 2017 09:44:13 +0000 (UTC) Received: by mail-wm0-f44.google.com with SMTP id b84so151102789wmh.0 for ; Thu, 01 Jun 2017 02:44:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1mt0XXH2zyDsaF1YI3aKgzBHmMSpRkgrngQcST+wDvA=; b=lwuMYoAv08Sgyka3uqemhFvGKeYVyGV+7BOUwK/YkuridK8bvpomm/h4mJMqMcvi+E Jaqv45lDfbYH7IZX3JVQr8gSJcokKFdA5YcmCxVmSD27nP1v7Ign29SzyTRLOXZA7eMD zFdF2JENKIE98UR/DYVJ6gAjdWt+XJq0HWii1rgWsqzgYhSoTjqSqX+x9SfmjROAzwfn FTKKw7xO+WaCvbQjFPYxTJ/i096lTHK5Szc/gK74xf88ZsKYYpLbvxIWq0KXrhOdjolN pBUrOsCHC3IFEVwLdlO7vih2M8EyutHds7TXEZJLULE2ai/gSDCZq0YjrscN7MMganP9 w8Uw== X-Gm-Message-State: AODbwcCOtOsjVpGvpq9w+Bj14VTtVS56m9R7sIMyADmF1UgmCYfFbaaN 8Y96fjWUKqWxevQlKn1fd0ql X-Received: by 10.28.98.8 with SMTP id w8mr8696924wmb.121.1496310252297; Thu, 01 Jun 2017 02:44:12 -0700 (PDT) Received: from localhost.localdomain ([196.71.200.86]) by smtp.gmail.com with ESMTPSA id 64sm23257679wmn.20.2017.06.01.02.44.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Jun 2017 02:44:11 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Thu, 1 Jun 2017 09:43:53 +0000 Message-Id: <20170601094353.16235-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170601094353.16235-1-ard.biesheuvel@linaro.org> References: <20170601094353.16235-1-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH 6/6] Platforms/AMD/Styx: align UEFI PCI bus range with DT/ACPI descriptions X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The DT and ACPI descriptions of the PCIe root complex only specify a bus range of [0x0, 0x7f]. So let's use the same range in UEFI. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index b4893ca34587..98f5c9452dcd 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -423,7 +423,7 @@ DEFINE DO_KCS = 1 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000 gArmTokenSpaceGuid.PcdPciBusMin|0x0 - gArmTokenSpaceGuid.PcdPciBusMax|0xFF + gArmTokenSpaceGuid.PcdPciBusMax|0x7F gArmTokenSpaceGuid.PcdPciIoBase|0x1000 gArmTokenSpaceGuid.PcdPciIoSize|0xF000