From patchwork Fri Feb 18 09:16:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BBFDC4321E for ; Fri, 18 Feb 2022 09:16:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231174AbiBRJRM (ORCPT ); Fri, 18 Feb 2022 04:17:12 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233204AbiBRJRJ (ORCPT ); Fri, 18 Feb 2022 04:17:09 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74FEB10FC7; Fri, 18 Feb 2022 01:16:45 -0800 (PST) X-UUID: c669cd9a74da4a49a946962a501f6aa2-20220218 X-UUID: c669cd9a74da4a49a946962a501f6aa2-20220218 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1132822781; Fri, 18 Feb 2022 17:16:38 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:37 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 01/23] arm64: dts: mt8192: Add power domains controller Date: Fri, 18 Feb 2022 17:16:11 +0800 Message-ID: <20220218091633.9368-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add power domains controller node for SoC mt8192. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++++++++++++++ 1 file changed, 201 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c1d4030e7e4b..f10a9c75b20c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8192"; @@ -301,6 +302,206 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8192-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + power-domain@MT8192_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&infracfg CLK_INFRA_AUDIO>; + clock-names = "audio", "audio1", "audio2"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CONN { + reg = ; + clocks = <&infracfg CLK_INFRA_PMIC_CONN>; + clock-names = "conn"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { + reg = ; + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_MFG1 { + reg = ; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_MFG2 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG3 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG4 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG5 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG6 { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8192_POWER_DOMAIN_DISP { + reg = ; + clocks = <&topckgen CLK_TOP_DISP_SEL>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "disp", "disp-0", "disp-1", "disp-2", + "disp-3"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_IPE { + reg = ; + clocks = <&topckgen CLK_TOP_IPE_SEL>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS>; + clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", + "ipe-3"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_IMG1_SEL>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "isp", "isp-0", "isp-1"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_ISP2 { + reg = ; + clocks = <&topckgen CLK_TOP_IMG2_SEL>, + <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_GALS>; + clock-names = "isp2", "isp2-0", "isp2-1"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MDP { + reg = ; + clocks = <&topckgen CLK_TOP_MDP_SEL>, + <&mdpsys CLK_MDP_SMI0>; + clock-names = "mdp", "mdp-0"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_VENC_SEL>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "venc", "venc-0"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_VDEC2 { + reg = ; + clocks = <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "vdec2-0", "vdec2-1", + "vdec2-2"; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM { + reg = ; + clocks = <&topckgen CLK_TOP_CAM_SEL>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CCU_GALS>, + <&camsys CLK_CAM_CAM2MM_GALS>; + clock-names = "cam", "cam-0", "cam-1", "cam-2", + "cam-3"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { + reg = ; + clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "cam_rawa-0"; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { + reg = ; + clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "cam_rawb-0"; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { + reg = ; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; + clock-names = "cam_rawc-0"; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8192-wdt"; reg = <0 0x10007000 0 0x100>; From patchwork Fri Feb 18 09:16:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF76EC433EF for ; Fri, 18 Feb 2022 09:16:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233194AbiBRJRK (ORCPT ); Fri, 18 Feb 2022 04:17:10 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233188AbiBRJRE (ORCPT ); Fri, 18 Feb 2022 04:17:04 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC3C610FD9; Fri, 18 Feb 2022 01:16:47 -0800 (PST) X-UUID: ea24ec52d4c949aebf453e56e417182b-20220218 X-UUID: ea24ec52d4c949aebf453e56e417182b-20220218 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 681940819; Fri, 18 Feb 2022 17:16:41 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:40 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 04/23] arm64: dts: mt8192: Add gce node Date: Fri, 18 Feb 2022 17:16:14 +0800 Message-ID: <20220218091633.9368-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add gce node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 8635c8a53472..f92d8d7afa5d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include #include @@ -552,6 +553,15 @@ #size-cells = <0>; }; + gce: mailbox@10228000 { + compatible = "mediatek,mt8192-gce"; + reg = <0 0x10228000 0 0x4000>; + interrupts = ; + #mbox-cells = <3>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; From patchwork Fri Feb 18 09:16:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543893 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B999C4332F for ; Fri, 18 Feb 2022 09:16:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233216AbiBRJRK (ORCPT ); Fri, 18 Feb 2022 04:17:10 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233191AbiBRJRE (ORCPT ); Fri, 18 Feb 2022 04:17:04 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EC8610FD0; Fri, 18 Feb 2022 01:16:45 -0800 (PST) X-UUID: 51e70bfc7d81466a93378d5b037a31d9-20220218 X-UUID: 51e70bfc7d81466a93378d5b037a31d9-20220218 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 94939064; Fri, 18 Feb 2022 17:16:43 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:42 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 06/23] arm64: dts: mt8192: Add usb-phy node Date: Fri, 18 Feb 2022 17:16:16 +0800 Message-ID: <20220218091633.9368-7-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 61aadd7bd397..ce18d692175f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -875,6 +875,31 @@ #clock-cells = <1>; }; + u3phy0: usb-phy@11e40000 { + compatible = "mediatek,mt8192-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port0: usb-phy@11e40000 { + reg = <0 0x11e40000 0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@11e40700 { + reg = <0 0x11e40700 0 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + i2c0: i2c@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>, From patchwork Fri Feb 18 09:16:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6785C433EF for ; Fri, 18 Feb 2022 09:16:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233245AbiBRJRN (ORCPT ); Fri, 18 Feb 2022 04:17:13 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233209AbiBRJRJ (ORCPT ); Fri, 18 Feb 2022 04:17:09 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0AFF11175; Fri, 18 Feb 2022 01:16:50 -0800 (PST) X-UUID: 8c74edc5be4d4c7cbc3def0e3364168e-20220218 X-UUID: 8c74edc5be4d4c7cbc3def0e3364168e-20220218 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1013492680; Fri, 18 Feb 2022 17:16:46 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:45 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:45 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 09/23] arm64: dts: mt8192: Add infracfg_rst node Date: Fri, 18 Feb 2022 17:16:19 +0800 Message-ID: <20220218091633.9368-10-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add infracfg_rst node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index f93fe3779161..a935a22babbb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8192"; @@ -267,10 +268,23 @@ #clock-cells = <1>; }; - infracfg: syscon@10001000 { - compatible = "mediatek,mt8192-infracfg", "syscon"; + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */ + 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */ + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */ + 0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */ + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */ + >; + }; }; pericfg: syscon@10003000 { From patchwork Fri Feb 18 09:16:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9256DC43217 for ; Fri, 18 Feb 2022 09:17:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233258AbiBRJRP (ORCPT ); Fri, 18 Feb 2022 04:17:15 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233208AbiBRJRJ (ORCPT ); Fri, 18 Feb 2022 04:17:09 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0CB71117E; Fri, 18 Feb 2022 01:16:50 -0800 (PST) X-UUID: cf2f7da9140d4f098cc3b515a4a63132-20220218 X-UUID: cf2f7da9140d4f098cc3b515a4a63132-20220218 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1742451437; Fri, 18 Feb 2022 17:16:47 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 18 Feb 2022 17:16:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:45 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 10/23] arm64: dts: mt8192: Add PCIe node Date: Fri, 18 Feb 2022 17:16:20 +0800 Message-ID: <20220218091633.9368-11-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PCIe node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a935a22babbb..4533c794effc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -886,6 +886,44 @@ }; }; + pcie: pcie@11230000 { + compatible = "mediatek,mt8192-pcie"; + device_type = "pci"; + reg = <0 0x11230000 0 0x2000>; + reg-names = "pcie-mac"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>, + <&infracfg CLK_INFRA_PCIE_TL_96M>, + <&infracfg CLK_INFRA_PCIE_TL_32K>, + <&infracfg CLK_INFRA_PCIE_PERI_26M>, + <&infracfg CLK_INFRA_PCIE_TOP_H_133M>, + <&infracfg CLK_INFRA_PCIE_PL_P_250M>; + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", + "obff_ck0", "axi_ck0", "pipe_ck0"; + assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; + resets = <&infracfg_rst 2>, + <&infracfg_rst 3>; + reset-names = "phy", "mac"; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, + <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; From patchwork Fri Feb 18 09:16:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 855DFC433FE for ; Fri, 18 Feb 2022 09:17:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233268AbiBRJRS (ORCPT ); Fri, 18 Feb 2022 04:17:18 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233232AbiBRJRM (ORCPT ); Fri, 18 Feb 2022 04:17:12 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CADC10FD0; Fri, 18 Feb 2022 01:16:54 -0800 (PST) X-UUID: fae9cd7c560b4e168fd4f3cab55fe57e-20220218 X-UUID: fae9cd7c560b4e168fd4f3cab55fe57e-20220218 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1348336215; Fri, 18 Feb 2022 17:16:49 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:48 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 13/23] arm64: dts: mt8192: Add mmc device nodes Date: Fri, 18 Feb 2022 17:16:23 +0800 Message-ID: <20220218091633.9368-14-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add mmc nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 +++++++++++++++++++++--- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 094805db395b..cfc2db501108 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1154,10 +1154,38 @@ #clock-cells = <1>; }; - msdc: clock-controller@11f60000 { - compatible = "mediatek,mt8192-msdc"; - reg = <0 0x11f60000 0 0x1000>; - #clock-cells = <1>; + mmc0: mmc@11f60000 { + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11f60000 0 0x1000>, + <0 0x11f50000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, + <&msdc_top CLK_MSDC_TOP_SRC_0P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>, + <&msdc_top CLK_MSDC_TOP_P_MSDC0>; + clock-names = "source", "hclk", "source_cg", "sys_cg", + "axi_cg", "ahb_cg", "pclk_cg"; + status = "disabled"; + }; + + mmc1: mmc@11f70000 { + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11f70000 0 0x1000>, + <0 0x11c70000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, + <&msdc_top CLK_MSDC_TOP_SRC_1P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>, + <&msdc_top CLK_MSDC_TOP_P_MSDC1>; + clock-names = "source", "hclk", "source_cg", "sys_cg", + "axi_cg", "ahb_cg", "pclk_cg"; + status = "disabled"; }; mfgcfg: clock-controller@13fbf000 { From patchwork Fri Feb 18 09:16:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1F10C4321E for ; Fri, 18 Feb 2022 09:17:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233240AbiBRJRQ (ORCPT ); Fri, 18 Feb 2022 04:17:16 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233195AbiBRJRK (ORCPT ); Fri, 18 Feb 2022 04:17:10 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6907512628; Fri, 18 Feb 2022 01:16:53 -0800 (PST) X-UUID: ed695d1ebde8408181d8632c57bf6e3a-20220218 X-UUID: ed695d1ebde8408181d8632c57bf6e3a-20220218 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 403941676; Fri, 18 Feb 2022 17:16:50 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 18 Feb 2022 17:16:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:49 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node Date: Fri, 18 Feb 2022 17:16:24 +0800 Message-ID: <20220218091633.9368-15-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add mipi_tx node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index cfc2db501108..f5e5af949f19 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1114,6 +1114,16 @@ }; }; + mipi_tx0: mipi-dphy@11e50000 { + compatible = "mediatek,mt8183-mipi-tx"; + reg = <0 0x11e50000 0 0x1000>; + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; + clock-names = "ref_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + }; + i2c0: i2c@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>, From patchwork Fri Feb 18 09:16:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543887 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEEE1C4167D for ; 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Fri, 18 Feb 2022 17:16:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:50 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 15/23] arm64: dts: mt8192: Add m4u and smi nodes Date: Fri, 18 Feb 2022 17:16:25 +0800 Message-ID: <20220218091633.9368-16-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add m4u and smi nodes for mt8192 SoC Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 191 +++++++++++++++++++++++ 1 file changed, 191 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index f5e5af949f19..40887120fdb3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -1210,24 +1211,114 @@ #clock-cells = <1>; }; + smi_common: smi@14002000 { + compatible = "mediatek,mt8192-smi-common"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_GALS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb0: larb@14003000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + mediatek,larb-id = <0>; + mediatek,smi = <&smi_common>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb1: larb@14004000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x14004000 0 0x1000>; + mediatek,larb-id = <1>; + mediatek,smi = <&smi_common>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + iommu0: m4u@1401d000 { + compatible = "mediatek,mt8192-m4u"; + reg = <0 0x1401d000 0 0x1000>; + mediatek,larbs = <&larb0 &larb1 &larb2 + &larb4 &larb5 &larb7 + &larb9 &larb11 &larb13 + &larb14 &larb16 &larb17 + &larb18 &larb19 &larb20>; + interrupts = ; + clocks = <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "bclk"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + #iommu-cells = <1>; + }; + imgsys: clock-controller@15020000 { compatible = "mediatek,mt8192-imgsys"; reg = <0 0x15020000 0 0x1000>; #clock-cells = <1>; }; + larb9: larb@1502e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1502e000 0 0x1000>; + mediatek,larb-id = <9>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; + }; + imgsys2: clock-controller@15820000 { compatible = "mediatek,mt8192-imgsys2"; reg = <0 0x15820000 0 0x1000>; #clock-cells = <1>; }; + larb11: larb@1582e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1582e000 0 0x1000>; + mediatek,larb-id = <11>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_LARB11>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; + }; + + larb5: larb@1600d000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1600d000 0 0x1000>; + mediatek,larb-id = <5>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + vdecsys_soc: clock-controller@1600f000 { compatible = "mediatek,mt8192-vdecsys_soc"; reg = <0 0x1600f000 0 0x1000>; #clock-cells = <1>; }; + larb4: larb@1602e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1602e000 0 0x1000>; + mediatek,larb-id = <4>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, + <&vdecsys CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + vdecsys: clock-controller@1602f000 { compatible = "mediatek,mt8192-vdecsys"; reg = <0 0x1602f000 0 0x1000>; @@ -1240,12 +1331,79 @@ #clock-cells = <1>; }; + larb7: larb@17010000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,larb-id = <7>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC_SET0_LARB>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8192-camsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + larb13: larb@1a001000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + mediatek,larb-id = <13>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB13>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb14: larb@1a002000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + mediatek,larb-id = <14>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB14>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb16: larb@1a00f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a00f000 0 0x1000>; + mediatek,larb-id = <16>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "apb", "smi"; + mediatek,smi-id = <16>; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: larb@1a010000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + mediatek,larb-id = <17>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; + }; + + larb18: larb@1a011000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a011000 0 0x1000>; + mediatek,larb-id = <18>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, + <&camsys_rawc CLK_CAM_RAWC_CAM>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; + }; + camsys_rawa: clock-controller@1a04f000 { compatible = "mediatek,mt8192-camsys_rawa"; reg = <0 0x1a04f000 0 0x1000>; @@ -1270,10 +1428,43 @@ #clock-cells = <1>; }; + larb20: larb@1b00f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1b00f000 0 0x1000>; + mediatek,larb-id = <20>; + mediatek,smi = <&smi_common>; + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB20>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; + }; + + larb19: larb@1b10f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1b10f000 0 0x1000>; + mediatek,larb-id = <19>; + mediatek,smi = <&smi_common>; + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB19>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; + }; + mdpsys: clock-controller@1f000000 { compatible = "mediatek,mt8192-mdpsys"; reg = <0 0x1f000000 0 0x1000>; #clock-cells = <1>; }; + + larb2: larb@1f002000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1f002000 0 0x1000>; + mediatek,larb-id = <2>; + mediatek,smi = <&smi_common>; + clocks = <&mdpsys CLK_MDP_SMI0>, + <&mdpsys CLK_MDP_SMI0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; + }; }; }; From patchwork Fri Feb 18 09:16:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543886 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB0CFC433F5 for ; Fri, 18 Feb 2022 09:17:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229974AbiBRJRU (ORCPT ); Fri, 18 Feb 2022 04:17:20 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233248AbiBRJRN (ORCPT ); Fri, 18 Feb 2022 04:17:13 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFE4D9FEC; Fri, 18 Feb 2022 01:16:56 -0800 (PST) X-UUID: cc028a83800b49e99bc316c9ab689c23-20220218 X-UUID: cc028a83800b49e99bc316c9ab689c23-20220218 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 21078361; Fri, 18 Feb 2022 17:16:52 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:52 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes Date: Fri, 18 Feb 2022 17:16:27 +0800 Message-ID: <20220218091633.9368-18-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add vcodec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 936aa788664f..543a80252ce5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1291,6 +1291,64 @@ power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; }; + vcodec_dec: vcodec_dec@16000000 { + compatible = "mediatek,mt8192-vcodec-dec"; + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ + mediatek,scp = <&scp>; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + }; + + vcodec_lat: vcodec_lat@0x16010000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */ + interrupts = ; + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec", + "vdec-top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + vcodec_core: vcodec_core@0x16025000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts = ; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec", + "vdec-top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + larb5: larb@1600d000 { compatible = "mediatek,mt8192-smi-larb"; reg = <0 0x1600d000 0 0x1000>; From patchwork Fri Feb 18 09:16:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84AA0C433F5 for ; Fri, 18 Feb 2022 09:17:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233274AbiBRJRY (ORCPT ); Fri, 18 Feb 2022 04:17:24 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233284AbiBRJRQ (ORCPT ); Fri, 18 Feb 2022 04:17:16 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDF4110FF4; Fri, 18 Feb 2022 01:16:57 -0800 (PST) X-UUID: e45ba5cb1f66402c8a47c7a1b4a737fa-20220218 X-UUID: e45ba5cb1f66402c8a47c7a1b4a737fa-20220218 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1768322415; Fri, 18 Feb 2022 17:16:56 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:55 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 17:16:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:54 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 20/23] arm64: dts: mt8192: Add display nodes Date: Fri, 18 Feb 2022 17:16:30 +0800 Message-ID: <20220218091633.9368-21-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add display nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 115 +++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index e3314cdc7c1a..026f2d8141b0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -32,6 +32,11 @@ i2c7 = &i2c7; i2c8 = &i2c8; i2c9 = &i2c9; + ovl0 = &ovl0; + ovl-2l0 = &ovl_2l0; + ovl-2l2 = &ovl_2l2; + rdma0 = &rdma0; + rdma4 = &rdma4; }; clk26m: oscillator0 { @@ -1224,6 +1229,13 @@ #clock-cells = <1>; }; + mutex: mutex@14001000 { + compatible = "mediatek,mt8192-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + }; + smi_common: smi@14002000 { compatible = "mediatek,mt8192-smi-common"; reg = <0 0x14002000 0 0x1000>; @@ -1255,6 +1267,109 @@ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; }; + ovl0: ovl@14005000 { + compatible = "mediatek,mt8192-disp-ovl"; + reg = <0 0x14005000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + ovl_2l0: ovl@14006000 { + compatible = "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14006000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + }; + + rdma0: rdma@14007000 { + compatible = "mediatek,mt8192-disp-rdma"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; + mediatek,larb = <&larb0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + color0: color@14009000 { + compatible = "mediatek,mt8192-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + }; + + ccorr0: ccorr@1400a000 { + compatible = "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + }; + + aal0: aal@1400b000 { + compatible = "mediatek,mt8192-disp-aal"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + }; + + gamma0: gamma@1400c000 { + compatible = "mediatek,mt8192-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + }; + + postmask0: postmask@1400d000 { + compatible = "mediatek,mt8192-disp-postmask"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; + iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; + }; + + dither0: dither@1400e000 { + compatible = "mediatek,mt8192-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + }; + + ovl_2l2: ovl@14014000 { + compatible = "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + }; + + rdma4: rdma@14015000 { + compatible = "mediatek,mt8192-disp-rdma"; + reg = <0 0x14015000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA4>; + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; + mediatek,rdma-fifo-size = <2048>; + }; + dpi0: dpi@14016000 { compatible = "mediatek,mt8192-dpi"; reg = <0 0x14016000 0 0x1000>; From patchwork Fri Feb 18 09:16:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 543884 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52DCBC433F5 for ; Fri, 18 Feb 2022 09:17:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233342AbiBRJRc (ORCPT ); Fri, 18 Feb 2022 04:17:32 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:59666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233314AbiBRJRZ (ORCPT ); Fri, 18 Feb 2022 04:17:25 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 020201D334; Fri, 18 Feb 2022 01:17:05 -0800 (PST) X-UUID: 0d04cbee63d6418d80cc3d063b58a05a-20220218 X-UUID: 0d04cbee63d6418d80cc3d063b58a05a-20220218 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1942008424; Fri, 18 Feb 2022 17:17:00 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Feb 2022 17:16:58 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 17:16:58 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , --to=Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Allen-KH Cheng Subject: [PATCH v2 23/23] arm64: dts: mt8192: Add pwm node Date: Fri, 18 Feb 2022 17:16:33 +0800 Message-ID: <20220218091633.9368-24-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pwm node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index df884c48669e..c0fc723fdf0a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -642,6 +642,16 @@ status = "disabled"; }; + pwm0: pwm@1100e000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names = "main", "mm"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8192-spi", "mediatek,mt6765-spi";