From patchwork Sun Feb 20 21:20:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Srba X-Patchwork-Id: 544483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFB26C4321E for ; Sun, 20 Feb 2022 21:23:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245134AbiBTVX4 (ORCPT ); Sun, 20 Feb 2022 16:23:56 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232384AbiBTVXy (ORCPT ); Sun, 20 Feb 2022 16:23:54 -0500 Received: from mxd1.seznam.cz (mxd1.seznam.cz [IPv6:2a02:598:a::78:210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1032237BD1; Sun, 20 Feb 2022 13:23:29 -0800 (PST) Received: from email.seznam.cz by email-smtpc21a.ko.seznam.cz (email-smtpc21a.ko.seznam.cz [10.53.18.26]) id 0f7fd9d054718db90ed6158e; Sun, 20 Feb 2022 22:23:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=seznam.cz; s=beta; t=1645392182; bh=5CacqU51VJnf8YWAFmHJVLRausKpihvis5Guh6QHwhQ=; h=Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:MIME-Version: Content-Transfer-Encoding:X-szn-frgn:X-szn-frgc; b=ZUE7joK5ur5Zt/TkQbwZwSYoVVIZ3i7XUYS7RwpD9Evb7/toknWqNg0VZpfnLz9gp qgiN5nVisJT2JazY3o43cRIGEYRYwho0n/StEHMMyxyBmKR/UnvC7Heu8e4qYJyY2C 6u0k9lXb70DPyDVXFN/WxYnuTH8bKDR0XPMLiihE= Received: from localhost.localdomain (ip-111-27.static.ccinternet.cz [147.161.27.111]) by email-relay14.ko.seznam.cz (Seznam SMTPD 1.3.136) with ESMTP; Sun, 20 Feb 2022 22:22:59 +0100 (CET) From: michael.srba@seznam.cz To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Philipp Zabel Cc: Linus Walleij , Florian Fainelli , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Michael Srba , Rob Herring Subject: [PATCH v8 1/5] dt-bindings: clock: gcc-msm8998: Add definitions of SSC-related clocks Date: Sun, 20 Feb 2022 22:20:30 +0100 Message-Id: <20220220212034.9152-1-michael.srba@seznam.cz> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-szn-frgn: X-szn-frgc: <0> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Michael Srba Add definitions of four clocks which need to be manipulated in order to initialize the AHB bus which exposes the SCC block in the global address space. Signed-off-by: Michael Srba Acked-by: Rob Herring Reviewed-by: Stephen Boyd --- CHANGES: - v2: none - v3: none - v4: none - v5: none - v6: none - v7: use imperative in commit message - v8: none --- include/dt-bindings/clock/qcom,gcc-msm8998.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 72c99e486d86..1badb4f9c58f 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -186,6 +186,10 @@ #define UFS_UNIPRO_CORE_CLK_SRC 177 #define GCC_MMSS_GPLL0_CLK 178 #define HMSS_GPLL0_CLK_SRC 179 +#define GCC_IM_SLEEP 180 +#define AGGRE2_SNOC_NORTH_AXI 181 +#define SSC_XO 182 +#define SSC_CNOC_AHBS_CLK 183 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 From patchwork Sun Feb 20 21:20:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Srba X-Patchwork-Id: 544482 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D131C4167B for ; Sun, 20 Feb 2022 21:23:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245136AbiBTVX5 (ORCPT ); Sun, 20 Feb 2022 16:23:57 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238479AbiBTVXy (ORCPT ); Sun, 20 Feb 2022 16:23:54 -0500 Received: from mxd1.seznam.cz (mxd1.seznam.cz [IPv6:2a02:598:a::78:210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEA9C37ABA; Sun, 20 Feb 2022 13:23:29 -0800 (PST) Received: from email.seznam.cz by email-smtpc19b.ko.seznam.cz (email-smtpc19b.ko.seznam.cz [10.53.18.23]) id 7d9599c1269bcda87c3c559f; Sun, 20 Feb 2022 22:23:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=seznam.cz; s=beta; t=1645392182; bh=moX0DSSgBQKFRDZ0LKvjSSigpIh53hpU4PzFSq8kepU=; h=Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:X-szn-frgn: X-szn-frgc; b=PNXTMAhUKGt8rCLOUINoZNz7IPx3uoSVbjfqtm0V5AwGABeUfphB4z5dffG+hPm8m X7+pm6Ly59BLdGkFMOfP83fM3X6nAprTLcUccP00UhqK1ZMo83Yu7K0pS4lZrZTcdX ROVllL17uPKAUdBFBRq1ddY0kKboFAAbj+xLTurM= Received: from localhost.localdomain (ip-111-27.static.ccinternet.cz [147.161.27.111]) by email-relay14.ko.seznam.cz (Seznam SMTPD 1.3.136) with ESMTP; Sun, 20 Feb 2022 22:23:00 +0100 (CET) From: michael.srba@seznam.cz To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Philipp Zabel Cc: Linus Walleij , Florian Fainelli , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Michael Srba Subject: [PATCH v8 2/5] clk: qcom: gcc-msm8998: add SSC-related clocks Date: Sun, 20 Feb 2022 22:20:31 +0100 Message-Id: <20220220212034.9152-2-michael.srba@seznam.cz> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220212034.9152-1-michael.srba@seznam.cz> References: <20220220212034.9152-1-michael.srba@seznam.cz> MIME-Version: 1.0 X-szn-frgn: X-szn-frgc: <0> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Michael Srba Add four clocks which need to be manipulated in order to initialize the AHB bus which exposes the SCC block in the global address space. If a device is known to be configured such that writing to these registers from Linux is not permitted, the 'protected-clocks' device tree property must be used to denote that fact. Signed-off-by: Michael Srba --- CHANGES: - v2: none - v3: none - v4: reword the commit message - v5: none - v6: none - v7: change 'struct clk_init_data' to 'const struct clk_init_data', use imperative in commit message - v8: change hex constants to lowercase in accordance with the code style --- drivers/clk/qcom/gcc-msm8998.c | 56 ++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 407e2c5caea4..2d14c3d672fc 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2833,6 +2833,58 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = { }, }; +static struct clk_branch gcc_im_sleep_clk = { + .halt_reg = 0x4300c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4300c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_im_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch aggre2_snoc_north_axi_clk = { + .halt_reg = 0x83010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x83010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "aggre2_snoc_north_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ssc_xo_clk = { + .halt_reg = 0x63018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x63018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "ssc_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ssc_cnoc_ahbs_clk = { + .halt_reg = 0x6300c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6300c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "ssc_cnoc_ahbs_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, .gds_hw_ctrl = 0x0, @@ -3036,6 +3088,10 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, + [GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr, + [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr, + [SSC_XO] = &ssc_xo_clk.clkr, + [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr, }; static struct gdsc *gcc_msm8998_gdscs[] = { From patchwork Sun Feb 20 21:20:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Srba X-Patchwork-Id: 544284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC88CC3526E for ; Sun, 20 Feb 2022 21:23:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245137AbiBTVX5 (ORCPT ); Sun, 20 Feb 2022 16:23:57 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244276AbiBTVXz (ORCPT ); Sun, 20 Feb 2022 16:23:55 -0500 Received: from mxd1.seznam.cz (mxd1.seznam.cz [IPv6:2a02:598:a::78:210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C650A377F9; Sun, 20 Feb 2022 13:23:30 -0800 (PST) Received: from email.seznam.cz by email-smtpc22a.ko.seznam.cz (email-smtpc22a.ko.seznam.cz [10.53.18.28]) id 49aac02f12a4944648030c71; Sun, 20 Feb 2022 22:23:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=seznam.cz; s=beta; t=1645392183; bh=ivbWPD4urwlD2EwKFkvTw9F6EXeJFHkc+xmoSuZkQ3E=; h=Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:X-szn-frgn: X-szn-frgc; b=gBypIhQHrMWnOJaz+5ld51SKZqR9u92EjwK6vnHA39wojGhF842700Xjuk/EubxRR GTmxy//EtUA5FzrD+CiOcMJEyhnu0SWXDi446W91QDGRinm9jdVkXhpOKZFC0EdtOz /NMitqlG1nkgwFKiNqzFLTOUdKjUaFnH0exhai/M= Received: from localhost.localdomain (ip-111-27.static.ccinternet.cz [147.161.27.111]) by email-relay14.ko.seznam.cz (Seznam SMTPD 1.3.136) with ESMTP; Sun, 20 Feb 2022 22:23:00 +0100 (CET) From: michael.srba@seznam.cz To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Philipp Zabel Cc: Linus Walleij , Florian Fainelli , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Michael Srba , Rob Herring Subject: [PATCH v8 3/5] dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus Date: Sun, 20 Feb 2022 22:20:32 +0100 Message-Id: <20220220212034.9152-3-michael.srba@seznam.cz> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220212034.9152-1-michael.srba@seznam.cz> References: <20220220212034.9152-1-michael.srba@seznam.cz> MIME-Version: 1.0 X-szn-frgn: X-szn-frgc: <0> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Michael Srba Adds bindings for the AHB bus which exposes the SCC block in the global address space. This bus (and the SSC block itself) is present on certain qcom SoCs. In typical configuration, this bus (as some of the clocks and registers that we need to manipulate) is not accessible to the OS, and the resources on this bus are indirectly accessed by communicating with a hexagon CPU core residing in the SSC block. In this configuration, the hypervisor is the one performing the bus initialization for the purposes of bringing the haxagon CPU core out of reset. However, it is possible to change the configuration, in which case this binding serves to allow the OS to initialize the bus. Signed-off-by: Michael Srba Reviewed-by: Rob Herring --- CHANGES: - v2: fix issues caught by by dt-schema - v3: none - v4: address the issues pointed out in the review - v5: clarify type of additional properties; remove ssc_tlmm node for now - v6: none - v7: fix indentation, use imperative in commit message - v8: none --- .../bindings/bus/qcom,ssc-block-bus.yaml | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml new file mode 100644 index 000000000000..4044af0afda8 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs + +maintainers: + - Michael Srba + +description: | + This binding describes the dependencies (clocks, resets, power domains) which + need to be turned on in a sequence before communication over the AHB bus + becomes possible. + + Additionally, the reg property is used to pass to the driver the location of + two sadly undocumented registers which need to be poked as part of the sequence. + +properties: + compatible: + items: + - const: qcom,msm8998-ssc-block-bus + - const: qcom,ssc-block-bus + + reg: + description: | + Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1 + registers + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: mpm_sscaon_config0 + - const: mpm_sscaon_config1 + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: xo + - const: aggre2 + - const: gcc_im_sleep + - const: aggre2_north + - const: ssc_xo + - const: ssc_ahbs + + power-domains: + description: Power domain phandles for the ssc_cx and ssc_mx power domains + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: ssc_cx + - const: ssc_mx + + resets: + description: | + Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the + branch control register associated with the ssc_xo and ssc_ahbs clocks) + minItems: 2 + maxItems: 2 + + reset-names: + items: + - const: ssc_reset + - const: ssc_bcr + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: describes how to locate the ssc AXI halt register + items: + - items: + - description: Phandle reference to a syscon representing TCSR + - description: offset for the ssc AXI halt register + +required: + - compatible + - reg + - reg-names + - '#address-cells' + - '#size-cells' + - ranges + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - qcom,halt-regs + +additionalProperties: + type: object + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + // devices under this node are physically located in the SSC block, connected to an ssc-internal bus; + ssc_ahb_slave: bus@10ac008 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus"; + reg = <0x10ac008 0x4>, <0x10ac010 0x4>; + reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1"; + + clocks = <&xo>, + <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&gcc GCC_IM_SLEEP>, + <&gcc AGGRE2_SNOC_NORTH_AXI>, + <&gcc SSC_XO>, + <&gcc SSC_CNOC_AHBS_CLK>; + clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs"; + + resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>; + reset-names = "ssc_reset", "ssc_bcr"; + + power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>; + power-domain-names = "ssc_cx", "ssc_mx"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x26000>; + }; + }; From patchwork Sun Feb 20 21:20:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Srba X-Patchwork-Id: 544481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8624BC433EF for ; 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b=cPMHYkua0Q5zODeOQHCSfx95kzkRIupyG6FQuwh7bLe5E/eywjNQm5h5vR05p/FDF 5CgtVmKHXTC6S0RPBnc8O144aKtQ8v+FjmIvOyzzAy/VKrFV6RAa+lpNJNbnX5y42N 9y8Gq6XQ6EcipuskboCLVqAgpt/RE7E57Y4xLLq4= Received: from localhost.localdomain (ip-111-27.static.ccinternet.cz [147.161.27.111]) by email-relay14.ko.seznam.cz (Seznam SMTPD 1.3.136) with ESMTP; Sun, 20 Feb 2022 22:23:00 +0100 (CET) From: michael.srba@seznam.cz To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Philipp Zabel Cc: Linus Walleij , Florian Fainelli , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Michael Srba Subject: [PATCH v8 4/5] drivers: bus: add driver for initializing the SSC bus on (some) qcom SoCs Date: Sun, 20 Feb 2022 22:20:33 +0100 Message-Id: <20220220212034.9152-4-michael.srba@seznam.cz> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220212034.9152-1-michael.srba@seznam.cz> References: <20220220212034.9152-1-michael.srba@seznam.cz> MIME-Version: 1.0 X-szn-frgn: <5c87564a-171c-406d-9e4b-8b95cbf7c5ec> X-szn-frgc: <0> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Michael Srba Add bindings for the AHB bus which exposes the SCC block in the global address space. This bus (and the SSC block itself) is present on certain qcom SoCs. In typical configuration, this bus (as some of the clocks and registers that we need to manipulate) is not accessible to Linux, and the resources on this bus are indirectly accessed by communicating with a hexagon CPU core residing in the SSC block. In this configuration, the hypervisor is the one performing the bus initialization for the purposes of bringing the haxagon CPU core out of reset. However, it is possible to change the configuration, in which case this driver will initialize the bus. In combination with drivers for resources on the SSC bus, this driver can aid in debugging, and for example with a TLMM driver can be used to directly access SSC-dedicated GPIO pins, removing the need to commit to a particular usecase during hw design. Finally, until open firmware for the hexagon core is available, this approach allows for using sensors hooked up to SSC-dedicated GPIO pins on mainline Linux simply by utilizing the existing in-tree drivers for these sensors. Signed-off-by: Michael Srba --- CHANGES: - v2: none - v3: fix clang warning - v4: address the issues pointed out in the review - v5: none - v6: restore alphabetic ordering in Makefile against v5.17-rc4 - v7: use imperative in commit message - v8: none --- drivers/bus/Kconfig | 6 + drivers/bus/Makefile | 1 + drivers/bus/qcom-ssc-block-bus.c | 383 +++++++++++++++++++++++++++++++ 3 files changed, 390 insertions(+) create mode 100644 drivers/bus/qcom-ssc-block-bus.c diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 3c68e174a113..9e29d1da9a61 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -152,6 +152,12 @@ config QCOM_EBI2 Interface 2, which can be used to connect things like NAND Flash, SRAM, ethernet adapters, FPGAs and LCD displays. +config QCOM_SSC_BLOCK_BUS + bool "Qualcomm SSC Block Bus Init Driver" + help + Say y here to enable support for initializing the bus that connects the SSC block's internal + bus to the cNoC on (some) qcom SoCs + config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64 diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 52c2f35a26a9..e6756e83a9c4 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o +obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/qcom-ssc-block-bus.c b/drivers/bus/qcom-ssc-block-bus.c new file mode 100644 index 000000000000..e489f5614e90 --- /dev/null +++ b/drivers/bus/qcom-ssc-block-bus.c @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2021, Michael Srba + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* AXI Halt Register Offsets */ +#define AXI_HALTREQ_REG 0x0 +#define AXI_HALTACK_REG 0x4 +#define AXI_IDLE_REG 0x8 + +static const char *const qcom_ssc_block_pd_names[] = { + "ssc_cx", + "ssc_mx" +}; + +struct qcom_ssc_block_bus_data { + int num_pds; + const char *const *pd_names; + struct device *pds[ARRAY_SIZE(qcom_ssc_block_pd_names)]; + char __iomem *reg_mpm_sscaon_config0; // MPM - msm power manager; AON - always-on + char __iomem *reg_mpm_sscaon_config1; // that's as much as we know about these + struct regmap *halt_map; + u32 ssc_axi_halt; + struct clk *xo_clk; + struct clk *aggre2_clk; + struct clk *gcc_im_sleep_clk; + struct clk *aggre2_north_clk; + struct clk *ssc_xo_clk; + struct clk *ssc_ahbs_clk; + struct reset_control *ssc_bcr; + struct reset_control *ssc_reset; +}; + +static void reg32_set_bits(char __iomem *reg, u32 value) +{ + u32 tmp = ioread32(reg); + + iowrite32(tmp | value, reg); +} + +static void reg32_clear_bits(char __iomem *reg, u32 value) +{ + u32 tmp = ioread32(reg); + + iowrite32(tmp & (~value), reg); +} + + +static int qcom_ssc_block_bus_init(struct device *dev) +{ + int ret; + + struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev); + + ret = clk_prepare_enable(data->xo_clk); + if (ret) { + dev_err(dev, "error enabling xo_clk: %d\n", ret); + goto err_xo_clk; + } + + ret = clk_prepare_enable(data->aggre2_clk); + if (ret) { + dev_err(dev, "error enabling aggre2_clk: %d\n", ret); + goto err_aggre2_clk; + } + + ret = clk_prepare_enable(data->gcc_im_sleep_clk); + if (ret) { + dev_err(dev, "error enabling gcc_im_sleep_clk: %d\n", ret); + goto err_gcc_im_sleep_clk; + } + + reg32_clear_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5)); + reg32_clear_bits(data->reg_mpm_sscaon_config1, BIT(31)); + + ret = clk_prepare_enable(data->aggre2_north_clk); + if (ret) { + dev_err(dev, "error enabling aggre2_north_clk: %d\n", ret); + goto err_aggre2_north_clk; + } + + ret = reset_control_deassert(data->ssc_reset); + if (ret) { + dev_err(dev, "error deasserting ssc_reset: %d\n", ret); + goto err_ssc_reset; + } + + ret = reset_control_deassert(data->ssc_bcr); + if (ret) { + dev_err(dev, "error deasserting ssc_bcr: %d\n", ret); + goto err_ssc_bcr; + } + + regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 0); + + ret = clk_prepare_enable(data->ssc_xo_clk); + if (ret) { + dev_err(dev, "error deasserting ssc_xo_clk: %d\n", ret); + goto err_ssc_xo_clk; + } + + ret = clk_prepare_enable(data->ssc_ahbs_clk); + if (ret) { + dev_err(dev, "error deasserting ssc_ahbs_clk: %d\n", ret); + goto err_ssc_ahbs_clk; + } + + return 0; + +err_ssc_ahbs_clk: + clk_disable(data->ssc_xo_clk); + +err_ssc_xo_clk: + regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1); + + reset_control_assert(data->ssc_bcr); + +err_ssc_bcr: + reset_control_assert(data->ssc_reset); + +err_ssc_reset: + clk_disable(data->aggre2_north_clk); + +err_aggre2_north_clk: + reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5)); + reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31)); + + clk_disable(data->gcc_im_sleep_clk); + +err_gcc_im_sleep_clk: + clk_disable(data->aggre2_clk); + +err_aggre2_clk: + clk_disable(data->xo_clk); + +err_xo_clk: + return ret; +} + +static void qcom_ssc_block_bus_deinit(struct device *dev) +{ + int ret; + + struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev); + + clk_disable(data->ssc_xo_clk); + clk_disable(data->ssc_ahbs_clk); + + ret = reset_control_assert(data->ssc_bcr); + if (ret) + dev_err(dev, "error asserting ssc_bcr: %d\n", ret); + + regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1); + + reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31)); + reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5)); + + ret = reset_control_assert(data->ssc_reset); + if (ret) + dev_err(dev, "error asserting ssc_reset: %d\n", ret); + + clk_disable(data->gcc_im_sleep_clk); + + clk_disable(data->aggre2_north_clk); + + clk_disable(data->aggre2_clk); + clk_disable(data->xo_clk); +} + + +static int qcom_ssc_block_bus_pds_attach(struct device *dev, struct device **pds, + const char *const *pd_names, size_t num_pds) +{ + int ret; + int i; + + for (i = 0; i < num_pds; i++) { + pds[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); + if (IS_ERR_OR_NULL(pds[i])) { + ret = PTR_ERR(pds[i]) ? : -ENODATA; + goto unroll_attach; + } + } + + return num_pds; + +unroll_attach: + for (i--; i >= 0; i--) + dev_pm_domain_detach(pds[i], false); + + return ret; +}; + +static void qcom_ssc_block_bus_pds_detach(struct device *dev, struct device **pds, size_t num_pds) +{ + int i; + + for (i = 0; i < num_pds; i++) + dev_pm_domain_detach(pds[i], false); +} + +static int qcom_ssc_block_bus_pds_enable(struct device **pds, size_t num_pds) +{ + int ret; + int i; + + for (i = 0; i < num_pds; i++) { + dev_pm_genpd_set_performance_state(pds[i], INT_MAX); + ret = pm_runtime_get_sync(pds[i]); + if (ret < 0) + goto unroll_pd_votes; + } + + return 0; + +unroll_pd_votes: + for (i--; i >= 0; i--) { + dev_pm_genpd_set_performance_state(pds[i], 0); + pm_runtime_put(pds[i]); + } + + return ret; +}; + +static void qcom_ssc_block_bus_pds_disable(struct device **pds, size_t num_pds) +{ + int i; + + for (i = 0; i < num_pds; i++) { + dev_pm_genpd_set_performance_state(pds[i], 0); + pm_runtime_put(pds[i]); + } +} + +static int qcom_ssc_block_bus_probe(struct platform_device *pdev) +{ + struct qcom_ssc_block_bus_data *data; + struct device_node *np = pdev->dev.of_node; + struct of_phandle_args halt_args; + struct resource *res; + int ret; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + platform_set_drvdata(pdev, data); + + data->pd_names = qcom_ssc_block_pd_names; + data->num_pds = ARRAY_SIZE(qcom_ssc_block_pd_names); + + // power domains + ret = qcom_ssc_block_bus_pds_attach(&pdev->dev, data->pds, data->pd_names, data->num_pds); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "error when attaching power domains\n"); + + ret = qcom_ssc_block_bus_pds_enable(data->pds, data->num_pds); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "error when enabling power domains\n"); + + // the meaning of the bits in these two registers is sadly not documented, + // the set/clear operations are just copying what qcom does + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0"); + data->reg_mpm_sscaon_config0 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->reg_mpm_sscaon_config0)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->reg_mpm_sscaon_config0), + "Failed to ioremap mpm_sscaon_config0\n"); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config1"); + data->reg_mpm_sscaon_config1 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->reg_mpm_sscaon_config1)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->reg_mpm_sscaon_config1), + "Failed to ioremap mpm_sscaon_config1\n"); + + // resets + data->ssc_bcr = devm_reset_control_get_exclusive(&pdev->dev, "ssc_bcr"); + if (IS_ERR(data->ssc_bcr)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_bcr), + "Failed to acquire reset: scc_bcr\n"); + + data->ssc_reset = devm_reset_control_get_exclusive(&pdev->dev, "ssc_reset"); + if (IS_ERR(data->ssc_reset)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_reset), + "Failed to acquire reset: ssc_reset:\n"); + + // clocks + data->xo_clk = devm_clk_get(&pdev->dev, "xo"); + if (IS_ERR(data->xo_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->xo_clk), + "Failed to get clock: xo\n"); + + data->aggre2_clk = devm_clk_get(&pdev->dev, "aggre2"); + if (IS_ERR(data->aggre2_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->aggre2_clk), + "Failed to get clock: aggre2\n"); + + data->gcc_im_sleep_clk = devm_clk_get(&pdev->dev, "gcc_im_sleep"); + if (IS_ERR(data->gcc_im_sleep_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->gcc_im_sleep_clk), + "Failed to get clock: gcc_im_sleep\n"); + + data->aggre2_north_clk = devm_clk_get(&pdev->dev, "aggre2_north"); + if (IS_ERR(data->aggre2_north_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->aggre2_north_clk), + "Failed to get clock: aggre2_north\n"); + + data->ssc_xo_clk = devm_clk_get(&pdev->dev, "ssc_xo"); + if (IS_ERR(data->ssc_xo_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_xo_clk), + "Failed to get clock: ssc_xo\n"); + + data->ssc_ahbs_clk = devm_clk_get(&pdev->dev, "ssc_ahbs"); + if (IS_ERR(data->ssc_ahbs_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_ahbs_clk), + "Failed to get clock: ssc_ahbs\n"); + + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "qcom,halt-regs", 1, 0, + &halt_args); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to parse qcom,halt-regs\n"); + + data->halt_map = syscon_node_to_regmap(halt_args.np); + of_node_put(halt_args.np); + if (IS_ERR(data->halt_map)) + return PTR_ERR(data->halt_map); + + data->ssc_axi_halt = halt_args.args[0]; + + qcom_ssc_block_bus_init(&pdev->dev); + + of_platform_populate(np, NULL, NULL, &pdev->dev); + + return 0; +} + +static int qcom_ssc_block_bus_remove(struct platform_device *pdev) +{ + struct qcom_ssc_block_bus_data *data = platform_get_drvdata(pdev); + + qcom_ssc_block_bus_deinit(&pdev->dev); + + iounmap(data->reg_mpm_sscaon_config0); + iounmap(data->reg_mpm_sscaon_config1); + + qcom_ssc_block_bus_pds_disable(data->pds, data->num_pds); + qcom_ssc_block_bus_pds_detach(&pdev->dev, data->pds, data->num_pds); + pm_runtime_disable(&pdev->dev); + pm_clk_destroy(&pdev->dev); + + return 0; +} + +static const struct of_device_id qcom_ssc_block_bus_of_match[] = { + { .compatible = "qcom,ssc-block-bus", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, qcom_ssc_block_bus_of_match); + +static struct platform_driver qcom_ssc_block_bus_driver = { + .probe = qcom_ssc_block_bus_probe, + .remove = qcom_ssc_block_bus_remove, + .driver = { + .name = "qcom-ssc-block-bus", + .of_match_table = qcom_ssc_block_bus_of_match, + }, +}; + +module_platform_driver(qcom_ssc_block_bus_driver); + +MODULE_DESCRIPTION("A driver for handling the init sequence needed for accessing the SSC block on (some) qcom SoCs over AHB"); +MODULE_AUTHOR("Michael Srba "); +MODULE_LICENSE("GPL v2"); From patchwork Sun Feb 20 21:20:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Srba X-Patchwork-Id: 544285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0E26C43217 for ; Sun, 20 Feb 2022 21:23:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245054AbiBTVX4 (ORCPT ); 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Sun, 20 Feb 2022 22:23:00 +0100 (CET) From: michael.srba@seznam.cz To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Philipp Zabel Cc: Linus Walleij , Florian Fainelli , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Michael Srba , Michael Srba Subject: [PATCH v8 5/5] arm64: dts: qcom: msm8998: reserve potentially inaccessible clocks Date: Sun, 20 Feb 2022 22:20:34 +0100 Message-Id: <20220220212034.9152-5-michael.srba@seznam.cz> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220212034.9152-1-michael.srba@seznam.cz> References: <20220220212034.9152-1-michael.srba@seznam.cz> MIME-Version: 1.0 X-szn-frgn: X-szn-frgc: <0> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Michael Srba With the gcc driver now being more complete and describing clocks which might not always be write-accessible to the OS, conservatively specify all such clocks as protected in the SoC dts. The board dts - or even user-supplied dts - can override this property to reflect the actual configuration. Signed-off-by: Michael Srba Reviewed-by: Jeffrey Hugo --- CHANGES: - v2: add this patch - v3: fix missing Signed-off-by - v4: add a proper explanation as per review, (hopefully) fix the subject and commit message - v5: none - v6: none - v7: none - v8: none --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index f273bc1ff629..16dccf9d881e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -863,6 +863,21 @@ gcc: clock-controller@100000 { clock-names = "xo", "sleep_clk"; clocks = <&xo>, <&sleep_clk>; + + /* + * The hypervisor typically configures the memory region where these clocks + * reside as read-only for the HLOS. If the HLOS tried to enable or disable + * these clocks on a device with such configuration (e.g. because they are + * enabled but unused during boot-up), the device will most likely decide + * to reboot. + * In light of that, we are conservative here and we list all such clocks + * as protected. The board dts (or a user-supplied dts) can override the + * list of protected clocks if it differs from the norm, and it is in fact + * desired for the HLOS to manage these clocks + */ + protected-clocks = , + , + ; }; rpm_msg_ram: sram@778000 {