From patchwork Mon Feb 28 12:02:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 548291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE2E1C4321E for ; Mon, 28 Feb 2022 12:03:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236116AbiB1MEB (ORCPT ); Mon, 28 Feb 2022 07:04:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236137AbiB1MD6 (ORCPT ); Mon, 28 Feb 2022 07:03:58 -0500 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83ACE17A88 for ; Mon, 28 Feb 2022 04:03:15 -0800 (PST) Received: by mail-lj1-x230.google.com with SMTP id u7so17020037ljk.13 for ; Mon, 28 Feb 2022 04:03:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=llyo1vt8nztwq9vuzChH7ZX+hL5GQL+RCx/E9zX9FlQ=; b=jig1PrXmtI6DQFsrrZZPbfkPW/kd4F4C97eud7gOQE/RJ+A9kmrWOs0XfHFuE5Xh9E TgnMN5eYdHLfk0V35dgYoFgcPdviKh3f+bUyz1tYNbydOdMIn2HniMo71K4SlPg27oWj Yuof6Mgh8hctVzZ4/AfgQt0RtQEVSRZUPyXXvzQ/8scnNNguGMUNpGimAbXj8INBNDpC zGUUAQxwRqFakTPR44aZ3bMb1HC7wqA8bkx+3xXwInvreDyWq1p0siMWPSqoWdDe5Aga aQbjWS0czlznWIWe/7uKJiF6GN2VWSqrbIG7mdtpUgaBTN2e8PQXn8Q6QyWAq6skhobn rNyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=llyo1vt8nztwq9vuzChH7ZX+hL5GQL+RCx/E9zX9FlQ=; b=4wgbVuJ0tgVMPFF6qwYXjKW3VDkQmthOv+Pn6HHnq/TxUYJ49RIBpM5eSaGmzdq+Ob mJ4vQchCJjqi+2XMLE5Zb/J8b8ScGpeEC68GKbTcpXfr0K1QBsWpcb1PaEzdyxoAgV8G MIoVO6zn6AzfBKHyxiKNd7EK35I/CQt7mNdIHPO6oA96XNyr8m6tFSechRtwVayj5Abm W4muFzi4h+rzvqWtBWdigXBlrG47u5EJ3tqSQYa3wiNfs2LrUMitcLnLtl/XL+3oPD5M aMj15Tmx1kSDTZ1mQg9ispkj2NfgaiR0TuUSZJL6kdDG/ZvrvXezbpOF/Ffv15JlFsVe bNWQ== X-Gm-Message-State: AOAM5327i/WikDT7DXT3MPJXtrRsmIzx/N0LVcj7jrFHMBnWSiVop4/q RuFyJHVy3L941dloEgU5YVOIAw== X-Google-Smtp-Source: ABdhPJwzGV33FpCY/Mjj3WaO+AWk2tV7z5IHci8HwW6CnNcWT5ts7Xh/kk3h/YosKv52jZDfqOHgtA== X-Received: by 2002:a2e:9d46:0:b0:246:1605:7802 with SMTP id y6-20020a2e9d46000000b0024616057802mr14405425ljj.264.1646049793877; Mon, 28 Feb 2022 04:03:13 -0800 (PST) Received: from localhost.localdomain (88-113-46-102.elisa-laajakaista.fi. [88.113.46.102]) by smtp.gmail.com with ESMTPSA id j19-20020a2e6e13000000b002463d2595fbsm1284253ljc.7.2022.02.28.04.03.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 04:03:13 -0800 (PST) From: Vladimir Zapolskiy To: Rob Herring , Bjorn Andersson Cc: Andy Gross , Stephen Boyd , Michael Turquette , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/8] arm64: dts: qcom: sm8450: Add description of camera clock controller Date: Mon, 28 Feb 2022 14:02:58 +0200 Message-Id: <20220228120258.997027-3-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220228120258.997027-1-vladimir.zapolskiy@linaro.org> References: <20220228120258.997027-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The change adds description of QCOm SM8450 camera clock controller. Signed-off-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 10c25ad2d0c7..54d1a5df1048 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -672,6 +673,24 @@ usb_1_ssphy: phy@88e9200 { }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8450-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "iface", + "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; From patchwork Mon Feb 28 12:03:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 548290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5422FC433FE for ; Mon, 28 Feb 2022 12:03:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233380AbiB1MEU (ORCPT ); Mon, 28 Feb 2022 07:04:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236122AbiB1MER (ORCPT ); Mon, 28 Feb 2022 07:04:17 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C128717E0F for ; Mon, 28 Feb 2022 04:03:38 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id i11so20966786lfu.3 for ; Mon, 28 Feb 2022 04:03:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wpNOYJbLuHAROObNPm3JzKG5s6/JM5BLEeZyhqZ773Q=; b=forMbeBW4fCCoz6ra4j4jdnnt3YZ5ahGiQmjH2hEPf8wICpZ2GTJyc2R8kIwGaY8um e/YGs+u25viKM9bvkNlZUH3Lx6dQe3I52XSEKM08qaJX/yCTxlGYkcPqDgVwYXte+tgJ /+bLsSqvfLZw7RV+pmep9Tp9pwEuu8Zf3dRzKREoYtzPEaZKEnwIzQ+wsAi9d+cvUcJZ f8XNxY3wBPP2HUQJgwdr26xMCalE3ZecLpaFX8LcHUgIIH6Tzl4/d8P1xHQMQ14iGwV1 7Ez6s4F/QyW5NsH7JW41bTJGQZpqCH9yiFBGBQl9J1ZXiStNGie/5fiTefAyWScSUDnH fwkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wpNOYJbLuHAROObNPm3JzKG5s6/JM5BLEeZyhqZ773Q=; b=1DpS9TU/XO1aKaRiycjOQ4NUsu8RAdoAaYKMz+ZMpKvwxCOrVWZ3Sx1FX+sqXNec0e APbTjqECpXOoSlopwd/Qv0SvBInt0KwVdSQTYHXgaSOCZxixZ1Bbt+wj6gahEGJ+HPZs I6fQC4iHLJbb8jug8X61PRpNQG4AXvO3V43d2jRCarbgrSyl4Rh3L1fKYFVNA3Bdoi4s YPyIZEVctp/Kdii0T0Q/Lbpl7D/BX2xnStnTlNs2lWJvcHTzJFIYm0qhFQIDxx/nIQZR TRkonm5SaLOmLeJ+aU7tDcarN8zTHoyCUxUAWUVEVNJL4aj/et7e3ao3Rzmv9gdP8kjU zI6Q== X-Gm-Message-State: AOAM530rn94l161vEFijVnYC4uRk5GzSy7B+e/8QB29ayyFI0g/t641Q 98XctpbwjSE6YqkIgtrTXO/Jss5J9yzJ1x5A X-Google-Smtp-Source: ABdhPJwjcDOJvwHIVv66Ff6OPuiGUnLQofUx6A6fszsDjXhpOsnULjPQPLHdH4yTocrBb1jVxciN3A== X-Received: by 2002:a05:6512:324e:b0:443:b0a3:6756 with SMTP id c14-20020a056512324e00b00443b0a36756mr13127965lfr.613.1646049817146; Mon, 28 Feb 2022 04:03:37 -0800 (PST) Received: from localhost.localdomain (88-113-46-102.elisa-laajakaista.fi. [88.113.46.102]) by smtp.gmail.com with ESMTPSA id a21-20020a19f815000000b00443977d5a61sm928516lff.110.2022.02.28.04.03.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 04:03:36 -0800 (PST) From: Vladimir Zapolskiy To: Bjorn Andersson Cc: Andy Gross , Stephen Boyd , Michael Turquette , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 3/8] clk: qcom: clk-alpha-pll: fix clk_trion_pll_configure description Date: Mon, 28 Feb 2022 14:03:34 +0200 Message-Id: <20220228120334.997058-1-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220228120258.997027-1-vladimir.zapolskiy@linaro.org> References: <20220228120258.997027-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org After merging lucid and trion pll functions in commit 0b01489475c6 ("clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid") the function clk_trion_pll_configure() is left with an old description header, which results in a W=2 compile time warning, fix it. Signed-off-by: Vladimir Zapolskiy Acked-by: Stephen Boyd --- drivers/clk/qcom/clk-alpha-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 4406cf609aae..288692f0ea39 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1439,7 +1439,7 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); /** - * clk_lucid_pll_configure - configure the lucid pll + * clk_trion_pll_configure - configure the trion pll * * @pll: clk alpha pll * @regmap: register map From patchwork Mon Feb 28 12:03:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 548289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12216C433FE for ; Mon, 28 Feb 2022 12:03:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236130AbiB1ME0 (ORCPT ); Mon, 28 Feb 2022 07:04:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236136AbiB1MEY (ORCPT ); Mon, 28 Feb 2022 07:04:24 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CCC929C87 for ; Mon, 28 Feb 2022 04:03:44 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id u7so17021829ljk.13 for ; Mon, 28 Feb 2022 04:03:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X1kSt/cNOLlYSBXaFCcGxTofXAnfGn13whIIfArQmJc=; b=WrHVxS79m29CFEiohaDpnInO4nUT8U7LX83tqoBZx6omXMGH8ySx52udZKm3fpF8GH zPKoCeZxuyVit1itrSSvO5u04qqOk/0ki1kGK6MbQesZJ6qcrALguLJzZQs4Sll4e0Jc bp6H9dXH0JbEaPS/7CppuaFAILWZd4x91py53z56/KKwbDFLkuvbYF0Zm8Zky45dHJzB pdjndwx8oY4WawYUvAWqajDcLoeJZITuVIxpgj9u2TMaXYYsw8dg2K4C4j9LW70+h9dN INHSlcHchM3MDKZOhP6ON/WV+AYed0Mp9gxr2pj2yFeaRpYYgJDP3eX7rwJFeNXLITn5 jqzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X1kSt/cNOLlYSBXaFCcGxTofXAnfGn13whIIfArQmJc=; b=2zIVK/RWJKNPma3blVxUz3b/ub8yLIeCx3tBDh7JCfJsdQpmR8Z45j1Btd8LJKo8gB GWUtUlv/qhWpgA1RBMOjzq/v1t2gaq6zYJdpSWspoWe9LLNDsyvdB0mZtntdSBi0btpw 5HfTn9/i4vx3LSGnvItSOw+vlW0NdPDfTfAWvE5MSvCFnPL7Mh3Pr930b7M1EPfHw6xk qaE4ZMLYsBd+8LOCNeWXOow5yl4K+8xBM2Yy8CA46mv4oMPXSn20hPP2gY+j9hDFt+6q aWHv4NLKK2FFT8mgW2jBQiieQnWFlsi/lpLvQNuaTCdlsyXVxRbm1h0gj/6a0j92peGi YOMw== X-Gm-Message-State: AOAM532qPDjG8Rthi2vnOCM8fAd3FAi2ZjZptZq2MNmBEzkeoyZ4WHQw dEJHoTE7Dve2ybHlchv4hZ95Sg== X-Google-Smtp-Source: ABdhPJxj9aYhDgJS5z9oUFopmsw5kxl7jTsBdnOT3BNdANgWdC+WvaNNqb6+yrL67BD9qnP/D84gkA== X-Received: by 2002:a2e:3e13:0:b0:246:7097:87eb with SMTP id l19-20020a2e3e13000000b00246709787ebmr11534107lja.168.1646049822423; Mon, 28 Feb 2022 04:03:42 -0800 (PST) Received: from localhost.localdomain (88-113-46-102.elisa-laajakaista.fi. [88.113.46.102]) by smtp.gmail.com with ESMTPSA id q17-20020a2e8751000000b00244beaacef1sm1278111ljj.18.2022.02.28.04.03.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 04:03:42 -0800 (PST) From: Vladimir Zapolskiy To: Bjorn Andersson Cc: Andy Gross , Stephen Boyd , Michael Turquette , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 6/8] clk: qcom: clk-alpha-pll: export lucid evo PLL configuration interfaces Date: Mon, 28 Feb 2022 14:03:41 +0200 Message-Id: <20220228120341.997121-1-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220228120258.997027-1-vladimir.zapolskiy@linaro.org> References: <20220228120258.997027-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The change exports lucid evo PLL configuration and control functions to clock controller drivers. Signed-off-by: Vladimir Zapolskiy --- drivers/clk/qcom/clk-alpha-pll.c | 65 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 5 ++- 2 files changed, 69 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 47879ee5a677..54bad5277802 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -191,8 +191,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) /* LUCID EVO PLL specific settings and offsets */ +#define LUCID_EVO_PCAL_NOT_DONE BIT(8) #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) +#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 /* ZONDA PLL specific */ #define ZONDA_PLL_OUT_MASK 0xf @@ -1994,6 +1996,33 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); +void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l | + (TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT)); + + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); + + /* Disable PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + + /* Set operation mode to STANDBY */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); + + /* Place the PLL in STANDBY mode */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); +} +EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); + static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); @@ -2079,6 +2108,31 @@ static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); } +static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct clk_hw *p; + u32 val = 0; + int ret; + + /* Return early if calibration is not needed. */ + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); + if (!(val & LUCID_EVO_PCAL_NOT_DONE)) + return 0; + + p = clk_hw_get_parent(hw); + if (!p) + return -EINVAL; + + ret = alpha_pll_lucid_evo_enable(hw); + if (ret) + return ret; + + alpha_pll_lucid_evo_disable(hw); + + return 0; +} + static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -2114,3 +2168,14 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { .set_rate = clk_lucid_evo_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); + +const struct clk_ops clk_alpha_pll_lucid_evo_ops = { + .prepare = alpha_pll_lucid_evo_prepare, + .enable = alpha_pll_lucid_evo_enable, + .disable = alpha_pll_lucid_evo_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = alpha_pll_lucid_evo_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = alpha_pll_lucid_5lpe_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6e9907deaf30..0b7a6859ca2c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -152,6 +152,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_zonda_ops; #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops + +extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; @@ -168,6 +170,7 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); - +void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); #endif From patchwork Mon Feb 28 12:03:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 548288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28224C433FE for ; Mon, 28 Feb 2022 12:03:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236158AbiB1ME3 (ORCPT ); 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[88.113.46.102]) by smtp.gmail.com with ESMTPSA id t24-20020a19dc18000000b004433d7c87a6sm937511lfg.72.2022.02.28.04.03.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 04:03:43 -0800 (PST) From: Vladimir Zapolskiy To: Bjorn Andersson Cc: Andy Gross , Stephen Boyd , Michael Turquette , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 7/8] clk: qcom: clk-alpha-pll: add rivian evo PLL configuration interfaces Date: Mon, 28 Feb 2022 14:03:42 +0200 Message-Id: <20220228120342.997142-1-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220228120258.997027-1-vladimir.zapolskiy@linaro.org> References: <20220228120258.997027-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The change adds and exports rivian evo PLL configuration and control functions to clock controller drivers. Signed-off-by: Vladimir Zapolskiy --- drivers/clk/qcom/clk-alpha-pll.c | 70 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 6 +++ 2 files changed, 76 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 54bad5277802..ab4f0fc15a48 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { + [PLL_OFF_OPMODE] = 0x04, + [PLL_OFF_STATUS] = 0x0c, + [PLL_OFF_L_VAL] = 0x10, + [PLL_OFF_USER_CTL] = 0x14, + [PLL_OFF_USER_CTL_U] = 0x18, + [PLL_OFF_CONFIG_CTL] = 0x1c, + [PLL_OFF_CONFIG_CTL_U] = 0x20, + [PLL_OFF_CONFIG_CTL_U1] = 0x24, + [PLL_OFF_TEST_CTL] = 0x28, + [PLL_OFF_TEST_CTL_U] = 0x2c, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -2179,3 +2191,61 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = { .set_rate = alpha_pll_lucid_5lpe_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); + +void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); + + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); + + regmap_update_bits(regmap, PLL_MODE(pll), + PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, + PLL_RESET_N | PLL_BYPASSNL); +} +EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); + +static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l; + + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); + + return parent_rate * l; +} + +static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + unsigned long min_freq, max_freq; + u32 l; + u64 a; + + rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); + if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) + return rate; + + min_freq = pll->vco_table[0].min_freq; + max_freq = pll->vco_table[pll->num_vco - 1].max_freq; + + return clamp(rate, min_freq, max_freq); +} + +const struct clk_ops clk_alpha_pll_rivian_evo_ops = { + .enable = alpha_pll_lucid_5lpe_enable, + .disable = alpha_pll_lucid_5lpe_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_rivian_evo_pll_recalc_rate, + .round_rate = clk_rivian_evo_pll_round_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 0b7a6859ca2c..447efb82fe59 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -18,6 +18,7 @@ enum { CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, CLK_ALPHA_PLL_TYPE_LUCID_EVO, + CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -157,6 +158,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; +extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; +#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, @@ -172,5 +176,7 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); #endif