From patchwork Tue Dec 4 20:26:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152852 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503383ljp; Tue, 4 Dec 2018 12:29:25 -0800 (PST) X-Google-Smtp-Source: AFSGD/WLWzk4YHoFrdgPREjFr6v6tdmGzTRgXRhU3o0zsQTI6VSoRhpXweK4kGt1gqbmOaWrUn1s X-Received: by 2002:a25:b086:: with SMTP id f6mr11032613ybj.116.1543955365655; Tue, 04 Dec 2018 12:29:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955365; cv=none; d=google.com; s=arc-20160816; b=pYwR3fi9c/pjsrc2gp1ar7779v1sKvl4eboE4fpzost5LgNFeJRgzilCgvtI6NzBmc 5Tg6UhMeOc3foYTwsx4HTvqqSIZgcgSY95wtoGLSmRW1KlD9D/pwo+wbGbxKfap4joO+ CwIrv4j7TScRCYG2Fk0mSmaWfIHkVhl2WPtxpo6DiM7AqD8pjer/DJ5cHMuDAdiyOzBf cnSNapQhoFiS/3uyfTzIgM9tL6h0yvU+nuM2KAVL/c6vSXdcbc0G9S47roWg2Ik/DUdN AIjo+t6lzuKwP4DnKz2rnlfZ9X1HkUB9EPEdLaUfp6qCmeGI7w3MOaD6wqS41RD1Izgj 9AOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=m/v0gxd+nXVhKHbcU6qc+bomDRYaYj//HlFhgLkNR5U=; b=VOyBEy3DjCmPYNtBkx0UOWDoE0HvsBxs87rUZzT0D8u6F8z+wa0arEiWRbtZT3lCxD MArX5fGwvbCm0BxgUVW9wkStVu8lW7PoaRvbwjPweW2Y96zcULKPHllixSWAyDp6LfPp 4FxD803uc/NMMP+1yf+aYAAGh7ORD6co1n0wjQJ4s8ljcy4jelx7P3TZrjFl3USxhV3z wWAWBL372D+v3hdYs7FR58tAr6x5yMk3ZiYO723lJQRuXA/qEVX0NlBV9q9g4UnJ32D4 8VvljV6nxspgED38ZEAfpPsLsRfd9PedEI9w1f6zAFMP3VBCoNw6/N2xtHIWeLX6pXlQ Ld6A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id v192si11530102ywa.235.2018.12.04.12.29.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHu-00085o-9U; Tue, 04 Dec 2018 20:27:22 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHs-00085Y-GJ for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:20 +0000 X-Inumbo-ID: ff51c996-f802-11e8-a585-df93f377db2e Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id ff51c996-f802-11e8-a585-df93f377db2e; Tue, 04 Dec 2018 20:27:19 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A5A4D15BE; Tue, 4 Dec 2018 12:27:18 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DD4F93F614; Tue, 4 Dec 2018 12:27:17 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:35 +0000 Message-Id: <20181204202651.8836-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 01/17] xen/arm: Introduce helpers to clear/flags flags in HCR_EL2 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A couple of places in the code will need to clear/set flags in HCR_EL2 for a given vCPU and then replicate into the hardware. Introduce helpers and replace open-coded version. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- The patch was previously sent separately and reviewed by Stefano. I haven't find a good place for those new helpers so stick to processor.h at the moment. This require to use macro rather than inline helpers given that processor.h is usually the root of all headers. --- xen/arch/arm/traps.c | 3 +-- xen/include/asm-arm/processor.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 88ffeeb480..c05a8ad25c 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -681,8 +681,7 @@ static void inject_vabt_exception(struct cpu_user_regs *regs) break; } - current->arch.hcr_el2 |= HCR_VA; - WRITE_SYSREG(current->arch.hcr_el2, HCR_EL2); + vcpu_hcr_set_flags(current, HCR_VA); } /* diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 72ddc42778..cb781751a6 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -490,6 +490,24 @@ register_t get_default_hcr_flags(void); : : : "memory"); \ } while (0) +/* + * Clear/Set flags in HCR_EL2 for a given vCPU. It only supports the current + * vCPU for now. + */ +#define vcpu_hcr_clear_flags(v, flags) \ + do { \ + ASSERT((v) == current); \ + (v)->arch.hcr_el2 &= ~(flags); \ + WRITE_SYSREG((v)->arch.hcr_el2, HCR_EL2); \ + } while (0) + +#define vcpu_hcr_set_flags(v, flags) \ + do { \ + ASSERT((v) == current); \ + (v)->arch.hcr_el2 |= (flags); \ + WRITE_SYSREG((v)->arch.hcr_el2, HCR_EL2); \ + } while (0) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_PROCESSOR_H */ /* From patchwork Tue Dec 4 20:26:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152847 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503214ljp; Tue, 4 Dec 2018 12:29:12 -0800 (PST) X-Google-Smtp-Source: AFSGD/VK6XR66djy/LJuEZD++BfVUQP6wVV7uUnztE3/J1Y9Jt6D/hQ20KJqkS6e+lgpwA9BfkK5 X-Received: by 2002:a25:1d56:: with SMTP id d83mr10284169ybd.392.1543955352572; Tue, 04 Dec 2018 12:29:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955352; cv=none; d=google.com; s=arc-20160816; b=W5Fau9+Qkyh/6pSbVxuThUrQ5kEiylwbezOxCbHBs6QW+JZlJ9W8ZbWukgJ6OpvzJo cE3Rn2GYP3/emTW7LfdT4Ny6xig/0NkAPKZZM9rAyS+7eEFxasX+W1Jr1xH4wh5IgxjV DerRMrXCfPpWTXQBbWENbRumD7nUPcFmv8XrP6Zpl0ZBCb4Mp0T6ZXUaVPUEt/WQ9EwI rfYJ33I3yWoE6NQs4+EGQVFGFrbgnfZADtZ8C85ncoVJcDD9CRyAFJmylwO0wPPqUuBO yzW0EbulJuDwV7NtHh2L1gkXbzFsUZytjoxc/uXDJHTyznkNMENj8uIThGjvHRs1KK3Y C82w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=PIX8FJZyS6hUguf1SNJCP5pgvTf/WCu+V/GDgun9FHQ=; b=py/VEFELTEFfo4bu9uLMogOfFZhulBqInhmvmtO5XOqgGE3yAXgC/bONcRTM0AdOx8 VmkLHJo8v7Cr1HmTL/J4GKcQpI1rWbrBiMnN6zSbdSk6lTvmUXd29dzDS8DAlP6o4/Qa MBVsitNh5K5SB1+1jdwKvUEKZEPI1h1rE+esvVmUOV5IDZxEPlQN5glyrAunf1tr08rj gIV5koXEc9Xe2HmEHkHCmwrqcfiAidrN09WWb3OoRPu49l1qQVvdBkQmH53OmXlwNXEE w0t4vdS4bpIV1NDbQqvuHRB9nR5XRAFOCKTq3ffC0psvbc/UUlV1g11009Qjc4baAPpr p5uA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id x131-v6si10373252yba.249.2018.12.04.12.29.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHIP-0000F6-IM; Tue, 04 Dec 2018 20:27:53 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHIN-0000Ck-JE for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:51 +0000 X-Inumbo-ID: 11acab24-f803-11e8-bfe5-4b39350725be Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 11acab24-f803-11e8-bfe5-4b39350725be; Tue, 04 Dec 2018 20:27:50 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AC9D315BF; Tue, 4 Dec 2018 12:27:19 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E38623F614; Tue, 4 Dec 2018 12:27:18 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:36 +0000 Message-Id: <20181204202651.8836-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 02/17] xen/arm: traps: Move the implementation of GUEST_BUG_ON in traps.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" GUEST_BUG_ON may be used in other files doing guest emulation. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- The patch was previously sent separately. Changes in v2: - Add Stefano's acked-by --- xen/arch/arm/traps.c | 24 ------------------------ xen/include/asm-arm/traps.h | 24 ++++++++++++++++++++++++ 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index c05a8ad25c..94fe1a6da7 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -67,30 +67,6 @@ static inline void check_stack_alignment_constraints(void) { #endif } -/* - * GUEST_BUG_ON is intended for checking that the guest state has not been - * corrupted in hardware and/or that the hardware behaves as we - * believe it should (i.e. that certain traps can only occur when the - * guest is in a particular mode). - * - * The intention is to limit the damage such h/w bugs (or spec - * misunderstandings) can do by turning them into Denial of Service - * attacks instead of e.g. information leaks or privilege escalations. - * - * GUEST_BUG_ON *MUST* *NOT* be used to check for guest controllable state! - * - * Compared with regular BUG_ON it dumps the guest vcpu state instead - * of Xen's state. - */ -#define guest_bug_on_failed(p) \ -do { \ - show_execution_state(guest_cpu_user_regs()); \ - panic("Guest Bug: %pv: '%s', line %d, file %s\n", \ - current, p, __LINE__, __FILE__); \ -} while (0) -#define GUEST_BUG_ON(p) \ - do { if ( unlikely(p) ) guest_bug_on_failed(#p); } while (0) - #ifdef CONFIG_ARM_32 static int debug_stack_lines = 20; #define stack_words_per_line 8 diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 6d8a43a691..997c37884e 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -10,6 +10,30 @@ # include #endif +/* + * GUEST_BUG_ON is intended for checking that the guest state has not been + * corrupted in hardware and/or that the hardware behaves as we + * believe it should (i.e. that certain traps can only occur when the + * guest is in a particular mode). + * + * The intention is to limit the damage such h/w bugs (or spec + * misunderstandings) can do by turning them into Denial of Service + * attacks instead of e.g. information leaks or privilege escalations. + * + * GUEST_BUG_ON *MUST* *NOT* be used to check for guest controllable state! + * + * Compared with regular BUG_ON it dumps the guest vcpu state instead + * of Xen's state. + */ +#define guest_bug_on_failed(p) \ +do { \ + show_execution_state(guest_cpu_user_regs()); \ + panic("Guest Bug: %pv: '%s', line %d, file %s\n", \ + current, p, __LINE__, __FILE__); \ +} while (0) +#define GUEST_BUG_ON(p) \ + do { if ( unlikely(p) ) guest_bug_on_failed(#p); } while (0) + int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr); void advance_pc(struct cpu_user_regs *regs, const union hsr hsr); From patchwork Tue Dec 4 20:26:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152846 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503213ljp; Tue, 4 Dec 2018 12:29:12 -0800 (PST) X-Google-Smtp-Source: AFSGD/VEK4kUcN9+oNbOsRA81PWRBzxcSV64lUVfuVcQhKdMkU3OrFqiK26boJ+zW1WS4e/ZLCBi X-Received: by 2002:a81:7dc6:: with SMTP id y189mr6873862ywc.310.1543955352545; Tue, 04 Dec 2018 12:29:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955352; cv=none; d=google.com; s=arc-20160816; b=D4KNYoa0V6p8AFNmAGusgJYZG0fc9knju6k0AlZDjWdI84DQKpF2EKgexUDDq5gsFk rQlHwzE25QsMhaV7PenAVe7tWmw2GG/bIREW4s2FLwnnFqOscVco/mmVnZ81GpXOXDo0 jBBUiuONd+KzgEeBX/ltEfyRJBPaSUIJ70XEW29VWDK2RnBJTKmQsgpBt83E8QKxsfcK r48PYPqswHKg3rwlNQXphr7wqnzL4UAizrKs4gwy3Jnuvd9fVtvWr0MhpHP4ruay9uvL 8opqgcE5ELTJuxRlZjoLig1JxBA9Wkwr9g0yXwbzGuSwM/dgL0m/kBnlVAxGlvYu8X74 +XIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=Laz2wZzTUg9gYfZqu7wyznHgA9Cr4f9B49M4NGdbghY=; b=A+VJtNkX81TTQPxnWkLHVh05+PYqvGMSDn3Sz7VPlYGNcK++kj5NjYbF5JgBXbQJ5w lBMUz7AQlbc2Io+3cXuKc/aGvX+kq+EwDdDREVKGB5jgdRiMy0sUlX5UGYJJWuA4F6Xs ERPBtiiicxrycFclan220xxENW32GPqtI+youJYMsAYcIeZfsaUIQefs2Vc5GXJnNeU3 xxSM4hwn6HMGwbQVxjFW9KBVOTRV2GcTaH6L5t51d0vSxNh5USdGAEFxH+QkScizhTQF S4A3GOTFtuvqjifVgvJXbekk7Uv4pV6zYesaneZrOQiNhEiK9ltxCkeyVhKwepS9KU7f 6twQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d6-v6si3286787ybi.259.2018.12.04.12.29.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHu-000864-PW; Tue, 04 Dec 2018 20:27:22 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHt-00085j-MQ for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:21 +0000 X-Inumbo-ID: 00646f32-f803-11e8-8ba2-9f94e87d73e3 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 00646f32-f803-11e8-8ba2-9f94e87d73e3; Tue, 04 Dec 2018 20:27:21 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B299C165C; Tue, 4 Dec 2018 12:27:20 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E9B643F614; Tue, 4 Dec 2018 12:27:19 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:37 +0000 Message-Id: <20181204202651.8836-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 03/17] xen/arm: p2m: Clean-up headers included and order them alphabetically X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A lot of the headers are not necessary, so remove them. At the same time, re-order them alphabetically. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/p2m.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 6c76298ebc..81f3107dd2 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1,19 +1,11 @@ -#include -#include -#include +#include #include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include +#include +#include + #include -#include +#include #include #define MAX_VMID_8_BIT (1UL << 8) From patchwork Tue Dec 4 20:26:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152853 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503419ljp; Tue, 4 Dec 2018 12:29:27 -0800 (PST) X-Google-Smtp-Source: AFSGD/XP57sTW1Y5tbq3nlXSzW5T30ILLm1hRIHtj1kXf9n0Zk5S+TiqFvng2qs9IphMi1xpUwk1 X-Received: by 2002:a25:4a83:: with SMTP id x125-v6mr20618527yba.413.1543955367845; Tue, 04 Dec 2018 12:29:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955367; cv=none; d=google.com; s=arc-20160816; b=Sg30HnWRHnHOAHThF03OLTRjKbdmUs1PVk/bjwpkfM/0N0XWUpMduMVZfvtUFmSARc 1G6arEeuna+bWJZLYfVwzFRJcFLvwENZlXo7NLnYxps3ukIkPcm5UMwJiKKnfrWooJsT BjVdo/IfKpt8wko5uLB/myyIhzFFNpHCk8UPRyI0gZDH3WJxMmtrTusWvDU+EjtFQwb9 zcbcxzH40JScGYqsZrYBWDVte/zBcPLxtjKOiClhYUsT7ZDO32kUdQ+sXq8YVzt8vo+A QeKcIVK6bJJCz3DYbt3HwCJ9xLawoc4C/SOd3n7irvz1bUuKKpFKdLkVoEAFZ+QqySo3 NIYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=Xxi/GvlZ9XZKDPydUYToaSn2bGWZD3JsAUvbWR+x9DM=; b=HRX9khRuCiEc0f0ON50rtenR55ymzuF7z9qmsne3BFENZz5Kssv8lAn2pMz0jYAAY1 dAObNeiyiDo1sjERZVqeNji+I2X8fQgz+hhd6gXyWXFrFYbvP3BV0EJDwFQBOR3mBKjJ txwtLjgl9KsJ1i0DDbBPoXPXR1o3To18CGoQ2hdjzMyqlwBmC44LKOOU9Rz8ONGWnS0R /0UjyI1UM3hdBDRDDBnEKxr9KFGiq9fgYebZK9Rkk7AolCNftregHX/NgeSfd9MzbhwA NBcQVFqayzeN089xzHGMpZ5dEcfHmkvSQW/cGZJbpOzHSG1ZRHtd59/+qeoRyKZii9xJ R9TQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id e184si10668288ywf.2.2018.12.04.12.29.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHw-00086N-2i; Tue, 04 Dec 2018 20:27:24 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHu-000867-UQ for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:22 +0000 X-Inumbo-ID: 00e163a2-f803-11e8-a4b4-0feac6537a25 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 00e163a2-f803-11e8-a4b4-0feac6537a25; Tue, 04 Dec 2018 20:27:21 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B854F168F; Tue, 4 Dec 2018 12:27:21 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F00563F614; Tue, 4 Dec 2018 12:27:20 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:38 +0000 Message-Id: <20181204202651.8836-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 04/17] xen/arm: p2m: Introduce p2m_is_valid and use it X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The LPAE format allows to store information in an entry even with the valid bit unset. In a follow-up patch, we will take advantage of this feature to re-purpose the valid bit for generating a translation fault even if an entry contains valid information. So we need a different way to know whether an entry contains valid information. It is possible to use the information hold in the p2m_type to know for that purpose. Indeed all entries containing valid information will have a valid p2m type (i.e p2m_type != p2m_invalid). This patch introduces a new helper p2m_is_valid, which implements that idea, and replace most of lpae_is_valid call with the new helper. The ones remaining are for TLBs handling and entries accounting. With the renaming there are 2 others changes required: - Generate table entry with a valid p2m type - Detect new mapping for proper stats accounting Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Don't open-code p2m_is_superpage --- xen/arch/arm/p2m.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 81f3107dd2..47b54c792e 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -212,17 +212,26 @@ static p2m_access_t p2m_mem_access_radix_get(struct p2m_domain *p2m, gfn_t gfn) } /* + * In the case of the P2M, the valid bit is used for other purpose. Use + * the type to check whether an entry is valid. + */ +static inline bool p2m_is_valid(lpae_t pte) +{ + return pte.p2m.type != p2m_invalid; +} + +/* * lpae_is_* helpers don't check whether the valid bit is set in the * PTE. Provide our own overlay to check the valid bit. */ static inline bool p2m_is_mapping(lpae_t pte, unsigned int level) { - return lpae_is_valid(pte) && lpae_is_mapping(pte, level); + return p2m_is_valid(pte) && lpae_is_mapping(pte, level); } static inline bool p2m_is_superpage(lpae_t pte, unsigned int level) { - return lpae_is_valid(pte) && lpae_is_superpage(pte, level); + return p2m_is_valid(pte) && lpae_is_superpage(pte, level); } #define GUEST_TABLE_MAP_FAILED 0 @@ -256,7 +265,7 @@ static int p2m_next_level(struct p2m_domain *p2m, bool read_only, entry = *table + offset; - if ( !lpae_is_valid(*entry) ) + if ( !p2m_is_valid(*entry) ) { if ( read_only ) return GUEST_TABLE_MAP_FAILED; @@ -348,7 +357,7 @@ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, entry = table[offsets[level]]; - if ( lpae_is_valid(entry) ) + if ( p2m_is_valid(entry) ) { *t = entry.p2m.type; @@ -536,8 +545,11 @@ static lpae_t page_to_p2m_table(struct page_info *page) /* * The access value does not matter because the hardware will ignore * the permission fields for table entry. + * + * We use p2m_ram_rw so the entry has a valid type. This is important + * for p2m_is_valid() to return valid on table entries. */ - return mfn_to_p2m_entry(page_to_mfn(page), p2m_invalid, p2m_access_rwx); + return mfn_to_p2m_entry(page_to_mfn(page), p2m_ram_rw, p2m_access_rwx); } static inline void p2m_write_pte(lpae_t *p, lpae_t pte, bool clean_pte) @@ -561,7 +573,7 @@ static int p2m_create_table(struct p2m_domain *p2m, lpae_t *entry) struct page_info *page; lpae_t *p; - ASSERT(!lpae_is_valid(*entry)); + ASSERT(!p2m_is_valid(*entry)); page = alloc_domheap_page(NULL, 0); if ( page == NULL ) @@ -618,7 +630,7 @@ static int p2m_mem_access_radix_set(struct p2m_domain *p2m, gfn_t gfn, */ static void p2m_put_l3_page(const lpae_t pte) { - ASSERT(lpae_is_valid(pte)); + ASSERT(p2m_is_valid(pte)); /* * TODO: Handle other p2m types @@ -646,7 +658,7 @@ static void p2m_free_entry(struct p2m_domain *p2m, struct page_info *pg; /* Nothing to do if the entry is invalid. */ - if ( !lpae_is_valid(entry) ) + if ( !p2m_is_valid(entry) ) return; /* Nothing to do but updating the stats if the entry is a super-page. */ @@ -943,7 +955,7 @@ static int __p2m_set_entry(struct p2m_domain *p2m, else p2m->need_flush = true; } - else /* new mapping */ + else if ( !p2m_is_valid(orig_pte) ) /* new mapping */ p2m->stats.mappings[level]++; p2m_write_pte(entry, pte, p2m->clean_pte); @@ -957,7 +969,7 @@ static int __p2m_set_entry(struct p2m_domain *p2m, * Free the entry only if the original pte was valid and the base * is different (to avoid freeing when permission is changed). */ - if ( lpae_is_valid(orig_pte) && + if ( p2m_is_valid(orig_pte) && !mfn_eq(lpae_get_mfn(*entry), lpae_get_mfn(orig_pte)) ) p2m_free_entry(p2m, orig_pte, level); From patchwork Tue Dec 4 20:26:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152854 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503423ljp; Tue, 4 Dec 2018 12:29:28 -0800 (PST) X-Google-Smtp-Source: AFSGD/Vcs5QXDTPvUFpTOTNF/Y2/r4MvSv5EofnBX7XFmE9FgmnrgJtj0EgoHMAdSJvxUSEgPXAh X-Received: by 2002:a25:1486:: with SMTP id 128-v6mr20368321ybu.97.1543955368211; Tue, 04 Dec 2018 12:29:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955368; cv=none; d=google.com; s=arc-20160816; b=PBmOiugQWybrwHPy5/R3hpAtX0ZTu02+kT+i/u3cMfXeltRzflzCGX386O5jvBzhsF lfYV0Ni9a6p7Xe15EH5iZUJjo0BonJVBPBuDW+1shu8Pq4MznAtMkk7LbcJuJXt78ctI XgQ4sP+YbR0gkUTVW/klyMADpF5NdVEpV+TkfE2ei/R4vajU8OvOXiHD8bgxEazDmotx Pc86VCZVRdB8JqWZXio8GYSCSPYBOG8oFWHWfattF7B9AOBzD+05avKCI7uXwlc0J9B1 DTI/nSoajbOL0DiOHNExT1RDEXwud3tV2D6IlpKho2D4zoRgOuFS8y6aUNUHc2FKP2ub vTwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=hJ2CwD6aSnXOGXB3l6ZnqWs1MVMsUD8BH8r1cEoQaI4=; b=kYq45syBAxDwPIxWGwmU+L6jI+2GWHuqALKlo0W6fIcoiKZ7SBJdoyY1Qi8RPMhPyA 7co+KuhvSq8V9ShgsmU/iPglUaeRqyONy33pMICgy7fVgSc1iCsyxzk0sY3k8ZOt+U3H SdFlTtlOrMHYwiUvxNMOTLaRydQC3CSPPs3YnQclnmZyntvTNwhuO8fokBy8Z5JIrKhD f2m3MASu16aB59t5enf9ndUdNdM5LqPMxeL/owjj1e2Ru+VzgK0dmIDxqr7DMzxVDTXx NVU4G56wKaHsNyfb5gZWxHPx4W03vnprIYxYoAY2IbAYlrIigd8lt7e8YmSaX1AUl2oR nJHA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id t8-v6si10114781ybb.191.2018.12.04.12.29.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHx-00086i-D2; Tue, 04 Dec 2018 20:27:25 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHv-00086J-Vy for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:24 +0000 X-Inumbo-ID: 017e2a48-f803-11e8-9b20-5fe4980ec26a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 017e2a48-f803-11e8-9b20-5fe4980ec26a; Tue, 04 Dec 2018 20:27:22 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BE82915BE; Tue, 4 Dec 2018 12:27:22 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0205F3F614; Tue, 4 Dec 2018 12:27:21 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:39 +0000 Message-Id: <20181204202651.8836-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 05/17] xen/arm: p2m: Handle translation fault in get_page_from_gva X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will re-purpose the valid bit of LPAE entries to generate fault even on entry containing valid information. This means that when translating a guest VA to guest PA (e.g IPA) will fail if the Stage-2 entries used have the valid bit unset. Because of that, we need to fallback to walk the page-table in software to check whether the fault was expected. This patch adds the software page-table walk on all the translation fault. It would be possible in the future to avoid pointless walk when the fault in PAR_EL1 is not a translation fault. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- There are a couple of TODO in the code. They are clean-up and performance improvement (e.g when the fault cannot be handled) that could be delayed after the series has been merged. Changes in v2: - Check stage-2 permission during software lookup - Fix typoes --- xen/arch/arm/p2m.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 47b54c792e..39680eeb6e 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -6,6 +6,7 @@ #include #include +#include #include #define MAX_VMID_8_BIT (1UL << 8) @@ -1430,6 +1431,8 @@ struct page_info *get_page_from_gva(struct vcpu *v, vaddr_t va, struct page_info *page = NULL; paddr_t maddr = 0; uint64_t par; + mfn_t mfn; + p2m_type_t t; /* * XXX: To support a different vCPU, we would need to load the @@ -1446,8 +1449,29 @@ struct page_info *get_page_from_gva(struct vcpu *v, vaddr_t va, par = gvirt_to_maddr(va, &maddr, flags); p2m_read_unlock(p2m); + /* + * gvirt_to_maddr may fail if the entry does not have the valid bit + * set. Fallback to the second method: + * 1) Translate the VA to IPA using software lookup -> Stage-1 page-table + * may not be accessible because the stage-2 entries may have valid + * bit unset. + * 2) Software lookup of the MFN + * + * Note that when memaccess is enabled, we instead call directly + * p2m_mem_access_check_and_get_page(...). Because the function is a + * a variant of the methods described above, it will be able to + * handle entries with valid bit unset. + * + * TODO: Integrate more nicely memaccess with the rest of the + * function. + * TODO: Use the fault error in PAR_EL1 to avoid pointless + * translation. + */ if ( par ) { + paddr_t ipa; + unsigned int s1_perms; + /* * When memaccess is enabled, the translation GVA to MADDR may * have failed because of a permission fault. @@ -1455,20 +1479,48 @@ struct page_info *get_page_from_gva(struct vcpu *v, vaddr_t va, if ( p2m->mem_access_enabled ) return p2m_mem_access_check_and_get_page(va, flags, v); - dprintk(XENLOG_G_DEBUG, - "%pv: gvirt_to_maddr failed va=%#"PRIvaddr" flags=0x%lx par=%#"PRIx64"\n", - v, va, flags, par); - return NULL; + /* + * The software stage-1 table walk can still fail, e.g, if the + * GVA is not mapped. + */ + if ( !guest_walk_tables(v, va, &ipa, &s1_perms) ) + { + dprintk(XENLOG_G_DEBUG, + "%pv: Failed to walk page-table va %#"PRIvaddr"\n", v, va); + return NULL; + } + + mfn = p2m_lookup(d, gaddr_to_gfn(ipa), &t); + if ( mfn_eq(INVALID_MFN, mfn) || !p2m_is_ram(t) ) + return NULL; + + /* + * Check permission that are assumed by the caller. For instance + * in case of guestcopy, the caller assumes that the translated + * page can be accessed with the requested permissions. If this + * is not the case, we should fail. + * + * Please note that we do not check for the GV2M_EXEC + * permission. This is fine because the hardware-based translation + * instruction does not test for execute permissions. + */ + if ( (flags & GV2M_WRITE) && !(s1_perms & GV2M_WRITE) ) + return NULL; + + if ( (flags & GV2M_WRITE) && t != p2m_ram_rw ) + return NULL; } + else + mfn = maddr_to_mfn(maddr); - if ( !mfn_valid(maddr_to_mfn(maddr)) ) + if ( !mfn_valid(mfn) ) { dprintk(XENLOG_G_DEBUG, "%pv: Invalid MFN %#"PRI_mfn"\n", - v, mfn_x(maddr_to_mfn(maddr))); + v, mfn_x(mfn)); return NULL; } - page = mfn_to_page(maddr_to_mfn(maddr)); + page = mfn_to_page(mfn); ASSERT(page); if ( unlikely(!get_page(page, d)) ) From patchwork Tue Dec 4 20:26:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152860 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503530ljp; Tue, 4 Dec 2018 12:29:36 -0800 (PST) X-Google-Smtp-Source: AFSGD/U3NByi0QizGKXpxe+OV7jLL1XbkVECbXkaxBGCN8M8FM+rBGHLKCynyxb92sIgSUpkUutJ X-Received: by 2002:a25:ddc3:: with SMTP id u186-v6mr20455485ybg.440.1543955376265; Tue, 04 Dec 2018 12:29:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955376; cv=none; d=google.com; s=arc-20160816; b=JdPi7pmxlmM1XMe0jnVdpYkQMHC6vygQk3MNTbfppPIYEZ3AvOabUe3cvRjw/0s8bl 81i3UzO38DaLdEagyI/sn9rcWRSwTYlXAOI8ckdvriFRQ+2j0OZhZWdJidNj5CzMVMqT bSkX4OZB57Zn7qezEVzHcGuxeiOWS495Dq3DEXI8NNmPAJfDR67fYF6sMt4sP77s3Yds 86NbFUSTpsjw7jGxr0RRMoYmEar9imdFMRUel5lmCtmsVQ4QReMqDBQ1BIfgv2PAZSOA l4uDpcn/mYClgMVvH5ooCFUpHXlbbe02vOcLzWRmvqFZYzdm7DnbkzDI/UdjLAw88G/l ifaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=Bb/mCPfKxBJn52xwHMEUwR3F138ZgTRqdSQetFHOD1Y=; b=NCEYfrvXlSh7AimqnwkhMrEW2IGM2nqQrEadOh/iD1ItijkAytITkRhWbbFXccXRuu dSTvVhMxH9nLt/SirwWAcdT7hfNANC+ARRE7FSXVS/iNHoEr0ctTF/OgmxBUXl/4b0AR pr7RqzuaJ0skDR8zJjN6nG7ht5+RfWq/+ChaiQsT8wcbL83Y6erj3YAa9W6hK4G6bEmg EldW0HeNooeVGxjAKsUx8xe7RKvecaZIqIoFht9i1vcZNMA1jcNUblskGh5Z5v6+JCIE C3yITFUvicya0i+QehhHlqIhaC4HH5knY3Ug60C8wUsdc3OMg+XX+UFujlu3kgKEWOel pBwA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id l8-v6si9951978ybp.221.2018.12.04.12.29.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHy-00086x-1Y; Tue, 04 Dec 2018 20:27:26 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHw-00086b-Lb for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:24 +0000 X-Inumbo-ID: 02382768-f803-11e8-a67f-2bd172bc02dd Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 02382768-f803-11e8-a67f-2bd172bc02dd; Tue, 04 Dec 2018 20:27:24 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E7E51165C; Tue, 4 Dec 2018 12:27:23 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0813A3F614; Tue, 4 Dec 2018 12:27:22 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:40 +0000 Message-Id: <20181204202651.8836-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 06/17] xen/arm: p2m: Introduce a function to resolve translation fault X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently a Stage-2 translation fault could happen: 1) MMIO emulation 2) Another pCPU was modifying the P2M using Break-Before-Make 3) Guest Physical address is not mapped A follow-up patch will re-purpose the valid bit in an entry to generate translation fault. This would be used to do an action on each entry to track pages used for a given period. When receiving the translation fault, we would need to walk the pages table to find the faulting entry and then toggle valid bit. We can't use p2m_lookup() for this purpose as it only tells us the mapping exists. So this patch adds a new function to walk the page-tables and updates the entry. This function will also handle 2) as it also requires walking the page-table. The function is able to cope with both table and block entry having the validate bit unset. This gives flexibility to the function clearing the valid bits. To keep the algorithm simple, the fault will be propating one-level down. This will be repeated until a block entry has been reached. At the moment, there are no action done when reaching a block/page entry but setting the valid bit to 1. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Typoes - Add more comment - Skip clearing valid bit if it was already done - Move the prototype in p2m.h - Expand commit message --- xen/arch/arm/p2m.c | 142 ++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/traps.c | 10 ++-- xen/include/asm-arm/p2m.h | 2 + 3 files changed, 148 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 39680eeb6e..2706db3e67 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1035,6 +1035,148 @@ int p2m_set_entry(struct p2m_domain *p2m, return rc; } +/* Invalidate all entries in the table. The p2m should be write locked. */ +static void p2m_invalidate_table(struct p2m_domain *p2m, mfn_t mfn) +{ + lpae_t *table; + unsigned int i; + + ASSERT(p2m_is_write_locked(p2m)); + + table = map_domain_page(mfn); + + for ( i = 0; i < LPAE_ENTRIES; i++ ) + { + lpae_t pte = table[i]; + + /* + * Writing an entry can be expensive because it may involve + * cleaning the cache. So avoid updating the entry if the valid + * bit is already cleared. + */ + if ( !pte.p2m.valid ) + continue; + + pte.p2m.valid = 0; + + p2m_write_pte(&table[i], pte, p2m->clean_pte); + } + + unmap_domain_page(table); + + p2m->need_flush = true; +} + +/* + * Resolve any translation fault due to change in the p2m. This + * includes break-before-make and valid bit cleared. + */ +bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn) +{ + struct p2m_domain *p2m = p2m_get_hostp2m(d); + unsigned int level = 0; + bool resolved = false; + lpae_t entry, *table; + paddr_t addr = gfn_to_gaddr(gfn); + + /* Convenience aliases */ + const unsigned int offsets[4] = { + zeroeth_table_offset(addr), + first_table_offset(addr), + second_table_offset(addr), + third_table_offset(addr) + }; + + p2m_write_lock(p2m); + + /* This gfn is higher than the highest the p2m map currently holds */ + if ( gfn_x(gfn) > gfn_x(p2m->max_mapped_gfn) ) + goto out; + + table = p2m_get_root_pointer(p2m, gfn); + /* + * The table should always be non-NULL because the gfn is below + * p2m->max_mapped_gfn and the root table pages are always present. + */ + BUG_ON(table == NULL); + + /* + * Go down the page-tables until an entry has the valid bit unset or + * a block/page entry has been hit. + */ + for ( level = P2M_ROOT_LEVEL; level <= 3; level++ ) + { + int rc; + + entry = table[offsets[level]]; + + if ( level == 3 ) + break; + + /* Stop as soon as we hit an entry with the valid bit unset. */ + if ( !lpae_is_valid(entry) ) + break; + + rc = p2m_next_level(p2m, true, level, &table, offsets[level]); + if ( rc == GUEST_TABLE_MAP_FAILED ) + goto out_unmap; + else if ( rc != GUEST_TABLE_NORMAL_PAGE ) + break; + } + + /* + * If the valid bit of the entry is set, it means someone was playing with + * the Stage-2 page table. Nothing to do and mark the fault as resolved. + */ + if ( lpae_is_valid(entry) ) + { + resolved = true; + goto out_unmap; + } + + /* + * The valid bit is unset. If the entry is still not valid then the fault + * cannot be resolved, exit and report it. + */ + if ( !p2m_is_valid(entry) ) + goto out_unmap; + + /* + * Now we have an entry with valid bit unset, but still valid from + * the P2M point of view. + * + * If an entry is pointing to a table, each entry of the table will + * have there valid bit cleared. This allows a function to clear the + * full p2m with just a couple of write. The valid bit will then be + * propagated on the fault. + * If an entry is pointing to a block/page, no work to do for now. + */ + if ( lpae_is_table(entry, level) ) + p2m_invalidate_table(p2m, lpae_get_mfn(entry)); + + /* + * Now that the work on the entry is done, set the valid bit to prevent + * another fault on that entry. + */ + resolved = true; + entry.p2m.valid = 1; + + p2m_write_pte(table + offsets[level], entry, p2m->clean_pte); + + /* + * No need to flush the TLBs as the modified entry had the valid bit + * unset. + */ + +out_unmap: + unmap_domain_page(table); + +out: + p2m_write_unlock(p2m); + + return resolved; +} + static inline int p2m_insert_mapping(struct domain *d, gfn_t start_gfn, unsigned long nr, diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 94fe1a6da7..b00d0b8e1e 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1893,7 +1893,6 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, vaddr_t gva; paddr_t gpa; uint8_t fsc = xabt.fsc & ~FSC_LL_MASK; - mfn_t mfn; bool is_data = (hsr.ec == HSR_EC_DATA_ABORT_LOWER_EL); /* @@ -1972,12 +1971,11 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, } /* - * The PT walk may have failed because someone was playing - * with the Stage-2 page table. Walk the Stage-2 PT to check - * if the entry exists. If it's the case, return to the guest + * First check if the translation fault can be resolved by the + * P2M subsystem. If that's the case nothing else to do. */ - mfn = gfn_to_mfn(current->domain, gaddr_to_gfn(gpa)); - if ( !mfn_eq(mfn, INVALID_MFN) ) + if ( p2m_resolve_translation_fault(current->domain, + gaddr_to_gfn(gpa)) ) return; if ( is_data && try_map_mmio(gaddr_to_gfn(gpa)) ) diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index 4fe78d39a5..13f7a27c38 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -226,6 +226,8 @@ int p2m_set_entry(struct p2m_domain *p2m, p2m_type_t t, p2m_access_t a); +bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn); + /* Clean & invalidate caches corresponding to a region of guest address space */ int p2m_cache_flush(struct domain *d, gfn_t start, unsigned long nr); From patchwork Tue Dec 4 20:26:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152859 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503529ljp; Tue, 4 Dec 2018 12:29:36 -0800 (PST) X-Google-Smtp-Source: AFSGD/W85x4wj1aaDOZp+ZfUoFZbqr+/WdexrTKCycSkNVsRylKXa6314Uikcqe8ny9GVLKnFPvt X-Received: by 2002:a81:e247:: with SMTP id z7mr21282070ywl.461.1543955376191; Tue, 04 Dec 2018 12:29:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955376; cv=none; d=google.com; s=arc-20160816; b=u2LU6J9QNq8ywg5dpfVziSxKYi6Q1cN/mMAADj+O2xkuN+wYPSV3sxtTU96IGCy7Ru qwc/JJdUddiQkkGt0ATpgRqSCKwcjuQsWbHUncdfm0Y/0+WI3VBQG47VtsCeCzMLoIcp XDg6x4VtALvmceOaqNOYvBBvhCye51wwdR8uN38ck+f6eOjWutMF+VAoRf1cuOcoasmx RwSghe1rBeAs78KrPBCBVFQ+NAoM7GlNQmqj0VfUuxRrpvCbR4za9xebw4A/AWfovN04 W10On1jfmwrr+FQjTbFRPd8jcWyygEDz6YwKbf+BTjjGZ6Li84NedWQ6wqQLZhvc/Ibt a2qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=NbuEaCJKkNzf8fqvOd0WoXIdeah20yU7mmiwTLBxUcY=; b=jS1YpsUEFVR57nz2i3tt75gHDZQzZltD7dKNOLGnDl4lInEWDgjwLtRD3YxCYjWzyn UdIMy50bGsDCI+HwYVojmWORQ7gZPPssm70455UWa5bkQL2xiHh1Mn7DoJCM4xFn7l5/ nfQf1LjE2bbzqdUkAGzwttUTcrEXQJbxVH4GJKCXPbK72T9Utszlqc/smzqRQw2sU7vB hFO1WOI6+JqR3UplEPF/GmF0QRD0NRYJeC8siBWiKUfuRN8hvGc2+M+HPcURoNvwS/3J 6eycTlbQ49uSEjCDG19glMt04dF5yBF1AAIl3o9PxdKwxQBGi8mIpW9DXJ4eCczdcADe lJzg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id m204-v6si10877357ybb.61.2018.12.04.12.29.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI0-00088A-RD; Tue, 04 Dec 2018 20:27:28 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHy-00087L-TL for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:26 +0000 X-Inumbo-ID: 02f81028-f803-11e8-9c06-1392136fa650 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 02f81028-f803-11e8-9c06-1392136fa650; Tue, 04 Dec 2018 20:27:25 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EE1F915BE; Tue, 4 Dec 2018 12:27:24 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 318003F614; Tue, 4 Dec 2018 12:27:24 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:41 +0000 Message-Id: <20181204202651.8836-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 07/17] xen/arm: vcpreg: Add wrappers to handle co-proc access trapped by HCR_EL2.TVM X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will require to emulate some accesses to some co-processors registers trapped by HCR_EL2.TVM. When set, all NS EL1 writes to the virtual memory control registers will be trapped to the hypervisor. This patch adds the infrastructure to passthrough the access to host registers. For convenience a bunch of helpers have been added to generate the different helpers. Note that HCR_EL2.TVM will be set in a follow-up patch dynamically. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Add missing include vreg.h - Fixup mask TMV_REG32_COMBINED - Update comments --- xen/arch/arm/vcpreg.c | 149 +++++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/cpregs.h | 1 + 2 files changed, 150 insertions(+) diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index 7b783e4bcc..550c25ec3f 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -23,8 +23,129 @@ #include #include #include +#include #include +/* + * Macros to help generating helpers for registers trapped when + * HCR_EL2.TVM is set. + * + * Note that it only traps NS write access from EL1. + * + * - TVM_REG() should not be used outside of the macros. It is there to + * help defining TVM_REG32() and TVM_REG64() + * - TVM_REG32(regname, xreg) and TVM_REG64(regname, xreg) are used to + * resp. generate helper accessing 32-bit and 64-bit register. "regname" + * is the Arm32 name and "xreg" the Arm64 name. + * - TVM_REG32_COMBINED(lowreg, hireg, xreg) are used to generate a + * pair of register sharing the same Arm64 register, but are 2 distinct + * Arm32 registers. "lowreg" and "hireg" contains the name for on Arm32 + * registers, "xreg" contains the name for the combined register on Arm64. + * The definition of "lowreg" and "higreg" match the Armv8 specification, + * this means "lowreg" is an alias to xreg[31:0] and "high" is an alias to + * xreg[63:32]. + * + */ + +/* The name is passed from the upper macro to workaround macro expansion. */ +#define TVM_REG(sz, func, reg...) \ +static bool func(struct cpu_user_regs *regs, uint##sz##_t *r, bool read) \ +{ \ + GUEST_BUG_ON(read); \ + WRITE_SYSREG##sz(*r, reg); \ + \ + return true; \ +} + +#define TVM_REG32(regname, xreg) TVM_REG(32, vreg_emulate_##regname, xreg) +#define TVM_REG64(regname, xreg) TVM_REG(64, vreg_emulate_##regname, xreg) + +#ifdef CONFIG_ARM_32 +#define TVM_REG32_COMBINED(lowreg, hireg, xreg) \ + /* Use TVM_REG directly to workaround macro expansion. */ \ + TVM_REG(32, vreg_emulate_##lowreg, lowreg) \ + TVM_REG(32, vreg_emulate_##hireg, hireg) + +#else /* CONFIG_ARM_64 */ +#define TVM_REG32_COMBINED(lowreg, hireg, xreg) \ +static bool vreg_emulate_##xreg(struct cpu_user_regs *regs, uint32_t *r, \ + bool read, bool hi) \ +{ \ + register_t reg = READ_SYSREG(xreg); \ + \ + GUEST_BUG_ON(read); \ + if ( hi ) /* reg[63:32] is AArch32 register hireg */ \ + { \ + reg &= GENMASK(31, 0); \ + reg |= ((uint64_t)*r) << 32; \ + } \ + else /* reg[31:0] is AArch32 register lowreg. */ \ + { \ + reg &= GENMASK(63, 32); \ + reg |= *r; \ + } \ + WRITE_SYSREG(reg, xreg); \ + \ + return true; \ +} \ + \ +static bool vreg_emulate_##lowreg(struct cpu_user_regs *regs, uint32_t *r, \ + bool read) \ +{ \ + return vreg_emulate_##xreg(regs, r, read, false); \ +} \ + \ +static bool vreg_emulate_##hireg(struct cpu_user_regs *regs, uint32_t *r, \ + bool read) \ +{ \ + return vreg_emulate_##xreg(regs, r, read, true); \ +} +#endif + +/* Defining helpers for emulating co-processor registers. */ +TVM_REG32(SCTLR, SCTLR_EL1) +/* + * AArch32 provides two way to access TTBR* depending on the access + * size, whilst AArch64 provides one way. + * + * When using AArch32, for simplicity, use the same access size as the + * guest. + */ +#ifdef CONFIG_ARM_32 +TVM_REG32(TTBR0_32, TTBR0_32) +TVM_REG32(TTBR1_32, TTBR1_32) +#else +TVM_REG32(TTBR0_32, TTBR0_EL1) +TVM_REG32(TTBR1_32, TTBR1_EL1) +#endif +TVM_REG64(TTBR0, TTBR0_EL1) +TVM_REG64(TTBR1, TTBR1_EL1) +/* AArch32 registers TTBCR and TTBCR2 share AArch64 register TCR_EL1. */ +TVM_REG32_COMBINED(TTBCR, TTBCR2, TCR_EL1) +TVM_REG32(DACR, DACR32_EL2) +TVM_REG32(DFSR, ESR_EL1) +TVM_REG32(IFSR, IFSR32_EL2) +/* AArch32 registers DFAR and IFAR shares AArch64 register FAR_EL1. */ +TVM_REG32_COMBINED(DFAR, IFAR, FAR_EL1) +TVM_REG32(ADFSR, AFSR0_EL1) +TVM_REG32(AIFSR, AFSR1_EL1) +/* AArch32 registers MAIR0 and MAIR1 share AArch64 register MAIR_EL1. */ +TVM_REG32_COMBINED(MAIR0, MAIR1, MAIR_EL1) +/* AArch32 registers AMAIR0 and AMAIR1 share AArch64 register AMAIR_EL1. */ +TVM_REG32_COMBINED(AMAIR0, AMAIR1, AMAIR_EL1) +TVM_REG32(CONTEXTIDR, CONTEXTIDR_EL1) + +/* Macro to generate easily case for co-processor emulation. */ +#define GENERATE_CASE(reg, sz) \ + case HSR_CPREG##sz(reg): \ + { \ + bool res; \ + \ + res = vreg_emulate_cp##sz(regs, hsr, vreg_emulate_##reg); \ + ASSERT(res); \ + break; \ + } + void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) { const struct hsr_cp32 cp32 = hsr.cp32; @@ -65,6 +186,31 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) break; /* + * HCR_EL2.TVM + * + * ARMv8 (DDI 0487D.a): Table D1-38 + */ + GENERATE_CASE(SCTLR, 32) + GENERATE_CASE(TTBR0_32, 32) + GENERATE_CASE(TTBR1_32, 32) + GENERATE_CASE(TTBCR, 32) + GENERATE_CASE(TTBCR2, 32) + GENERATE_CASE(DACR, 32) + GENERATE_CASE(DFSR, 32) + GENERATE_CASE(IFSR, 32) + GENERATE_CASE(DFAR, 32) + GENERATE_CASE(IFAR, 32) + GENERATE_CASE(ADFSR, 32) + GENERATE_CASE(AIFSR, 32) + /* AKA PRRR */ + GENERATE_CASE(MAIR0, 32) + /* AKA NMRR */ + GENERATE_CASE(MAIR1, 32) + GENERATE_CASE(AMAIR0, 32) + GENERATE_CASE(AMAIR1, 32) + GENERATE_CASE(CONTEXTIDR, 32) + + /* * MDCR_EL2.TPM * * ARMv7 (DDI 0406C.b): B1.14.17 @@ -193,6 +339,9 @@ void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr) return inject_undef_exception(regs, hsr); break; + GENERATE_CASE(TTBR0, 64) + GENERATE_CASE(TTBR1, 64) + /* * CPTR_EL2.T{0..9,12..13} * diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index 97a3c6f1c1..8fd344146e 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -140,6 +140,7 @@ /* CP15 CR2: Translation Table Base and Control Registers */ #define TTBCR p15,0,c2,c0,2 /* Translation Table Base Control Register */ +#define TTBCR2 p15,0,c2,c0,3 /* Translation Table Base Control Register 2 */ #define TTBR0 p15,0,c2 /* Translation Table Base Reg. 0 */ #define TTBR1 p15,1,c2 /* Translation Table Base Reg. 1 */ #define HTTBR p15,4,c2 /* Hyp. Translation Table Base Register */ From patchwork Tue Dec 4 20:26:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152848 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503249ljp; Tue, 4 Dec 2018 12:29:15 -0800 (PST) X-Google-Smtp-Source: AFSGD/URFVZx/Za0WHDiYBA3x0Tox8VS8hWV/x6nWsvxtcgyEEL3bGQ7q8m5OL0TivS5StTI3MSD X-Received: by 2002:a25:8e0c:: with SMTP id p12mr4920033ybl.127.1543955355228; Tue, 04 Dec 2018 12:29:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955355; cv=none; d=google.com; s=arc-20160816; b=g66K3+KOjoGgn0y4Ygn09N/S48kLDPJ2e3M+EvdS3IGrXoyHVwjMYDyZUX91zoN4dO leTO7tMBvBFA7y05f0/rruOibPHrEFf1v9HYRywqX77eq/XfqBalnq0UOxnCClZuKUQ3 Xgz0Dr6lgPyL2psnDeO5oyU/CWJkJQoQM+roHgTl+PN0EYkjSP97a7L/To7NEzaLXWgY AzLZ1op8x5LmEoqgWcuUmvB5KrqgHg6YTxpsxpH4QSm0M0QGl9b8TGtgqV84Z47IaEGP 23ienzJXznlNMbDzSp8gfZcpXXVRUU5lsv4Ofef8pMxFYL70pRHtzYvMo6dnekerZ/gZ 0oug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=TmkIxKLRSpJZMhU+QPf0in+WlSAESKcnR2kh+8bN3ds=; b=VRzhPjPboPoeUfyh6wxgItxYHIMcYo1GbmlFF+F/CDTaO8+zDdZYVrIynVSPoo1zeu sVheWPhsuqGa+Tm+5m51tL9ohgUYX4fPwRP9HZ9vj11dLGyKyI7SB9kr1Z0bhLjFHQ/h MtlC5jtU6w3BtT0aw9dN80a5rMA5xMSq+Y45Pq5s8XT983Q2u7YFztfiXXnH2rtzjsGB qHwzWOWZSpIcwFKpfImzZAuwkFM0qBsLIxSFgCx4UNxSRMGq0Aq2O1T63o90sCrEMPDR yZuOEeu1hRbUQF0trbJDohxmVIx6nkm+IdATRMFY8C/4mN3lVOHqb90eXefY18+j1z6S bKYA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b66si10678913ywd.460.2018.12.04.12.29.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI0-000881-HM; Tue, 04 Dec 2018 20:27:28 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHy-00087K-Sr for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:26 +0000 X-Inumbo-ID: 036f5804-f803-11e8-a7ed-d75a0e0d9f14 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 036f5804-f803-11e8-a7ed-d75a0e0d9f14; Tue, 04 Dec 2018 20:27:26 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00839165C; Tue, 4 Dec 2018 12:27:26 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 378383F614; Tue, 4 Dec 2018 12:27:25 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:42 +0000 Message-Id: <20181204202651.8836-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 08/17] xen/arm: vsysreg: Add wrapper to handle sysreg access trapped by HCR_EL2.TVM X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will require to emulate some accesses to system registers trapped by HCR_EL2.TVM. When set, all NS EL1 writes to the virtual memory control registers will be trapped to the hypervisor. This patch adds the infrastructure to passthrough the access to the host registers. Note that HCR_EL2.TVM will be set in a follow-up patch dynamically. Signed-off-by: Julien Grall --- Changes in v2: - Add missing include vreg.h - Update documentation reference to the lastest one --- xen/arch/arm/arm64/vsysreg.c | 58 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 6e60824572..16ac9c344a 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -21,8 +21,49 @@ #include #include #include +#include #include +/* + * Macro to help generating helpers for registers trapped when + * HCR_EL2.TVM is set. + * + * Note that it only traps NS write access from EL1. + */ +#define TVM_REG(reg) \ +static bool vreg_emulate_##reg(struct cpu_user_regs *regs, \ + uint64_t *r, bool read) \ +{ \ + GUEST_BUG_ON(read); \ + WRITE_SYSREG64(*r, reg); \ + \ + return true; \ +} + +/* Defining helpers for emulating sysreg registers. */ +TVM_REG(SCTLR_EL1) +TVM_REG(TTBR0_EL1) +TVM_REG(TTBR1_EL1) +TVM_REG(TCR_EL1) +TVM_REG(ESR_EL1) +TVM_REG(FAR_EL1) +TVM_REG(AFSR0_EL1) +TVM_REG(AFSR1_EL1) +TVM_REG(MAIR_EL1) +TVM_REG(AMAIR_EL1) +TVM_REG(CONTEXTIDR_EL1) + +/* Macro to generate easily case for co-processor emulation */ +#define GENERATE_CASE(reg) \ + case HSR_SYSREG_##reg: \ + { \ + bool res; \ + \ + res = vreg_emulate_sysreg64(regs, hsr, vreg_emulate_##reg); \ + ASSERT(res); \ + break; \ + } + void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { @@ -44,6 +85,23 @@ void do_sysreg(struct cpu_user_regs *regs, break; /* + * HCR_EL2.TVM + * + * ARMv8 (DDI 0487D.a): Table D1-38 + */ + GENERATE_CASE(SCTLR_EL1) + GENERATE_CASE(TTBR0_EL1) + GENERATE_CASE(TTBR1_EL1) + GENERATE_CASE(TCR_EL1) + GENERATE_CASE(ESR_EL1) + GENERATE_CASE(FAR_EL1) + GENERATE_CASE(AFSR0_EL1) + GENERATE_CASE(AFSR1_EL1) + GENERATE_CASE(MAIR_EL1) + GENERATE_CASE(AMAIR_EL1) + GENERATE_CASE(CONTEXTIDR_EL1) + + /* * MDCR_EL2.TDRA * * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 From patchwork Tue Dec 4 20:26:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152850 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503324ljp; Tue, 4 Dec 2018 12:29:20 -0800 (PST) X-Google-Smtp-Source: AFSGD/UQ5aR73xkw7pPhh3HXN6VsyAiYprsslRR0xHBf2PIahMRrwhVifqGAs+qRnaPd+szjn9r6 X-Received: by 2002:a81:5744:: with SMTP id l65mr1869233ywb.91.1543955360820; Tue, 04 Dec 2018 12:29:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955360; cv=none; d=google.com; s=arc-20160816; b=1CKue5L24KulSwYb4U5m8c03o0tIbV3OXGSdDtOYGA71CViaga21DU+7MrjlbtS1xD a4KUHDxAIkhqu0Rdk7YMwv3Ko+c3m02vfPYZ420CUqLHsTo8WRwzuZCBeCnJVm2QT/RQ xRz9ZiJRxMQgB3riQwMNdFStiIokE/X0fKHl8SF1OH6zdnHlE7X6u1R9mItt+MgmJlHh jvSJF3X8XSirmU2fKoz0tZCGDtKFxN0FjdaPqRPxsNbPswJy2n2sBJIFrOG+FADshL4a aVqo8ntRoOnO87kxqLC73jkXJO2d8oKjm6f7mJd60Xamoxj0kPSFwpOD+BlL0RVp3Jd+ GCGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=QwSdEvsEGngWvKE294h9+mdVc7hYn2MX17dbvCGUysU=; b=xUwKl24Nj5R+I8Nu+22dlsEsinHCKjf79oHSAUYNPoXMCh7l5pjFyzaZ8uO7AdOsgV hGAyNgXVGITqRd9UmAiNOG6XS2rOwc0wGv8lSY1htEb2Ffd7jSHGNSn/RW7qzGDRBzIb if6q0YvPimh33UnBJQ+tW0nGq1GIpNBKU16ypoUec1GwmQZIdvfUIvbxvrAHpAo+ZiSe DBHj/ZZiVkenomtI12HLMwO9uiK2LrUnIMUPfrTSw1PQvKBGZrEV0fxzk41/+sMpb5sV P85gWcTzWJksoRRoBNx5JYW8PP5spPGPhj6iJ+dsSqhd9p2v/EQNZI0Oc/r3FTc3hBEd SUKA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id c10-v6si10226516ybm.200.2018.12.04.12.29.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI1-00088K-66; Tue, 04 Dec 2018 20:27:29 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI0-00087r-Be for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:28 +0000 X-Inumbo-ID: 040c01d6-f803-11e8-8f66-2710c3a051a6 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 040c01d6-f803-11e8-8f66-2710c3a051a6; Tue, 04 Dec 2018 20:27:27 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 06C0515BE; Tue, 4 Dec 2018 12:27:27 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3E4623F614; Tue, 4 Dec 2018 12:27:26 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:43 +0000 Message-Id: <20181204202651.8836-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 09/17] xen/arm: Rework p2m_cache_flush to take a range [begin, end) X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function will be easier to re-use in a follow-up patch if you have only the begin and end. At the same time, rename the function to reflect the change in the prototype. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Add Stefano's reviewed-by --- xen/arch/arm/domctl.c | 2 +- xen/arch/arm/p2m.c | 3 +-- xen/include/asm-arm/p2m.h | 7 +++++-- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/domctl.c b/xen/arch/arm/domctl.c index 4587c75826..c10f568aad 100644 --- a/xen/arch/arm/domctl.c +++ b/xen/arch/arm/domctl.c @@ -61,7 +61,7 @@ long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, if ( e < s ) return -EINVAL; - return p2m_cache_flush(d, _gfn(s), domctl->u.cacheflush.nr_pfns); + return p2m_cache_flush_range(d, _gfn(s), _gfn(e)); } case XEN_DOMCTL_bind_pt_irq: { diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 2706db3e67..836157292c 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1514,10 +1514,9 @@ int relinquish_p2m_mapping(struct domain *d) return rc; } -int p2m_cache_flush(struct domain *d, gfn_t start, unsigned long nr) +int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) { struct p2m_domain *p2m = p2m_get_hostp2m(d); - gfn_t end = gfn_add(start, nr); gfn_t next_gfn; p2m_type_t t; unsigned int order; diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index 13f7a27c38..5858f97e9c 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -228,8 +228,11 @@ int p2m_set_entry(struct p2m_domain *p2m, bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn); -/* Clean & invalidate caches corresponding to a region of guest address space */ -int p2m_cache_flush(struct domain *d, gfn_t start, unsigned long nr); +/* + * Clean & invalidate caches corresponding to a region [start,end) of guest + * address space. + */ +int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end); /* * Map a region in the guest p2m with a specific p2m type. From patchwork Tue Dec 4 20:26:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152851 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503368ljp; Tue, 4 Dec 2018 12:29:25 -0800 (PST) X-Google-Smtp-Source: AFSGD/WIz7PhvJC9Mps8f7f6p97gXfm7cE03KOESbcdMiu8WLipyIjcUWaP/L33lVxEdTtII9sep X-Received: by 2002:a81:451:: with SMTP id 78mr21662763ywe.139.1543955364890; Tue, 04 Dec 2018 12:29:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955364; cv=none; d=google.com; s=arc-20160816; b=s444sCkk19ajw64n2xWZpcckZ5Rf+HwjCFAXsyr9OuTEz8Ndry0XfZoTtwG9TMUs5P uz1PE01kHdsCPHUBsB4YZ70Sf9PU0FngYsrUHDzsXu2CcmrOfFTo0t2z0xUU1UFopwVi ZQEZy3UmfJt/J5Nz7kOF6GlHbRCqrnIEiX3SS0UcDTTIhckzN5xGklHXwx0H/fM0oNoC ON4G+RiWngB6pY6DUNha0O+FO5M31o0Srxqk3Vw+1yLYp2uchou477yypnqa9xZEswkb d+RVtquyHgvu+n4QE7cKNL27U+R8rIskHMWc67gpUPZ3mciCkJTWfPlkWDa2kQJfkYXL zpUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=HsMvb/Ii0uIoym2gvOPgi4FtJwEAK7dM/XPBAO3gH7Y=; b=n/Eq0sOoZtzaVqr+/7UvaQRvmtuw0JlKOKahI8sZOq7u9ft9uJ/0MwTGW6f+fxIyWj xIa9JvvtzILJF55G+DVytU5IiLsvHWmLJvIA9R2p2uKX7SL6LOT0/lBdt7DTwUvWA3Zg LM4j/Z4sW31hQiw5A507CHuBEUPyaDaye4eQKlfqXGETdVvmpKOTnocPBSTWISvxincC pZJ6jKXP0/qI3WFonVBzQhPX92SYl9rAQDr2mT3SToDX3gFzu4p/T4wtvSBdgSOu/Azz 0BxZ4kjD5rRKHEmitZM5xzIeslF9nisbMDF6PvF9zvr2DxV+oiqxJy6sm2PLz8XnsxcK 9znQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id s203si10796343yws.274.2018.12.04.12.29.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI2-00089J-H8; Tue, 04 Dec 2018 20:27:30 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI1-00088W-J4 for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:29 +0000 X-Inumbo-ID: 04aaedc8-f803-11e8-ad94-f3cbc4eb1e68 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 04aaedc8-f803-11e8-ad94-f3cbc4eb1e68; Tue, 04 Dec 2018 20:27:28 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0CFA0165C; Tue, 4 Dec 2018 12:27:28 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 449AA3F614; Tue, 4 Dec 2018 12:27:27 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:44 +0000 Message-Id: <20181204202651.8836-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 10/17] xen/arm: p2m: Allow to flush cache on any RAM region X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently, we only allow to flush cache on regions mapped as p2m_ram_{rw,ro}. There are no real problem in cache flushing any RAM regions such as grants and foreign mapping. Therefore, relax the check to allow flushing the cache on any RAM region. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Fix typoes - Add Stefano's reviewed-by --- xen/arch/arm/p2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 836157292c..4e0ddbf70b 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1539,7 +1539,7 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) next_gfn = gfn_next_boundary(start, order); /* Skip hole and non-RAM page */ - if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_ram(t) ) + if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_any_ram(t) ) continue; /* XXX: Implement preemption */ From patchwork Tue Dec 4 20:26:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152849 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503297ljp; Tue, 4 Dec 2018 12:29:19 -0800 (PST) X-Google-Smtp-Source: AFSGD/XCxH9bjG6lG4E+MCV6WFcjWilTUmWlDfpnPXMqezoN5np7K/Nzrh9zdRRS/F+hUGYUAXg8 X-Received: by 2002:a0d:d945:: with SMTP id b66mr21072967ywe.318.1543955359015; Tue, 04 Dec 2018 12:29:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955359; cv=none; d=google.com; s=arc-20160816; b=0V+80hdP+d+d0Yn6eXbKUDwjdboJotsvC/M+bQg9BN3OSuvl9hOy1BKMSlEz8zjJyX G1260KFa5yg7PhE0qw1p0a3pkxUhMK1mFdeoe2gh/6fsrUKRKZHspicl+wJTqcrkzh4s pD252mvFkQUmePAPBBw4wQMURStGp3uKaMsjiwbOVtLul2JvICrz7y6zIzABN78pTvKT rMCI5PsN3/1RD+LXONFNZY9ua15OfYpNv2crgTZOpo+PS4c9W2foBkV1bOumhjcfZZnw xx5lxZHGbNcaV4S4e5oRn50NOxiAfV/canYGM03oHC2Hd7LtJnxtoYudc//DYwC5M3Wi Y7SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=Yl8guLWQt1dCwSLq8HwpGeA7Di1FT0mm7WXsPuIm8j0=; b=Rn5saS5nWWc3SY1VFN0EOJWzsjI243TsVl9m3f60RACxJBxVLukbPws1iOjw43oE3c yoM4vUSrr4bze/l4aHkhcvjgW+2r6Pvy+PBwrFXx2rlICayPQw+W28gkDeZxpA8yV4YP ypvRkz1b2a7xyGewNHuaxkp/lJSoCsowhtNzZghNrEnFF4whMFW/ox1mbNA4t6LCcwqH wpV164m2xQGPo8dYtUP6EgJewgfLUYqeplZkC4QD1da48d5tpb0Oxdhundvd2HZAbmpK JOIhYsgkQOw0RCIGECrjr20TDA4twmXZpQgVOXQk68l4c176c1ySNG8BfrMUp6ACZMj+ GRVA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 140si10249921ywk.118.2018.12.04.12.29.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI4-00089t-00; Tue, 04 Dec 2018 20:27:31 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI2-00089P-Ql for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:30 +0000 X-Inumbo-ID: 057c8202-f803-11e8-88cd-4fc698895070 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 057c8202-f803-11e8-88cd-4fc698895070; Tue, 04 Dec 2018 20:27:29 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5A90B15BE; Tue, 4 Dec 2018 12:27:29 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4B4C53F614; Tue, 4 Dec 2018 12:27:28 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:45 +0000 Message-Id: <20181204202651.8836-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 11/17] xen/arm: p2m: Extend p2m_get_entry to return the value of bit[0] (valid bit) X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, Tamas K Lengyel , Razvan Cojocaru MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" With the recent changes, a P2M entry may be populated but may as not valid. In some situation, it would be useful to know whether the entry has been marked available to guest in order to perform a specific action. So extend p2m_get_entry to return the value of bit[0] (valid bit). Signed-off-by: Julien Grall Acked-by: Razvan Cojocaru Reviewed-by: Stefano Stabellini --- Changes in v2: - Don't use _valid --- xen/arch/arm/mem_access.c | 6 +++--- xen/arch/arm/p2m.c | 18 ++++++++++++++---- xen/include/asm-arm/p2m.h | 3 ++- 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/mem_access.c b/xen/arch/arm/mem_access.c index f911937ccf..db49372a2c 100644 --- a/xen/arch/arm/mem_access.c +++ b/xen/arch/arm/mem_access.c @@ -71,7 +71,7 @@ static int __p2m_get_mem_access(struct domain *d, gfn_t gfn, * No setting was found in the Radix tree. Check if the * entry exists in the page-tables. */ - mfn_t mfn = p2m_get_entry(p2m, gfn, NULL, NULL, NULL); + mfn_t mfn = p2m_get_entry(p2m, gfn, NULL, NULL, NULL, NULL); if ( mfn_eq(mfn, INVALID_MFN) ) return -ESRCH; @@ -200,7 +200,7 @@ p2m_mem_access_check_and_get_page(vaddr_t gva, unsigned long flag, * We had a mem_access permission limiting the access, but the page type * could also be limiting, so we need to check that as well. */ - mfn = p2m_get_entry(p2m, gfn, &t, NULL, NULL); + mfn = p2m_get_entry(p2m, gfn, &t, NULL, NULL, NULL); if ( mfn_eq(mfn, INVALID_MFN) ) goto err; @@ -406,7 +406,7 @@ long p2m_set_mem_access(struct domain *d, gfn_t gfn, uint32_t nr, gfn = gfn_next_boundary(gfn, order) ) { p2m_type_t t; - mfn_t mfn = p2m_get_entry(p2m, gfn, &t, NULL, &order); + mfn_t mfn = p2m_get_entry(p2m, gfn, &t, NULL, &order, NULL); if ( !mfn_eq(mfn, INVALID_MFN) ) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 4e0ddbf70b..c713226561 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -298,10 +298,14 @@ static int p2m_next_level(struct p2m_domain *p2m, bool read_only, * * If the entry is not present, INVALID_MFN will be returned and the * page_order will be set according to the order of the invalid range. + * + * valid will contain the value of bit[0] (e.g valid bit) of the + * entry. */ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, p2m_type_t *t, p2m_access_t *a, - unsigned int *page_order) + unsigned int *page_order, + bool *valid) { paddr_t addr = gfn_to_gaddr(gfn); unsigned int level = 0; @@ -326,6 +330,9 @@ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, *t = p2m_invalid; + if ( valid ) + *valid = false; + /* XXX: Check if the mapping is lower than the mapped gfn */ /* This gfn is higher than the highest the p2m map currently holds */ @@ -371,6 +378,9 @@ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, * to the GFN. */ mfn = mfn_add(mfn, gfn_x(gfn) & ((1UL << level_orders[level]) - 1)); + + if ( valid ) + *valid = lpae_is_valid(entry); } out_unmap: @@ -389,7 +399,7 @@ mfn_t p2m_lookup(struct domain *d, gfn_t gfn, p2m_type_t *t) struct p2m_domain *p2m = p2m_get_hostp2m(d); p2m_read_lock(p2m); - mfn = p2m_get_entry(p2m, gfn, t, NULL, NULL); + mfn = p2m_get_entry(p2m, gfn, t, NULL, NULL, NULL); p2m_read_unlock(p2m); return mfn; @@ -1471,7 +1481,7 @@ int relinquish_p2m_mapping(struct domain *d) for ( ; gfn_x(start) < gfn_x(end); start = gfn_next_boundary(start, order) ) { - mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order); + mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order, NULL); count++; /* @@ -1534,7 +1544,7 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) for ( ; gfn_x(start) < gfn_x(end); start = next_gfn ) { - mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order); + mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order, NULL); next_gfn = gfn_next_boundary(start, order); diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index 5858f97e9c..7c1d930b1d 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -213,7 +213,8 @@ mfn_t p2m_lookup(struct domain *d, gfn_t gfn, p2m_type_t *t); */ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, p2m_type_t *t, p2m_access_t *a, - unsigned int *page_order); + unsigned int *page_order, + bool *valid); /* * Direct set a p2m entry: only for use by the P2M code. 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[192.237.175.120]) by mx.google.com with ESMTPS id s206si6135759ybc.235.2018.12.04.12.29.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI5-0008DZ-WE; Tue, 04 Dec 2018 20:27:33 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI4-00089v-24 for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:32 +0000 X-Inumbo-ID: 06120688-f803-11e8-8189-6bdc23c5bb6b Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 06120688-f803-11e8-8189-6bdc23c5bb6b; Tue, 04 Dec 2018 20:27:30 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 60A7F165C; Tue, 4 Dec 2018 12:27:30 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 984AF3F614; Tue, 4 Dec 2018 12:27:29 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:46 +0000 Message-Id: <20181204202651.8836-13-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 12/17] xen/arm: traps: Rework leave_hypervisor_tail X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function leave_hypervisor_tail is called before each return to the guest vCPU. It has two main purposes: 1) Process physical CPU work (e.g rescheduling) if required 2) Prepare the physical CPU to run the guest vCPU 2) will always be done once we finished to process physical CPU work. At the moment, it is done part of the last iterations of 1) making adding some extra indentation in the code. This could be streamlined by moving out 2) of the loop. At the same time, 1) is moved in a separate function making more obvious All those changes will help a follow-up patch where we would want to introduce some vCPU work before returning to the guest vCPU. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Patch added --- xen/arch/arm/traps.c | 61 ++++++++++++++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index b00d0b8e1e..02665cc7b4 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2241,36 +2241,12 @@ void do_trap_fiq(struct cpu_user_regs *regs) gic_interrupt(regs, 1); } -void leave_hypervisor_tail(void) +static void check_for_pcpu_work(void) { - while (1) - { - local_irq_disable(); - if ( !softirq_pending(smp_processor_id()) ) - { - vgic_sync_to_lrs(); - - /* - * If the SErrors handle option is "DIVERSE", we have to prevent - * slipping the hypervisor SError to guest. In this option, before - * returning from trap, we have to synchronize SErrors to guarantee - * that the pending SError would be caught in hypervisor. - * - * If option is NOT "DIVERSE", SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT - * will be set to cpu_hwcaps. This means we can use the alternative - * to skip synchronizing SErrors for other SErrors handle options. - */ - SYNCHRONIZE_SERROR(SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT); - - /* - * The hypervisor runs with the workaround always present. - * If the guest wants it disabled, so be it... - */ - if ( needs_ssbd_flip(current) ) - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 0, NULL); + ASSERT(!local_irq_is_enabled()); - return; - } + while ( softirq_pending(smp_processor_id()) ) + { local_irq_enable(); do_softirq(); /* @@ -2278,9 +2254,38 @@ void leave_hypervisor_tail(void) * and we want to patch the hypervisor with almost no stack. */ check_for_livepatch_work(); + local_irq_disable(); } } +void leave_hypervisor_tail(void) +{ + local_irq_disable(); + + check_for_pcpu_work(); + + vgic_sync_to_lrs(); + + /* + * If the SErrors handle option is "DIVERSE", we have to prevent + * slipping the hypervisor SError to guest. In this option, before + * returning from trap, we have to synchronize SErrors to guarantee + * that the pending SError would be caught in hypervisor. + * + * If option is NOT "DIVERSE", SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT + * will be set to cpu_hwcaps. This means we can use the alternative + * to skip synchronizing SErrors for other SErrors handle options. + */ + SYNCHRONIZE_SERROR(SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT); + + /* + * The hypervisor runs with the workaround always present. + * If the guest wants it disabled, so be it... + */ + if ( needs_ssbd_flip(current) ) + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 0, NULL); +} + /* * Local variables: * mode: C From patchwork Tue Dec 4 20:26:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152856 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503459ljp; Tue, 4 Dec 2018 12:29:30 -0800 (PST) X-Google-Smtp-Source: AFSGD/U+azz4yVhqTX4oEQc0g9NGpqCtrIchw+0Sqax3W2poBhuJ0cBQAla61hTxAH8y8pfYXzdM X-Received: by 2002:a0d:e0c5:: with SMTP id j188mr22446632ywe.164.1543955370372; Tue, 04 Dec 2018 12:29:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955370; cv=none; d=google.com; s=arc-20160816; b=yBighro5y+TuzEObstN4qUbRVSCUuj+xUJPC9VLSVbwuL3gmEsoqlAlFRVt/55XNBj 34mvFkXAcJMre2TkJDbmZRQ21bwSz1L66Ny80z956V6dFtKWlbP8/9aYFcfH8KFOuq2K AYZxGVVug+gMJVchYHsSkPjvFxV6BhV2w+C3RM6u+XK4HreIgVCyDFQ2zKsIoAJOMoYZ Pvhlz49lVBapxC1hki+BnU/jY0drEzERj2tle8EMiWvgzqaBenffKKZf8oHuhmmIDBAe uzFtc9HzvUD2MsPb3zpc8yfJeXcD6k+MWRd36XZtlimLHG8oLLkMDf0Gy1IesgDizuXp kLwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=Vr+y0FMpx1US+45Xx7tZzfOP68kW7psyDSbkcc6c2YI=; b=eZY1JOTKWA/ntLljFNe9J0HbQxFKqpyiPQMbjgeMgZUVkHEClWh3hcsbgduMVh+pbr R3NR8iYN04uIWz0AUH0zbFBvGkJsns9Pd8WvuE+F1yJVA3B+MOY8BEz9Gqf5ib3/EW92 pX7JGMdBUhYcS/9lkZXZghUXmzLNA2QudKFxEpSUFyiIZHmqeGVq8rHH9tqQcL8oNJeV +9ov5sgHwcRND6Xnw1/y/R4MHH0R8Lh8njCsj+zP7/9wcNF711h0qZN2lMWquwYA7HIq N0AkMHGKURT0gEcJ8AjkmhBwv1/vwy6uGSB37R6uJFQ+pu3KwyB/9qWkXQ6qyI6v4Tyn LQKw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id y128-v6si10047797yba.206.2018.12.04.12.29.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI5-0008Cy-IX; Tue, 04 Dec 2018 20:27:33 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI4-00089u-22 for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:32 +0000 X-Inumbo-ID: 06a477b6-f803-11e8-aab0-8787de5d20f2 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 06a477b6-f803-11e8-aab0-8787de5d20f2; Tue, 04 Dec 2018 20:27:31 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6737C168F; Tue, 4 Dec 2018 12:27:31 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9E81B3F614; Tue, 4 Dec 2018 12:27:30 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:47 +0000 Message-Id: <20181204202651.8836-14-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 13/17] xen/arm: p2m: Rework p2m_cache_flush_range X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will add support for preemption in p2m_cache_flush_range. Because of the complexity for the 2 loops, it would be necessary to add preemption in both of them. This can be avoided by merging the 2 loops together and still keeping the code fairly simple to read and extend. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Patch added --- xen/arch/arm/p2m.c | 52 +++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 37 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index c713226561..db22b53bfd 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1527,7 +1527,8 @@ int relinquish_p2m_mapping(struct domain *d) int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) { struct p2m_domain *p2m = p2m_get_hostp2m(d); - gfn_t next_gfn; + gfn_t next_block_gfn; + mfn_t mfn = INVALID_MFN; p2m_type_t t; unsigned int order; @@ -1542,24 +1543,45 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) start = gfn_max(start, p2m->lowest_mapped_gfn); end = gfn_min(end, p2m->max_mapped_gfn); - for ( ; gfn_x(start) < gfn_x(end); start = next_gfn ) - { - mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order, NULL); + next_block_gfn = start; - next_gfn = gfn_next_boundary(start, order); - - /* Skip hole and non-RAM page */ - if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_any_ram(t) ) - continue; - - /* XXX: Implement preemption */ - while ( gfn_x(start) < gfn_x(next_gfn) ) + while ( gfn_x(start) < gfn_x(end) ) + { + /* + * We want to flush page by page as: + * - it may not be possible to map the full block (can be up to 1GB) + * in Xen memory + * - we may want to do fine grain preemption as flushing multiple + * page in one go may take a long time + * + * As p2m_get_entry is able to return the size of the mapping + * in the p2m, it is pointless to execute it for each page. + * + * We can optimize it by tracking the gfn of the next + * block. So we will only call p2m_get_entry for each block (can + * be up to 1GB). + */ + if ( gfn_eq(start, next_block_gfn) ) { - flush_page_to_ram(mfn_x(mfn), false); + mfn = p2m_get_entry(p2m, start, &t, NULL, &order, NULL); + next_block_gfn = gfn_next_boundary(start, order); - start = gfn_add(start, 1); - mfn = mfn_add(mfn, 1); + /* + * The following regions can be skipped: + * - Hole + * - non-RAM + */ + if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_any_ram(t) ) + { + start = next_block_gfn; + continue; + } } + + flush_page_to_ram(mfn_x(mfn), false); + + start = gfn_add(start, 1); + mfn = mfn_add(mfn, 1); } invalidate_icache(); From patchwork Tue Dec 4 20:26:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152855 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503437ljp; Tue, 4 Dec 2018 12:29:29 -0800 (PST) X-Google-Smtp-Source: AFSGD/UwLwE8IiP8Gx93NLF1hNpMLEqtjg381X8an60DP05f/Uh1FDZ5oCGdNnPXvUUH0I5NHNsL X-Received: by 2002:a81:a0d2:: with SMTP id x201mr20975633ywg.421.1543955369178; Tue, 04 Dec 2018 12:29:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955369; cv=none; d=google.com; s=arc-20160816; b=CJ3jTGiZpX2AjMelDDMXvr9GP/PUSUsAZNvfciijmEsX4Rd2Oo8RwPfXq6z5FGn4Zv CAK8440xggzZecW2jIE8rIfRI95l/piCoL25QtKUrIwIe7DPsjMuaqatKAiQXG33K6i3 aJsgYUm3A1hXIZYDF6fwMXHZOIgAqZTqIF+X5s4AH74xCYX9e8nZSokwoYrHGV4/IRe2 e209ejfumkB5pOknn7J5uS93se1uv3mx8m2eNIM1pxjxNvB9frw84EXCTNk5spl58SB7 3okvg+Y4EUXmizk+zByZy3IQd2gxlA2AzsbwdXYFTVXG0R8JpNA00fWH+JibxgctTlbM VEjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=78FJDKqks3TGQ8WayPKS0oPLTuP2kKKGxnH/VkGyk3M=; b=VDlVYQ5NMGTATTCeKhXZ7ZmcYzRk9Z+rXD64Qcs+gUsydXt5VxYZmh6PJNCkeu5GqU YOfsPncnRiCNuHqezIoP39xqAzYCbJOYAgXIZux0TyXubPyKCGOp0AYtWkmkjinS5WMd KuXgD4uKvdJ3xnk2iNdilPnhV+HBloUdncQXO8qY2B52SORIW1nfP4BIB92YJc5aMsJR NNSnkV2CVXfzOdia0kNTP5VWKa3du/zEVZ1rHMDyBztSV6NRNps3DisUBWE89hFoAue3 cFEjV8ITa+C5w2JBOc7Z3csJES0O78NoCTPGoIajwa7F7wSVqcqgDisU50xn2CqBQiYT BdqA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id l37si12319048ywh.242.2018.12.04.12.29.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI6-0008EF-H3; Tue, 04 Dec 2018 20:27:34 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI5-0008Ch-A2 for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:33 +0000 X-Inumbo-ID: 07414fe6-f803-11e8-bf5e-d79027609bf2 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 07414fe6-f803-11e8-bf5e-d79027609bf2; Tue, 04 Dec 2018 20:27:32 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6D2A915BE; Tue, 4 Dec 2018 12:27:32 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A4C423F614; Tue, 4 Dec 2018 12:27:31 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:48 +0000 Message-Id: <20181204202651.8836-15-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 14/17] xen/arm: domctl: Use typesafe gfn in XEN_DOMCTL_cacheflush X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This will make changes in a follow-up patch easier. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Patch added --- xen/arch/arm/domctl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/domctl.c b/xen/arch/arm/domctl.c index c10f568aad..20691528a6 100644 --- a/xen/arch/arm/domctl.c +++ b/xen/arch/arm/domctl.c @@ -52,16 +52,16 @@ long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, { case XEN_DOMCTL_cacheflush: { - unsigned long s = domctl->u.cacheflush.start_pfn; - unsigned long e = s + domctl->u.cacheflush.nr_pfns; + gfn_t s = _gfn(domctl->u.cacheflush.start_pfn); + gfn_t e = gfn_add(s, domctl->u.cacheflush.nr_pfns); if ( domctl->u.cacheflush.nr_pfns > (1U< X-Patchwork-Id: 152857 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503498ljp; Tue, 4 Dec 2018 12:29:33 -0800 (PST) X-Google-Smtp-Source: AFSGD/Uz8S/h+sJQofb4sxinExDBz0aF6S4oVG+bvu8fxFeAwrJiu5U0G7d0AqmehRtDn0UvvnOj X-Received: by 2002:a81:6308:: with SMTP id x8mr12781715ywb.438.1543955373565; Tue, 04 Dec 2018 12:29:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955373; cv=none; d=google.com; s=arc-20160816; b=gYv1fMdrksqCV+Ci+D1stKEn1StT0atBheskf/2QQHjGey0EwatMw++bnkJBt20mb4 c3ALDJ7M1DtpWhB79PV3KNpTyBCY4BARtB8Ry9D6/6q1Jup7rA+LBZ1Va9pIEhr2qfAD v1fKmtYIzU1usr8C2EyHaW1CIBUZ5pOQQ9SKPHNYcCbIH2bjZ6NREFzRHYjW6zw0NYAr ZTwuMshLfWJ/l7P4ikMvYYXlbgQCHBjmqex46AtMxburNSdhLdGJk3YK9Ybor519n9h5 lXwEaY+dlWSn7goFKKB3YYEt+Bs91oJ38wrpvEgHNDj/Kx61+eh+Jj+GVeL2Cwpxsf3s 6CMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=xF1Rh7fRzIRutYnOgc8LCBXEoPsh84q6ZLmCRMeKQjw=; b=C4/tgwralQ/KCZLj+qdmEap2n2bYOO2TaPIga/AwmbW8qN5mz/dWbIZLrE3LqBoA67 6m8KKWrK1+KVm7gTrxGR7ePhcUQFwkWXxmAkbN8em2O2A0rYY9P2Du6VD9VFJcjBbQlA kGsNV7HFOflPThwYQ3h0MRvs8vMmlhGwe4plCJZ1b+DUB5f75CqNAOiuIPFZ/G/r8dJ2 aJm43oCzrmpBB7UP5uK7cbeAH9upcAoQIEq2dVXkCwItzS6gPjeJgUYHS2bGVrt8t1ct H8vs2fS2wUAyIQima/otMuqbwpaU311cjyzqrESHQ7yPrrVpfOar9iNBnEQ1UiSqP9Rj 515g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b14-v6si10624506ybn.14.2018.12.04.12.29.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI8-0008Hc-2X; Tue, 04 Dec 2018 20:27:36 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI6-0008E9-GU for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:34 +0000 X-Inumbo-ID: 07e54c18-f803-11e8-a27c-c3aaa8c709e1 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 07e54c18-f803-11e8-a27c-c3aaa8c709e1; Tue, 04 Dec 2018 20:27:33 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 73D2C165C; Tue, 4 Dec 2018 12:27:33 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AB04B3F614; Tue, 4 Dec 2018 12:27:32 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:49 +0000 Message-Id: <20181204202651.8836-16-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 15/17] xen/arm: p2m: Add support for preemption in p2m_cache_flush_range X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" p2m_cache_flush_range does not yet support preemption, this may be an issue as cleaning the cache can take a long time. While the current caller (XEN_DOMCTL_cacheflush) does not stricly require preemption, this will be necessary for new caller in a follow-up patch. The preemption implemented is quite simple, a counter is incremented by: - 1 on region skipped - 10 for each page requiring a flush When the counter reach 512 or above, we will check if preemption is needed. If not, the counter will be reset to 0. If yes, the function will stop, update start (to allow resuming later on) and return -ERESTART. This allows the caller to decide how the preemption will be done. For now, XEN_DOMCTL_cacheflush will continue to ignore the preemption. Signed-off-by: Julien Grall --- Changes in v2: - Patch added --- xen/arch/arm/domctl.c | 8 +++++++- xen/arch/arm/p2m.c | 35 ++++++++++++++++++++++++++++++++--- xen/include/asm-arm/p2m.h | 4 +++- 3 files changed, 42 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/domctl.c b/xen/arch/arm/domctl.c index 20691528a6..9da88b8c64 100644 --- a/xen/arch/arm/domctl.c +++ b/xen/arch/arm/domctl.c @@ -54,6 +54,7 @@ long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, { gfn_t s = _gfn(domctl->u.cacheflush.start_pfn); gfn_t e = gfn_add(s, domctl->u.cacheflush.nr_pfns); + int rc; if ( domctl->u.cacheflush.nr_pfns > (1U<= 512 ) + { + if ( softirq_pending(smp_processor_id()) ) + { + rc = -ERESTART; + break; + } + count = 0; + } + /* * We want to flush page by page as: * - it may not be possible to map the full block (can be up to 1GB) @@ -1573,22 +1596,28 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) */ if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_any_ram(t) ) { + count++; start = next_block_gfn; continue; } } + count += 10; + flush_page_to_ram(mfn_x(mfn), false); start = gfn_add(start, 1); mfn = mfn_add(mfn, 1); } - invalidate_icache(); + if ( rc != -ERESTART ) + invalidate_icache(); p2m_read_unlock(p2m); - return 0; + *pstart = start; + + return rc; } mfn_t gfn_to_mfn(struct domain *d, gfn_t gfn) diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index 7c1d930b1d..a633e27cc9 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -232,8 +232,10 @@ bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn); /* * Clean & invalidate caches corresponding to a region [start,end) of guest * address space. + * + * start will get updated if the function is preempted. */ -int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end); +int p2m_cache_flush_range(struct domain *d, gfn_t *pstart, gfn_t end); /* * Map a region in the guest p2m with a specific p2m type. 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[192.237.175.120]) by mx.google.com with ESMTPS id o66si3310931yba.405.2018.12.04.12.29.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI9-0008Jf-HB; Tue, 04 Dec 2018 20:27:37 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI7-0008Gl-R7 for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:35 +0000 X-Inumbo-ID: 08a6f9f8-f803-11e8-9411-43a526868f8e Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 08a6f9f8-f803-11e8-9411-43a526868f8e; Tue, 04 Dec 2018 20:27:34 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A639015BE; Tue, 4 Dec 2018 12:27:34 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B12E73F614; Tue, 4 Dec 2018 12:27:33 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:50 +0000 Message-Id: <20181204202651.8836-17-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 16/17] xen/arm: Implement Set/Way operations X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Set/Way operations are used to perform maintenance on a given cache. At the moment, Set/Way operations are not trapped and therefore a guest OS will directly act on the local cache. However, a vCPU may migrate to another pCPU in the middle of the processor. This will result to have cache with stall data (Set/Way are not propagated) potentially causing crash. This may be the cause of heisenbug noticed in Osstest [1]. Furthermore, Set/Way operations are not available on system cache. This means that OS, such as Linux 32-bit, relying on those operations to fully clean the cache before disabling MMU may break because data may sits in system caches and not in RAM. For more details about Set/Way, see the talk "The Art of Virtualizing Cache Maintenance" given at Xen Summit 2018 [2]. In the context of Xen, we need to trap Set/Way operations and emulate them. From the Arm Arm (B1.14.4 in DDI 046C.c), Set/Way operations are difficult to virtualized. So we can assume that a guest OS using them will suffer the consequence (i.e slowness) until developer removes all the usage of Set/Way. As the software is not allowed to infer the Set/Way to Physical Address mapping, Xen will need to go through the guest P2M and clean & invalidate all the entries mapped. Because Set/Way happen in batch (a loop on all Set/Way of a cache), Xen would need to go through the P2M for every instructions. This is quite expensive and would severely impact the guest OS. The implementation is re-using the KVM policy to limit the number of flush: - If we trap a Set/Way operations, we enable VM trapping (i.e HVC_EL2.TVM) to detect cache being turned on/off, and do a full clean. - We clean the caches when turning on and off - Once the caches are enabled, we stop trapping VM instructions [1] https://lists.xenproject.org/archives/html/xen-devel/2017-09/msg03191.html [2] https://fr.slideshare.net/xen_com_mgr/virtualizing-cache Signed-off-by: Julien Grall --- Changes in v2: - Fix emulation for Set/Way cache flush arm64 sysreg - Add support for preemption - Check cache status on every VM traps in Arm64 - Remove spurious change --- xen/arch/arm/arm64/vsysreg.c | 17 ++++++++ xen/arch/arm/p2m.c | 92 ++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/traps.c | 25 +++++++++++- xen/arch/arm/vcpreg.c | 22 +++++++++++ xen/include/asm-arm/domain.h | 8 ++++ xen/include/asm-arm/p2m.h | 20 ++++++++++ 6 files changed, 183 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 16ac9c344a..8a85507d9d 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -34,9 +34,14 @@ static bool vreg_emulate_##reg(struct cpu_user_regs *regs, \ uint64_t *r, bool read) \ { \ + struct vcpu *v = current; \ + bool cache_enabled = vcpu_has_cache_enabled(v); \ + \ GUEST_BUG_ON(read); \ WRITE_SYSREG64(*r, reg); \ \ + p2m_toggle_cache(v, cache_enabled); \ + \ return true; \ } @@ -85,6 +90,18 @@ void do_sysreg(struct cpu_user_regs *regs, break; /* + * HCR_EL2.TSW + * + * ARMv8 (DDI 0487B.b): Table D1-42 + */ + case HSR_SYSREG_DCISW: + case HSR_SYSREG_DCCSW: + case HSR_SYSREG_DCCISW: + if ( !hsr.sysreg.read ) + p2m_set_way_flush(current); + break; + + /* * HCR_EL2.TVM * * ARMv8 (DDI 0487D.a): Table D1-38 diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index ca9f0d9ebe..8ee6ff7bd7 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -1620,6 +1621,97 @@ int p2m_cache_flush_range(struct domain *d, gfn_t *pstart, gfn_t end) return rc; } +/* + * Clean & invalidate RAM associated to the guest vCPU. + * + * The function can only work with the current vCPU and should be called + * with IRQ enabled as the vCPU could get preempted. + */ +void p2m_flush_vm(struct vcpu *v) +{ + int rc; + gfn_t start = _gfn(0); + + ASSERT(v == current); + ASSERT(local_irq_is_enabled()); + ASSERT(v->arch.need_flush_to_ram); + + do + { + rc = p2m_cache_flush_range(v->domain, &start, _gfn(ULONG_MAX)); + if ( rc == -ERESTART ) + do_softirq(); + } while ( rc == -ERESTART ); + + if ( rc != 0 ) + gprintk(XENLOG_WARNING, + "P2M has not been correctly cleaned (rc = %d)\n", + rc); + + v->arch.need_flush_to_ram = false; +} + +/* + * See note at ARMv7 ARM B1.14.4 (DDI 0406C.c) (TL;DR: S/W ops are not + * easily virtualized). + * + * Main problems: + * - S/W ops are local to a CPU (not broadcast) + * - We have line migration behind our back (speculation) + * - System caches don't support S/W at all (damn!) + * + * In the face of the above, the best we can do is to try and convert + * S/W ops to VA ops. Because the guest is not allowed to infer the S/W + * to PA mapping, it can only use S/W to nuke the whole cache, which is + * rather a good thing for us. + * + * Also, it is only used when turning caches on/off ("The expected + * usage of the cache maintenance instructions that operate by set/way + * is associated with the powerdown and powerup of caches, if this is + * required by the implementation."). + * + * We use the following policy: + * - If we trap a S/W operation, we enabled VM trapping to detect + * caches being turned on/off, and do a full clean. + * + * - We flush the caches on both caches being turned on and off. + * + * - Once the caches are enabled, we stop trapping VM ops. + */ +void p2m_set_way_flush(struct vcpu *v) +{ + /* This function can only work with the current vCPU. */ + ASSERT(v == current); + + if ( !(v->arch.hcr_el2 & HCR_TVM) ) + { + v->arch.need_flush_to_ram = true; + vcpu_hcr_set_flags(v, HCR_TVM); + } +} + +void p2m_toggle_cache(struct vcpu *v, bool was_enabled) +{ + bool now_enabled = vcpu_has_cache_enabled(v); + + /* This function can only work with the current vCPU. */ + ASSERT(v == current); + + /* + * If switching the MMU+caches on, need to invalidate the caches. + * If switching it off, need to clean the caches. + * Clean + invalidate does the trick always. + */ + if ( was_enabled != now_enabled ) + { + v->arch.need_flush_to_ram = true; + } + + /* Caches are now on, stop trapping VM ops (until a S/W op) */ + if ( now_enabled ) + vcpu_hcr_clear_flags(v, HCR_TVM); +} + mfn_t gfn_to_mfn(struct domain *d, gfn_t gfn) { return p2m_lookup(d, gfn, NULL); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 02665cc7b4..221c762ada 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -97,7 +97,7 @@ register_t get_default_hcr_flags(void) { return (HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM| (vwfi != NATIVE ? (HCR_TWI|HCR_TWE) : 0) | - HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB); + HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); } static enum { @@ -2258,10 +2258,33 @@ static void check_for_pcpu_work(void) } } +/* + * Process pending work for the vCPU. Any call should be fast or + * implement preemption. + */ +static void check_for_vcpu_work(void) +{ + struct vcpu *v = current; + + if ( likely(!v->arch.need_flush_to_ram) ) + return; + + /* + * Give a chance for the pCPU to process work before handling the vCPU + * pending work. + */ + check_for_pcpu_work(); + + local_irq_enable(); + p2m_flush_vm(v); + local_irq_disable(); +} + void leave_hypervisor_tail(void) { local_irq_disable(); + check_for_vcpu_work(); check_for_pcpu_work(); vgic_sync_to_lrs(); diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index 550c25ec3f..cdc91cdf5b 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -51,9 +51,14 @@ #define TVM_REG(sz, func, reg...) \ static bool func(struct cpu_user_regs *regs, uint##sz##_t *r, bool read) \ { \ + struct vcpu *v = current; \ + bool cache_enabled = vcpu_has_cache_enabled(v); \ + \ GUEST_BUG_ON(read); \ WRITE_SYSREG##sz(*r, reg); \ \ + p2m_toggle_cache(v, cache_enabled); \ + \ return true; \ } @@ -71,6 +76,8 @@ static bool func(struct cpu_user_regs *regs, uint##sz##_t *r, bool read) \ static bool vreg_emulate_##xreg(struct cpu_user_regs *regs, uint32_t *r, \ bool read, bool hi) \ { \ + struct vcpu *v = current; \ + bool cache_enabled = vcpu_has_cache_enabled(v); \ register_t reg = READ_SYSREG(xreg); \ \ GUEST_BUG_ON(read); \ @@ -86,6 +93,8 @@ static bool vreg_emulate_##xreg(struct cpu_user_regs *regs, uint32_t *r, \ } \ WRITE_SYSREG(reg, xreg); \ \ + p2m_toggle_cache(v, cache_enabled); \ + \ return true; \ } \ \ @@ -186,6 +195,19 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) break; /* + * HCR_EL2.TSW + * + * ARMv7 (DDI 0406C.b): B1.14.6 + * ARMv8 (DDI 0487B.b): Table D1-42 + */ + case HSR_CPREG32(DCISW): + case HSR_CPREG32(DCCSW): + case HSR_CPREG32(DCCISW): + if ( !cp32.read ) + p2m_set_way_flush(current); + break; + + /* * HCR_EL2.TVM * * ARMv8 (DDI 0487D.a): Table D1-38 diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 175de44927..f16b973e0d 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -202,6 +202,14 @@ struct arch_vcpu struct vtimer phys_timer; struct vtimer virt_timer; bool vtimer_initialized; + + /* + * The full P2M may require some cleaning (e.g when emulation + * set/way). As the action can take a long time, it requires + * preemption. So this is deferred until we return to the guest. + */ + bool need_flush_to_ram; + } __cacheline_aligned; void vcpu_show_execution_state(struct vcpu *); diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index a633e27cc9..79abcb5a63 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -6,6 +6,8 @@ #include #include +#include + #define paddr_bits PADDR_BITS /* Holds the bit size of IPAs in p2m tables. */ @@ -237,6 +239,12 @@ bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn); */ int p2m_cache_flush_range(struct domain *d, gfn_t *pstart, gfn_t end); +void p2m_set_way_flush(struct vcpu *v); + +void p2m_toggle_cache(struct vcpu *v, bool was_enabled); + +void p2m_flush_vm(struct vcpu *v); + /* * Map a region in the guest p2m with a specific p2m type. * The memory attributes will be derived from the p2m type. @@ -364,6 +372,18 @@ static inline int set_foreign_p2m_entry(struct domain *d, unsigned long gfn, return -EOPNOTSUPP; } +/* + * A vCPU has cache enabled only when the MMU is enabled and data cache + * is enabled. + */ +static inline bool vcpu_has_cache_enabled(struct vcpu *v) +{ + /* Only works with the current vCPU */ + ASSERT(current == v); + + return (READ_SYSREG32(SCTLR_EL1) & (SCTLR_C|SCTLR_M)) == (SCTLR_C|SCTLR_M); +} + #endif /* _XEN_P2M_H */ /* From patchwork Tue Dec 4 20:26:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152844 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503099ljp; Tue, 4 Dec 2018 12:29:05 -0800 (PST) X-Google-Smtp-Source: AFSGD/XGhuG8Zd/xVq/I+mo1CmAjMDExHt2DGXtrIdqGfN1zA0wjdUDKWswYrtC0kuqR/A5eNvOz X-Received: by 2002:a81:e50d:: with SMTP id s13mr21511262ywl.405.1543955345142; Tue, 04 Dec 2018 12:29:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955345; cv=none; d=google.com; s=arc-20160816; b=pncZxCBqtPzHA13yfgBtIXQvoLsbimtngRjr0EPgiiCsiQ0PYChRWMKOr3fjh4jNX9 lc1ovPVNYtuk40sqlUHrwSLC5Khh8RT36xBxhozryKi0h+4tq2ZfAR6a0VaJAWdDr6tu 7/ZgkHx43nAYuMMBQYCXUNAKyLX9w9MpS0fPKR1k+VM/iRh1FrU/8ec39GwwFdTwnDBX c1h0E8EVB9MFj+j6K1LWjLMkAqO1Kl56rwutpA/Pc9C5AFZEXOBS8OWlP2CIuO/Qsm9s 6xYnTjHNW9T5TBX++EbrsUuBbswuXz40y6K9hR9OS4dHvlGOa0FXcDH537l2n7xUZ6d+ gmHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=dB3qTAyrylG+fbztp9esECTk47PKJWhxZtQsssPH5Vw=; b=yI6p7mcLWYjI3eiN8xRU8TJ9H7QBQaKOGnJ8BuGeH2dkY82B0384q9Aoja0s5Fo/w7 kChcq1mymN71Q/d1JQU35PMcoXGfQn6eRY99S4NvOlt02Av1ec69q7aBcFNVfAtk3OH5 8gODONPx7d4hC+jRrCNwy5gQI0PzKX6ia9JerxWXv3VQiLI7M8hecW1+hhAosuIsfRpP 0dBp9ZHhylYyCAmESW6TUUifOBPx/Oc23RkCVeb2GoM+rEHLJn932ntH0CKAUKgDOy6t MLaWcm5CxbL7KIVbau62b81YFmvF8r+LJEppUK7CVTeGLtIv1ghyBd+yzaQOI+ZBtz8t 3pLg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id h5si11009470ywh.342.2018.12.04.12.29.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHIB-0008M8-6v; Tue, 04 Dec 2018 20:27:39 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHIA-0008Kx-Dc for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:38 +0000 X-Inumbo-ID: 09e4db46-f803-11e8-b51a-3ff82174fce4 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 09e4db46-f803-11e8-b51a-3ff82174fce4; Tue, 04 Dec 2018 20:27:37 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D543115BE; Tue, 4 Dec 2018 12:27:36 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E5A033F614; Tue, 4 Dec 2018 12:27:34 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:51 +0000 Message-Id: <20181204202651.8836-18-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 17/17] xen/arm: Track page accessed between batch of Set/Way operations X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: sstabellini@kernel.org, Wei Liu , Konrad Rzeszutek Wilk , George Dunlap , Andrew Cooper , Ian Jackson , Tim Deegan , Julien Grall , Jan Beulich , =?utf-8?q?Ro?= =?utf-8?q?ger_Pau_Monn=C3=A9?= MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, the implementation of Set/Way operations will go through all the entries of the guest P2M and flush them. However, this is very expensive and may render unusable a guest OS using them. For instance, Linux 32-bit will use Set/Way operations during secondary CPU bring-up. As the implementation is really expensive, it may be possible to hit the CPU bring-up timeout. To limit the Set/Way impact, we track what pages has been of the guest has been accessed between batch of Set/Way operations. This is done using bit[0] (aka valid bit) of the P2M entry. This patch adds a new per-arch helper is introduced to perform actions just before the guest is first unpaused. This will be used to invalidate the P2M to track access from the start of the guest. Signed-off-by: Julien Grall Reviewed-by: Jan Beulich --- While we can spread d->creation_finished all over the code, the per-arch helper to perform actions just before the guest is first unpaused can bring a lot of benefit for both architecture. For instance, on Arm, the flush to the instruction cache could be delayed until the domain is first run. This would improve greatly the performance of creating guest. I am still doing the benchmark whether having a command line option is worth it. I will provide numbers as soon as I have them. Cc: Stefano Stabellini Cc: Julien Grall Cc: Andrew Cooper Cc: George Dunlap Cc: Ian Jackson Cc: Jan Beulich Cc: Konrad Rzeszutek Wilk Cc: Tim Deegan Cc: Wei Liu --- xen/arch/arm/domain.c | 14 ++++++++++++++ xen/arch/arm/p2m.c | 30 ++++++++++++++++++++++++++++-- xen/arch/x86/domain.c | 4 ++++ xen/common/domain.c | 5 ++++- xen/include/asm-arm/p2m.h | 2 ++ xen/include/xen/domain.h | 2 ++ 6 files changed, 54 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 1d926dcb29..41f101746e 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -767,6 +767,20 @@ int arch_domain_soft_reset(struct domain *d) return -ENOSYS; } +void arch_domain_creation_finished(struct domain *d) +{ + /* + * To avoid flushing the whole guest RAM on the first Set/Way, we + * invalidate the P2M to track what has been accessed. + * + * This is only turned when IOMMU is not used or the page-table are + * not shared because bit[0] (e.g valid bit) unset will result + * IOMMU fault that could be not fixed-up. + */ + if ( !iommu_use_hap_pt(d) ) + p2m_invalidate_root(p2m_get_hostp2m(d)); +} + static int is_guest_pv32_psr(uint32_t psr) { switch (psr & PSR_MODE_MASK) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 8ee6ff7bd7..44ea3580cf 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1079,6 +1079,22 @@ static void p2m_invalidate_table(struct p2m_domain *p2m, mfn_t mfn) } /* + * Invalidate all entries in the root page-tables. This is + * useful to get fault on entry and do an action. + */ +void p2m_invalidate_root(struct p2m_domain *p2m) +{ + unsigned int i; + + p2m_write_lock(p2m); + + for ( i = 0; i < P2M_ROOT_LEVEL; i++ ) + p2m_invalidate_table(p2m, page_to_mfn(p2m->root + i)); + + p2m_write_unlock(p2m); +} + +/* * Resolve any translation fault due to change in the p2m. This * includes break-before-make and valid bit cleared. */ @@ -1587,15 +1603,18 @@ int p2m_cache_flush_range(struct domain *d, gfn_t *pstart, gfn_t end) */ if ( gfn_eq(start, next_block_gfn) ) { - mfn = p2m_get_entry(p2m, start, &t, NULL, &order, NULL); + bool valid; + + mfn = p2m_get_entry(p2m, start, &t, NULL, &order, &valid); next_block_gfn = gfn_next_boundary(start, order); /* * The following regions can be skipped: * - Hole * - non-RAM + * - block with valid bit (bit[0]) unset */ - if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_any_ram(t) ) + if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_any_ram(t) || !valid ) { count++; start = next_block_gfn; @@ -1629,6 +1648,7 @@ int p2m_cache_flush_range(struct domain *d, gfn_t *pstart, gfn_t end) */ void p2m_flush_vm(struct vcpu *v) { + struct p2m_domain *p2m = p2m_get_hostp2m(v->domain); int rc; gfn_t start = _gfn(0); @@ -1648,6 +1668,12 @@ void p2m_flush_vm(struct vcpu *v) "P2M has not been correctly cleaned (rc = %d)\n", rc); + /* + * Invalidate the p2m to track which page was modified by the guest + * between call of p2m_flush_vm(). + */ + p2m_invalidate_root(p2m); + v->arch.need_flush_to_ram = false; } diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index b4d59487ad..d28e3f9b15 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -762,6 +762,10 @@ int arch_domain_soft_reset(struct domain *d) return ret; } +void arch_domain_creation_finished(struct domain *d) +{ +} + /* * These are the masks of CR4 bits (subject to hardware availability) which a * PV guest may not legitimiately attempt to modify. diff --git a/xen/common/domain.c b/xen/common/domain.c index 78cc5249e8..c623daec56 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -1116,8 +1116,11 @@ int domain_unpause_by_systemcontroller(struct domain *d) * Creation is considered finished when the controller reference count * first drops to 0. */ - if ( new == 0 ) + if ( new == 0 && !d->creation_finished ) + { d->creation_finished = true; + arch_domain_creation_finished(d); + } domain_unpause(d); diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index 79abcb5a63..01cd3ee4b5 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -231,6 +231,8 @@ int p2m_set_entry(struct p2m_domain *p2m, bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn); +void p2m_invalidate_root(struct p2m_domain *p2m); + /* * Clean & invalidate caches corresponding to a region [start,end) of guest * address space. diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index 33e41486cb..d1bfc82f57 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -70,6 +70,8 @@ void arch_domain_unpause(struct domain *d); int arch_domain_soft_reset(struct domain *d); +void arch_domain_creation_finished(struct domain *d); + void arch_p2m_set_access_required(struct domain *d, bool access_required); int arch_set_info_guest(struct vcpu *, vcpu_guest_context_u);