From patchwork Tue Mar 8 18:48:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue \(OSS\)" X-Patchwork-Id: 549429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46104C4332F for ; Tue, 8 Mar 2022 18:49:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349640AbiCHSuG (ORCPT ); Tue, 8 Mar 2022 13:50:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349638AbiCHSuF (ORCPT ); Tue, 8 Mar 2022 13:50:05 -0500 Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50046.outbound.protection.outlook.com [40.107.5.46]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BE7252E3C; Tue, 8 Mar 2022 10:49:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fe1kLzvAzW9K1K/mogQuXHXOUwN2jgjJ1SFa8gR0miGQw0xgHfk/rsUoSc31OxWiSAsbXQudO9qtLNNxmtbXvMUMSFwD49/qEep6+WXPUqbvjEONidxegoRKk9Ut60EuKHQJjWU+J4Y7qqNJuF573iikhARvIIvxNLLTUZtCsRrR+YXPC9VJlPOvcx9h3V7xwA+j1JtsOQG6iN0kFZWOBekq2QlO2ISWtQ0Q3Bgg0VyWXuSObqZzn7RYEN7r0qhTLs+uFyldGPNhz1XXW3LlRNofr7B08gOFCTkUhybiJs0IOdRpvInBp3xPV7JjtpJSUaSSSQwX7YT54h8hE+C8WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cW4qrzOcNxgGKlKzqqlU2sNKw1Qe/UX6a7HAmeMO8xs=; b=D/f8YlezGa16D8OhHmU53GyqRU0+8oEqiz41tebDrl2ilGYk38VKCMQpYL9Y/KaOnqoA/Nr2k+5hlhmwyMblu/HwLH0OQlZIrVnNhdlA63cVbaCMnIDgRT7n0w7aB/qCF01enj5KsB2lXLfC1pZbg+5LRdC5unZX+A3rB1daqID8X9U15BygWZm5SJD1kE5D7eWWDjdASJ4svzPwT1mXlKmBDy9vUiHwgAJv5M0PmLLg7kVCPIYNv07k9xpTIE1f4n8OVX+OBYF8lCqkvwkHH/MDtclIY7CgCiyK8/PK01ysWk20XTkZKuKTiV0m03ApindMtHC6Kr9xNWXtIA4aJA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cW4qrzOcNxgGKlKzqqlU2sNKw1Qe/UX6a7HAmeMO8xs=; b=IYUYE7mRP/u+Ah+cEsgjewh3Lh9kywSl7m4GtV6YuRYdOkM6ffWqinUAVp2ZAhhs4rqSIBJXeLb8PHpbBCy7FzUdp+64QJlE5XSC9yyYo/cUWJAvXuIIzQW8QidS9ClO59i+c/j10K5cP+f97L75pDQoRCOO3yMHAbgSjK2fnqI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by AM6PR04MB4311.eurprd04.prod.outlook.com (2603:10a6:209:40::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5038.15; Tue, 8 Mar 2022 18:49:03 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::a037:bc8:44b:5965]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::a037:bc8:44b:5965%3]) with mapi id 15.20.5038.027; Tue, 8 Mar 2022 18:49:03 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/9] vivid: add dynamic array test control Date: Tue, 8 Mar 2022 19:48:23 +0100 Message-Id: <20220308184829.38242-4-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308184829.38242-1-xavier.roumegue@oss.nxp.com> References: <20220308184829.38242-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR0P264CA0131.FRAP264.PROD.OUTLOOK.COM (2603:10a6:100:1a::23) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3aa6ab82-6be1-4cbf-6697-08da01345116 X-MS-TrafficTypeDiagnostic: AM6PR04MB4311:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZAEPCleqbkObTnWRCymmyVzsCOJWuYiw2scjmv802ffiNRar+iws6YdfAueRo3OlDsbsHjTumeR53p7HVGL1fJLbex2mz+eOmCsKZTzQhGR0Yl/fthoUO8cbvsXCo6JlcBbXzyk/u2JcjsMmiilkHfX5herX5/dMhFIyGMuwNNXNqCq0nnV6Fxv82B40fvjxD6PeCRJKBCUbIM//+/7nzcWmbjTUFdQ826Gkd9/Bna27er1J1D3ig7ubCZKwebOTkBYh8sr1xVKY5IsS7euv+xvnodB02Wu/z1qX+Qz0RSjggmCd1uOGRkaH5wCFFgSf9rycYxovRHCTQFQXbvj+7Jo0Ic+y0WONNrxtXXItLPfXkaPxbqA6/eAVixL8xdI4L4bSn3Q94oEZNCWV2IKVo1x1uOAmMJ+rDHPHviMiO7P+HE9Exd6m2Qsh4cmlXB8U9SOrXShkIfKU6Ud28XfqJkviNF5Az97Ff9gmStqPBkYY8646IsPbPbBRTFFVPdV4seOkS2uAek5ieOeZodgb608VeBqbbyvl33j2ucdTvmtFGBZ8bL+ozYOC5Uim+LbXBpwYOpIXmRjz0wr1aJQg6czc1dNikAwtnZ1BN9JDKxRKQbyxwO0t0NOUs9o402nRDU8MkUDslvVxVHoPhlVogg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAXPR04MB8703.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(4636009)(366004)(66946007)(66476007)(4326008)(186003)(1076003)(6486002)(86362001)(5660300002)(8676002)(66556008)(38100700002)(2906002)(44832011)(498600001)(8936002)(6512007)(52116002)(6666004)(6506007)(2616005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HkgtvTnces1ovYarsReFc4QIlYwUXsw5D/F1XxX3OC+WKmMBSrMvqbJhY4hdVW9stFg+svF7AZ5+dPGw+zOhy492FQwJcv0sgRS8fP+eIvmBiFQvKj5FemMIOq6kF1iPbNhQ5dnIyHOzPOSdzvYDBCyZIgJgMv1aoLJfNnOkBkr8gaLJN4tB0RZPwvMN2pB1pU3IvXpJCSDSixx2TnX2Zyks0/6CLLq4cGX+TBbp3/tihwMAHqcGpHspVM5BcTwR3FNVw8QDdqDjDjKWuOCUByhEmCIbrLnnXiIlt0Fsj3Pd8ZOmzHox4KLoqvuydbS9zPfv29x2XkCfvXK3iroA6UxZFoU+VJet4xSCHfc6sNxkQnIUqFhPU1aCphOGEmpgDmEDn2Jt9BMXIJVBG91rJ9UTYDP1egwq8iR6PzWUREF8Z3t4V2XDCtNV9/crKbI8QRuv3aXDPnN5tAV/3g7IInWWJfDMMf/yEM+1Ue8EgmIbufGSAx3ZiwV0g5sDY26X7HwIBGeVZKvmZgauaNUg/4O1hgEID79oC9jyl0Y3ACZBGAqESagU0Vnpu3aYZ0QArQpr3pjX7Tf99dDeIMfUz2CSNXVm65jNGNXddrZ0d/l0DXaPfKeD6AuARm5z4pU0+zjlBXhxN7e+KsgrpDSP6/cYRsUu+vt29WxnXQhHO4PnUa+B+ppzGtieAqTWVcQEXhfXvp6boxNZ4BZvGT3dmyvXMLeHS/kJ/9AwFzQvHmRcvvynaIRVzuuVYocQLyEAKbeBUSaRexf0IQeNqlCaPqsr679JfyIoKOmntbRtrKqinAwOWkIVw0nsqGho6NMkcCAqujVww7wLPqw4IuIABoYgMrCd8PaWM/UM2KDzZt6ZnapoEbctLZusVwcmNKFCCUkoRZz57lvKZ9xM5YxQyOM3FiSuidbTjRi0aU4iiUnzEhNoiu26fCfc13qivPLaSCOiLnYujBNHOfqptngAQnGqkunzlqT+QxK9yPpeKi8EuU1NGMdT5VF3LQ54Aqvcq/Tc8qnQNuRUP5yIGgF+FPObrr4qq+g84KFmLwt2v7tovJTyODUJcD3cDvi5CSG7UtIbG53jcESR2Y9b56wFZjP6U2cEm1ipq0WGDITmXZkFHIYURLBcCE7vzI25h3oCjDzSrH8RHgEn4gzDZG7ELUUUNR4s0UrLVtM7XNoXDGH720Z0kIpTlWv/SgeUWBPDlicb5RCu8CDkyGFk7h5JD38XGuZYPc2YYy70xrl4MJzKHZ01jEgm41mXZG1bEo+liUFBf4o0XXkA6lZvaRcsdLOhBd7MyTLaznp8JT7iayc+su3dWUnUBg3EAIdfuXcaFV0PXw76LbqZzBZ00eM8ZOO+d4bZzChIgCHYJxMzSMTpSrElXRMWWg5kwhHo6PoyyLD2GdlUq9QLSyCSr7IvC/KewvUWXdFF481SKTYaFn7HoFNrf5BtI3TbSGJwXGURJuuve9Jhk7S3DpMzEdDlygnCPo9HlUiLOLf571yvfoFyFXev8lptMdLHsD9GhG9IRCQV80UmQufzFKLflmPB0CEzaUmiDMDMCjGb3Xu/iNHSdHAmJ6w/7fJvkfddp5q0IQ8T/SAJx1u33eL3/fmtDDegNNgUHRmmpO9HxLRyYm0bppEWlM/2+BftT/rpGx9Yo/TGR+hREGhuvawjUtZSJTZ+XojP6zt9JDrljfUUUbY= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3aa6ab82-6be1-4cbf-6697-08da01345116 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2022 18:49:03.7945 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: EJWZsizcpgOBdTFJFQcdiwNDEnFb2yHTnqa/+suRWW+D1eiohfTcPM30ToIwYpTtiEovEr/vTd3hjak+Qiknyw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4311 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Hans Verkuil Add a dynamic array test control to help test support for this feature. Signed-off-by: Hans Verkuil --- drivers/media/test-drivers/vivid/vivid-ctrls.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/media/test-drivers/vivid/vivid-ctrls.c b/drivers/media/test-drivers/vivid/vivid-ctrls.c index e7516dc1227b..7267892dc18a 100644 --- a/drivers/media/test-drivers/vivid/vivid-ctrls.c +++ b/drivers/media/test-drivers/vivid/vivid-ctrls.c @@ -34,6 +34,7 @@ #define VIVID_CID_U8_4D_ARRAY (VIVID_CID_CUSTOM_BASE + 10) #define VIVID_CID_AREA (VIVID_CID_CUSTOM_BASE + 11) #define VIVID_CID_RO_INTEGER (VIVID_CID_CUSTOM_BASE + 12) +#define VIVID_CID_U32_DYN_ARRAY (VIVID_CID_CUSTOM_BASE + 13) #define VIVID_CID_VIVID_BASE (0x00f00000 | 0xf000) #define VIVID_CID_VIVID_CLASS (0x00f00000 | 1) @@ -189,6 +190,19 @@ static const struct v4l2_ctrl_config vivid_ctrl_u32_array = { .dims = { 1 }, }; +static const struct v4l2_ctrl_config vivid_ctrl_u32_dyn_array = { + .ops = &vivid_user_gen_ctrl_ops, + .id = VIVID_CID_U32_DYN_ARRAY, + .name = "U32 Dynamic Array", + .type = V4L2_CTRL_TYPE_U32, + .flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, + .def = 50, + .min = 10, + .max = 90, + .step = 1, + .dims = { 100 }, +}; + static const struct v4l2_ctrl_config vivid_ctrl_u16_matrix = { .ops = &vivid_user_gen_ctrl_ops, .id = VIVID_CID_U16_MATRIX, @@ -1612,6 +1626,7 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap, dev->ro_int32 = v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_ro_int32, NULL); v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_area, NULL); v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_u32_array, NULL); + v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_u32_dyn_array, NULL); v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_u16_matrix, NULL); v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_u8_4d_array, NULL); From patchwork Tue Mar 8 18:48:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue \(OSS\)" X-Patchwork-Id: 549427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED86CC4332F for ; Tue, 8 Mar 2022 18:49:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349657AbiCHSuN (ORCPT ); Tue, 8 Mar 2022 13:50:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349660AbiCHSuM (ORCPT ); Tue, 8 Mar 2022 13:50:12 -0500 Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50071.outbound.protection.outlook.com [40.107.5.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BDE152E3C; Tue, 8 Mar 2022 10:49:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XJRLjUIBBYalhYvadDdSf7umv69yEuU0PlCUBZYCbIsPkMUDIu7rnBxvFGhB1Wc0iDYPUDEVoYf5jwJDVIz2Di0KzK95NuojfjIf0irUN3b0oUQ+Of8NpBRRzxqu52AvHL6H4tRdisJXndJ98sGrB4NHL9BskFS1RqZIZlZqF2/gOu2c0Jci3UcfvCpuVeEen45R3BRQHVo+jQ+b09GUkyPd5FrWBme2u41K/mm0HzPYErS5h09sogUFLvIT6MsB5DtZEgwsMV0UOY2rjS+bO8z1S/Dm8BImh2qOINtRU4WRX7OjXerdH6PYrGdmKMEa2zJfJZFEl42myXbKItCwhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=roOCkUdbGizXqSiw7kyURKbwtlTm0mvMOxvPkVRvWPY=; b=F5zGD4r4u3fDxTqImPlhpU973U1RYE73RT5uSqKqx0nZWpNf7LiVIuQEDUXEgPoNtt+EsXskuQ6vRWLoSz8L6hw4GZCslCbvF1E6ICdZyImTSZ0bm26MZaJIc2V8APTA0TMpIDdxwZZy6krFAQZioLg6fX93Arc3J/vTvZVE+VFQiJS9eepX3x6tANPWxeFkAuHV+xlo87P8j7Ve5aN/awUi4858ZlCSIadzGhiTYULlkAH+GvCRO19F+NZbO/Yl8kGYd/U4XclEOd3dmC3RMIvXBEJmdWV0fIjShX0ZkZ+ZylewiJMmxFvEOcS1Cxg2INPD9oKnKKZfTMzDhtxP3Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=roOCkUdbGizXqSiw7kyURKbwtlTm0mvMOxvPkVRvWPY=; b=WA+23zDyhAdjEpBvm0HegC3ndmaaKhDwQLu6DOelcfTtWHKYWpLgNhaxQuOHHJ32/DzgxWsyaZibOPsO3vTQzDeOHXjTQhaRU2blB+qo7TlW0dXcdUWYqQkpCZPyBOmetYSKjg/9R5FqcHKsukTPD8+AN7n+AuHrZoI/f2pryKA= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by AM6PR04MB4311.eurprd04.prod.outlook.com (2603:10a6:209:40::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5038.15; Tue, 8 Mar 2022 18:49:04 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::a037:bc8:44b:5965]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::a037:bc8:44b:5965%3]) with mapi id 15.20.5038.027; Tue, 8 Mar 2022 18:49:04 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca Cc: Xavier Roumegue , linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/9] media: Documentation: dw100: Add user documentation for the DW100 driver Date: Tue, 8 Mar 2022 19:48:24 +0100 Message-Id: <20220308184829.38242-5-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308184829.38242-1-xavier.roumegue@oss.nxp.com> References: <20220308184829.38242-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR0P264CA0131.FRAP264.PROD.OUTLOOK.COM (2603:10a6:100:1a::23) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3f94f65f-73c0-4bda-87f0-08da01345164 X-MS-TrafficTypeDiagnostic: AM6PR04MB4311:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JhPgSnaaqcO2zACFPek0cky/UcT+mONmYi7D4W9fLuG1txNeCT9tSFtY5bF3LZRwgy3Kqy3gZulz15q4e/lCjEg61EuLC8clZ8iAJu5fW2IdLiWT0I/ftuHy7t/6WCr0hdqo2nX+dAbde21wo32OQks8lskG0xBga/5nJfWcBmDGEJSkyR3SbxQgA7tppZXwPqxX/Us1mqJCNa1eYNS7KBBDjo379EgqQtEA+MXuTlCoQm4cFaPHiiFKMuQ4DGKdfQ/mBgVhIOpqFJFMLcZi2xepgRlaQ2OEmEm0TaTcyO/nmyIttLei4tBnakq5PlY+AO+bhcr7ihvwHpVwSDJmsrKSujEEChqxloZUrufUkH89AIR4EqAIh6hFMNWLVZ99bkcpHvc05FS9rLR6VOeBItjOT+lEiMN/03g0VJCZjWSpLPt4MTsKMQqVti6d7x1l4UQn7UK56v7007wwV2hpDUYk01PmqP743AyunJNdM45Jfi2nAKClC932M/mAsUsZmx5cH0pfA4ed2MiHhw33nT3XbyTzUB/ejsx9FTwML6zalBduMHhz1+YQcLOXPow+qzUxRZdHP1REq4PRtx2Di4ZsdsWQH9dBsIET59TJnsHiLeggRz1GykOvjNf+W9cSzQ0W1v14AMESNsW7xVZTWokEHj7FVDS7GkHUog1eWQjBVsUSsO3wmc4SxgJKcgxl2+lISsIX4NzhAj/2L2jkdJzgMC24cTgjQ+dGTGBU4Ak= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAXPR04MB8703.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(4636009)(366004)(66946007)(66476007)(4326008)(186003)(1076003)(83380400001)(6486002)(86362001)(5660300002)(8676002)(66556008)(38100700002)(2906002)(44832011)(498600001)(8936002)(6512007)(52116002)(6666004)(6506007)(966005)(2616005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fp4vwc5uAjKX+XX2Sine2jausFEn/Z8pAxoZTUg7BBQqkGX0NVLFdO/ftlnKumydRRM7cBraMwS8bbQRa/H+K//L75Jsd2iCCBr5NksEEAbUchotOu1LoA8kfxjEV6UgsobO16ft8UWaBCmyYqpN0VBnInORMsnIlllWa6+1Mp/R+E3HJOxy+CqGULTAmkypa0aD7hiM1PwE9BNn2v4DPCLkCvMZNQv5Sp6iUY0VkocE+F/c2aYvfiNRvoFd/lKITilYA7YNOzLG0N7J5llR29OgKggjB16qA68rhsGjAimwyvk18bcdWcfVrpnLQdRpk8rDkTFfx5p3ok+vmTqkjeIG/Y8IBBcsbDdUff3vZPWLEL/0y2t3xqHIglKD8YdnTrw5Q3Zb0l0ceaG/Drt3TCxrZGBg+amJHQbwXFZZaB0fYHgQ+2G5zWjGrObE+Db8Hu5NFsLesE/gN7y3DxvOwDtDtBW3xhdYOozDB2YEWfZYOP9LWonKzXM/SRNhJ8CU0g8gkPNnmyfAKXEIcpXvLNwzPal/MsE6YysSNmVVw6UYbQjcEOSD5bV3bqWVSgacrklR5xBwZGKED3iNfNJrqWUsEZADfL2aCI6+4E96bGpX7Qfzg5YKST5/MS91jdUN+YTXaAB+BaUSMJ1sMaPeT2Z2Xk+/Ojeu7u6owPOLoJ3bD0NzKjiZX3PaRy5/olqGXnGBOkQHAdPekqvz7/Z++cuo1umGUGsq19FnpkIpuwFi2cPinkJGxFCKCpQXTzbIYMBC6gDYM7xCM2goHlglzCSB6HiiglIe0AgIcLvJnssnlEpfHU95dbZby2Bh56e7VR7v6x+VN8rUWnMp2GWiAf5sgo9fHQy4qg+PKkb6dgneaJJMoERELEscVDiIJKVfQWHRWZdRH/sGClltP0v5vd/lZIIjnYOFftYU6TXG4Mk03+3C8oql2NJRqtgqgzENwkV0eVbU8Wt9P+REmlluIZmWG8qaOgSboV0zDwuTCfXXcx80slMax9zjKdLNLGbhM4N3KLHOhVVyGwin6Uf79E+70yFQymCEXiaIvW3rtlfchn0M9QfWrY54D2XJpKtW8nWoIeXC7tbPa9vIZzfWGzpKggatVajVaGMU1j28Qb2fShd3yggltya2nP9+cQCZ6YqRsns2iSUqHItNCo/inEAPG56RUVM4iMOaztjrtEgTWOm597CnF1+593396jxLqa7HDzCczvGwNIbJmjPCYGkrwqQDiEkXKHrLyWn+qJd50VPS3CxLYNxPKpCFNl8K+J6v1MZO2o8WpesnqYCctLqKOW5xEkO9q4vRazjakHtQgyVEgFPEMsFfpQU8HywJn/qiJZMnWlXEkUusFcrRLELp4f5rawgbWjex++pGsFe4dmb5tXsCo1PrqitYxIa4Y6ZmeqEn9m4sMdhEYnPIHttIzYpeqy+6QMvRfB7F7DXoiji79YhnibM+jliEsfReJYYNqpCvhKjsCeWql7iC6ri06Ux9ED9bcAyrtoInoe4Ftm/sYIm4rc6DaT78VaWk0cwJ/FgIrqu5MicWuuXVO8Mzd9CEtoso58/4oDM5oXLjbkfzhFbDIItwh/M2PrGykrsYM419faye3dEZEyLcu63NIoKBUeFNGOHwraqVUwPUSlKOb546WUj8N3YVEiOuBth46R91Si0ZjKhJPk00WwfmvXgEK3LfqRwmM0Rz95M= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3f94f65f-73c0-4bda-87f0-08da01345164 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2022 18:49:04.3066 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TbktPRFU1USPbrsg5FDkPXRAuIBLcrSD2hyqHQm5j+i913syckgUPU3L8hfBUPdmnpJGs4kb9Wumhat+IAbnhA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4311 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add user documentation for the DW100 driver. Signed-off-by: Xavier Roumegue --- .../userspace-api/media/drivers/dw100.rst | 23 +++++++++++++++++++ .../userspace-api/media/drivers/index.rst | 1 + 2 files changed, 24 insertions(+) create mode 100644 Documentation/userspace-api/media/drivers/dw100.rst diff --git a/Documentation/userspace-api/media/drivers/dw100.rst b/Documentation/userspace-api/media/drivers/dw100.rst new file mode 100644 index 000000000000..20aeae63a94f --- /dev/null +++ b/Documentation/userspace-api/media/drivers/dw100.rst @@ -0,0 +1,23 @@ +.. SPDX-License-Identifier: GPL-2.0 + +DW100 dewarp driver +=========================== + +The Vivante DW100 Dewarp Processor IP core found on i.MX8MP SoC applies a +programmable geometrical transformation on input image to correct distorsion +introduced by lenses. + +The transformation function is exposed by the hardware as a grid map with 16x16 +pixel macroblocks indexed using X, Y vertex coordinates. Each x, y coordinate +register uses 16 bits to record the coordinate address in UQ12.4 fixed point +format. + +The dewarping map can be set from application through a dedicated v4l2 control. +If not set or invalid, the driver computes an identity map prior to start the +processing engine. The map is evaluated as invalid if the array size does not +match the expected size inherited from the destination image resolution. + +More details on the DW100 hardware operations can be found in +*chapter 13.15 DeWarp* of IMX8MP_ reference manuel. + +.. _IMX8MP: https://www.nxp.com/webapp/Download?colCode=IMX8MPIEC diff --git a/Documentation/userspace-api/media/drivers/index.rst b/Documentation/userspace-api/media/drivers/index.rst index 12e3c512d718..8826777321b0 100644 --- a/Documentation/userspace-api/media/drivers/index.rst +++ b/Documentation/userspace-api/media/drivers/index.rst @@ -33,6 +33,7 @@ For more details see the file COPYING in the source distribution of Linux. ccs cx2341x-uapi + dw100 hantro imx-uapi max2175 From patchwork Tue Mar 8 18:48:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue \(OSS\)" X-Patchwork-Id: 549428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAF98C433FE for ; Tue, 8 Mar 2022 18:49:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349655AbiCHSuN (ORCPT ); Tue, 8 Mar 2022 13:50:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349652AbiCHSuL (ORCPT ); Tue, 8 Mar 2022 13:50:11 -0500 Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50046.outbound.protection.outlook.com [40.107.5.46]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44E44532E3; Tue, 8 Mar 2022 10:49:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UyLnnq+mxz+mE+4L4VNiJ+w+WoeFepIPEP1gdRPspVb848BDGbiDpjpH4AWMSjPxA0+HHUW/1/WT9j5KTScD6L3EKDeJqnQAgcWUXA2Y4R/YifX1g9BlsxopOESThAwjzYTG84zO/qZbXqM33cgd98rZnaPvUqkew4AEo4RBTVCXgOnorJBH/i43WTZVBZp1seYXm5QEc/PKj3SckB1N5ObLWCArK9T01PwS8HQ8eJ1BSQ8oSIfJXrktT7/133t7NWA0l+rqJCOX3Uw1QuISCzyAhTqozqn5w9oKTmsmEPCY+OXF75hrrzuZZl4iQGKVdXk6uoOmkgo+vIYks5eIfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tQDh0wfjD2cCDwgTJ7xrrzvLa3R5Ew2ME9XWlfJwSxU=; b=RwGTkZGLOSg8wqHqClmCKIxbkeZtDuuAn+1aRlK9pimxNrMLCej34Xb/eokE7ohVE/CysRzDmrw80hB7vRrCGxnzSKdmSUhVBm3lcE3E7WInAHpgoNK6GxyjGTkzAHBkwBSRhcRPOGB2/LUmqUptIIgaFtQyY0z4rfIEjB/JBAg53ttAGC6Xc6S5/EmsMB2pRMNBUSPHIdqwKgaIszTr3qFYP49ztN0TLnySbQrDekZVH3IggVZND2lXOeSrS7KbVA0M02la+qHiVlwSGuGB5bzfmX8zPZJWFbnWtcx2f5LZ43kATUXPRNDAqIkEZS8+hBmjnJydsoMC+AmfQR2jcQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tQDh0wfjD2cCDwgTJ7xrrzvLa3R5Ew2ME9XWlfJwSxU=; b=FP4EWpOsopnPzSB7EVcu3NbSc/BRKfwkSHebTVIlj6G/ftiPgqmj6u55YFcPA86YpkYIyRi1gUxfthMZOE2PRS2oaCH+zyOgEZrglrEYU89v7sT44wUzWtgEXHJeoDEp0KQvkxA852zV0zI5y0VeynlamSABysaKLBYY7i+xdH8= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by AM6PR04MB4311.eurprd04.prod.outlook.com (2603:10a6:209:40::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5038.15; Tue, 8 Mar 2022 18:49:04 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::a037:bc8:44b:5965]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::a037:bc8:44b:5965%3]) with mapi id 15.20.5038.027; Tue, 8 Mar 2022 18:49:04 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca Cc: Xavier Roumegue , linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 5/9] media: v4l: uapi: Add user control base for DW100 controls Date: Tue, 8 Mar 2022 19:48:25 +0100 Message-Id: <20220308184829.38242-6-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308184829.38242-1-xavier.roumegue@oss.nxp.com> References: <20220308184829.38242-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR0P264CA0131.FRAP264.PROD.OUTLOOK.COM (2603:10a6:100:1a::23) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 815a80bf-19ad-4f0e-6d3e-08da013451ae X-MS-TrafficTypeDiagnostic: AM6PR04MB4311:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LQclm95gM0g3Qek1FxOVEeSMrNZa7zL4GSp1FS+KDlhUrrUHHxHvGLJhaPX15leRZMNH+Y/rUT3nN9c0DeEZVrnABAMx0zbtA2gc2S6vqLTASIHZQajgrpvlUIeZbkAQgU36ONczonCpIfS7hR0LUqZQbQskzaCqHxmS3BXxM8RXJaddyP/xEDIJwxaMSxHj1TJf8c5pJFMuR4V+OdLXfAiGd1U9KmtlCxgnOFtsRG5nyrGbgsHB15C5ZBP4sWRzo7c8NRPrg2PR4/zvTxV5glVw6IclzIIvvLVWsMAmne0H1kmVMWPYsGbnHFHE7uSN1fE/G2bpbOsXhgIDV11fY8NxGZigu64Wu4pQyRX3f3rL3xmVOyD+mJCHqSf9xOb9pQnkHTpO4xLTSNbaLcjbppqCu/M3hCNWfEfq2MKHxgTZ5EWrxycNP++xPjCBBqVXNT96sHtCDkF7/D4GAONL1fNh0+bdUe6LGhJvmDrox8u01rvGIquTV/fyv3bPFmMx0Bl7Auak7GGekklYCQFSBhnLF18eOw6fnFj5WqeFm7afsVIxzSmczOCBqBSZKCiy76K3QXHbRUEH8sVupEaBK90bhQzOKwcKwgaUmfWkXw9EP8OnhnRgRK7lu7/bCnQp60UTZ4oN/CuusmSSuI6sEw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAXPR04MB8703.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(4636009)(366004)(66946007)(66476007)(4326008)(186003)(1076003)(6486002)(86362001)(5660300002)(8676002)(66556008)(38100700002)(2906002)(44832011)(4744005)(498600001)(8936002)(6512007)(52116002)(6666004)(6506007)(2616005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: r8se1tjLsulnZYDQVVcDdaTmQIT5Qa3jVwioFGxydL/hPWL01lBeHZ/lltxk5+1CcSYaLbEd4BZSubXsePjq6KkHs9GeTLV3MlvRwwq5NDqy5wM2XAEjUbW2HoPoqu6XkCV4c76f5y9pAhe+rZ/DtwIi2YUj3tJt73AVOrQL/jn4SArquWzxzl0dnhQk7Fab79VGIMdZa9d8ee2ghHzdOHHw2QO1P6oOEEW5wUtTtmUQk1NhGrkk0Z4v+hAxqzXcdMDN+Sfjhkkm9ZiDg0FW7/2xGanVla8ufqIHoRvmuOWHHAG8VafySc/p4tJXiEUpfB207XeHpGUF1Eq/jL85J503IbBOPCJ43fIRK7uW5Pd29gEjbX5cbvMSkZsV1JVn4TMPQUqVw/a5+If5cRBJumArxZXLL3oliZPs1b93KcKJtOvGmWVmFnh9VIip07599jBedGpc3ass86eEJ4adBReGlmmvVtHhsBBoqEyvXkzxpXVnnQge5NDNHGYudYZB7vfDSn44d8AZOvOEa15C7H9xzute7LA+BKNLJdv5OuhynFue2oltTu0GEkAkXNBtg2/tzIIJkiVolZIa6RLcwSereBsUumZ8YETIQEBCMmjwL3IS3jK3d5EgONQ1fchlNOYkLhaMci0xIEYu/ir7QVJRn8NjkUF/VvnknXDQ1TqnnsV+uCbf7QdVe1NXcQz1jRXoioKym6VwQKlU6/Zq36gC4N/W8Q+RDhdBok2OJE3MP1712IHzSy9+xTXX9PP7mf2yMGcpsqxgMvCh5xuQ2xp0nTVEpqaQD/r/wT1J9kG5EItaUSH1iukJsh8Cv+UH7dqfiDQQrFetDBeVZuLmWPbAUXCzcMM9DYjiceL5ZGcUwFBrx9f5bYpq7drO6baMM5M5NnEjhDFWX4wPABhm2DKRyJsn01AqjVWwem0PAJNOKX4XDjdgMQ0uNMbskrVqoenNNh0tO6/gk/1P+YflEW6MkZLnWNGLt9NqyRJsh84xa07YtdzNNZ0hrc1YRuJAX+My/5K4wtsDgcGBxIXmvIQo3a0M3gkGHdbZrES1rhCGGD4rtvjQg3F5bq4fsL5/ysQZYKOdE78q6vYlA8cyWDeLqPG/MErnIoLg214gIJ1F02LOhzmY+OqocgSKxb8wka0O5tli7k0v+R/+b+HDBB8090ABZv7LxbgujZpIfN38TQJQFPZ6lSLiXVsjEAwbivXC+r9+RPUjN+Xxhn25bNnQIvHYm7zhhL1t/YJi/te3MjDVqO6NsEIWN9EHNlIdozZUeUkJcyQn/dhC9VW53BqqM3mYNdklJccekfHl0zbQRlEwRXdw8/9EQEa++XyDm6AaT15stkEWMPuxo8oeOnhWceTKsj6+E68uTsiHK9VlG7C7IitaxGU36FVPwdutPz0GA+QTKP21tRB8t9e+MVoM9M/77fYMoEA0BtiW6+hdWY3cGpywmSKQUsEQe7RNosWHTOWFGgm4Hz9B/A7naj8GuB1lbkKXwKK5uYEylZx9BrCTazWd3B1bcVA6Jl7pjJK4ZDfSjKwiS//OYKB0ujxM/x2nHq3Rm6NCwVEWLLIRgt+6TnGrZXhySj8hlCYIEl2MDbX/zBPQ7eE6c56RmVn3RoIDIJLgAVslWVLPf9X86BZ8/rNFaxiCVAw55hJJ9JZ501eYiXdTppInAZNs5b0Z2IyWolUl61gx77vGH5w= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 815a80bf-19ad-4f0e-6d3e-08da013451ae X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2022 18:49:04.8221 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ztbJvYptnv1DRKsIuxAJNO6VA88+W9b+DHq5ZqihTs4RESWdToC76wCWIvbJSnlPoE38Rj29p8IK6y0QaTLseA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4311 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a control base for DW100 driver controls, and reserve 16 controls. Signed-off-by: Xavier Roumegue --- include/uapi/linux/v4l2-controls.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index bb40129446d4..d275f8b1bd96 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -218,6 +218,11 @@ enum v4l2_colorfx { * We reserve 16 controls for this driver. */ #define V4L2_CID_USER_ALLEGRO_BASE (V4L2_CID_USER_BASE + 0x1170) +/* + * The base for DW100 driver controls. + * We reserve 16 controls for this driver. + */ +#define V4L2_CID_USER_DW100_BASE (V4L2_CID_USER_BASE + 0x1180) /* * The base for the isl7998x driver controls. From patchwork Tue Mar 8 18:48:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue \(OSS\)" X-Patchwork-Id: 549426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04FADC43217 for ; Tue, 8 Mar 2022 18:49:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349668AbiCHSuN (ORCPT ); Tue, 8 Mar 2022 13:50:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349661AbiCHSuM (ORCPT ); Tue, 8 Mar 2022 13:50:12 -0500 Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50071.outbound.protection.outlook.com [40.107.5.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3EB2532DF; Tue, 8 Mar 2022 10:49:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lxuHxdhY1AZ+REkedeKHZUS1m+HzBzR7K8huaCG9ChtajyLRTWw4sJYlEteu39Wif/tfl8xCrqQHxrxPVQFQaTLhyA5umEjO5KLFSqq8aZcY3HzK9Qcvq/zoilSUN//Igu8uuiNk/jRHV4zXFrNo42XTLH/txjJ1wHYdr8a31Oq6+K4srfdSlu9U1NpWQwu30nctHF7MVkg5h4vLjnMedYKFMWiiNM49xjvNWCjl2hz9Gi0xS6IqA5AOdzsyKeZiQvI5aAcZ9opXfV/SB/VisrtBkaLxlbx0Ik7P83Qn5OjcPakoRWjrpQY8IqJRF6kGpIEotsnjwJDBM1A/R6XYUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=euecBA5KU4JfTB107Tutxzr54jP8p/8G0c6Kiv5g+cQ=; b=C/vVJB6N7gbH4HiYae0QVuOvClurV8PnzWBqR7pfHT+bur1DTtY1yP94ggBWyuiiXODFXXJlo3TcHMMJXwCEuxzXifokE4/JggQrBVlvh5ka+n2cfEuZ52/rAIAHjBrwLwKSye78s6q6nOmbh7e4tUjnK/lb1PWIWImPeB5MzxbF3oVyOAENBWTDp6MgaBQA8Xrlq51H3RDblX7zuRCD4pFZFbLlcDpwxfzrbqnyNmlafCrPXeaGuI3XBSXl+Q1JFei36ej0v0SYy4WRxC78+4JbMgjcCdJFDEWm3zwEHg2s/PC2Orz7BolsRd1qRn2Xr6QSAU6w7iiVSmBjjjnrjQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=euecBA5KU4JfTB107Tutxzr54jP8p/8G0c6Kiv5g+cQ=; b=H7UNBd5wdfeC4oOyYvh0Tv0tBJiLdgfDhIlTCp0tkV10wQ0muXSWlYEcpPI8zSlcpc+H3LAexjlM9K6BiODbRuQ+TiArzxRNH/F6iGxR2nqMGB6JAJxFiVzgJgZtSHewKdXgJ+/chfQgd77ca8/N89+YNaep4Z5vQsyf/e9Zt5w= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by AM6PR04MB4311.eurprd04.prod.outlook.com (2603:10a6:209:40::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5038.15; Tue, 8 Mar 2022 18:49:06 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::a037:bc8:44b:5965]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::a037:bc8:44b:5965%3]) with mapi id 15.20.5038.027; Tue, 8 Mar 2022 18:49:05 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca Cc: Xavier Roumegue , linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 7/9] media: dt-bindings: media: Add i.MX8MP DW100 binding Date: Tue, 8 Mar 2022 19:48:27 +0100 Message-Id: <20220308184829.38242-8-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308184829.38242-1-xavier.roumegue@oss.nxp.com> References: <20220308184829.38242-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR0P264CA0131.FRAP264.PROD.OUTLOOK.COM (2603:10a6:100:1a::23) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1d409398-1465-4320-8cf3-08da01345245 X-MS-TrafficTypeDiagnostic: AM6PR04MB4311:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Poe3uRoRYLTOd5EmumeoatREmU+Dn5rACszGsd83j8SevZiiPQ9qNSQgSIIFmOSKwXC+71YkjOI9C2Ugf6xrG93p9alf6vVffu/IsGzxnAp5J3G4Ajnn68VLwCJT3MQWeHryzZR2t0qr+7Jg+TNmXt9VM4R9VBOGi7lJDHKmrynbzpckyiLRdDOJfyS3X63UobUtHbJB+qGzRA1v2SBtdNsshjEvhGQzzRhSVLFXzFr8OrHTCcw5QbR2aYJcH5lNK1QyqHrBjFy1QZXDNAA6vynqZDzglKfR4CrUufSdl2RldRjvv4gP6qiA/spAp8yVTeqaTC30O/3KQYSG2Gz7IG1jRKxTCUxN3Vk9HS6IfbWuVzmmTOWFXezVHGoItbMHdK2t6AUmq6hV4mvdVNctpImqj2xdITTb1I1V1WSC26e18ObceueGEibY609mrfAixlGrZi+fC7tBHu2y5DX8YicI3FPmO0eX19EAtZlMerbLuYNt6Urb9WzvygYDkq4+TlVsIvL8vOe2nBq8Iv285OFymiKqsW+N0qpKJFgNJd2QVgroqm+HeVuN19qyJnJDukw0zSwsE3zX2i27YOsbk8gacwyH6XcpmoUshPwf4PulcJvjtOfwRsCUaIKiyG1OxZfXjqWu8vjqW1RuE5KxE9xK8Jwfoi1bxBb4HEOUUd2IhEDSYQZi2uz4+AxeazirWE95N3KWeSqFaVy4weBTGixQ+qOYP27u6chJ9MSF8fw8fqwJ4iHYHh0xHZAYQ0xLnbx/U2uf8mepjVjWK/HNHg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAXPR04MB8703.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(4636009)(366004)(66946007)(66476007)(4326008)(186003)(1076003)(83380400001)(6486002)(86362001)(5660300002)(8676002)(66556008)(38100700002)(2906002)(44832011)(498600001)(8936002)(6512007)(52116002)(6666004)(6506007)(966005)(2616005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: yFeMQjcCkrEM4Uw9uQF99uyzCOYTU0+drJI50KHMhvFt3mMlf3s+p5oiNewCvMmsZFMgNrOXRiuvDN4TdzL+Bhl1fwU6l403wi347S5aBpbWxcRBjXbP3LPHeVLcLKivcZtH3cfRlTxXfkbhVBCGaU3pLfdi3pJDoaqHhK9vqztMlsHmiVxTBHnaPMTizZdUXirm+Jh1JO8kr5YdxFg3uhcpmOAk73PJXj05TZCojyFW0IC5ZrZ5oHEHFbfxTBDpQK54EEaiHjJ/bg9Q68zLHpR3MykS+NRKvKAG068+SJnx5sBKeDpciVUMNLb3fxfqk4A2jvo9Pezmb1Nce6T+8HbYTg1xpql37ANO/3A4QsNAl4bXOrgk0UgnkWjJRGIwF90WjPswN1oW93lIMZhm4lkV8VgClpNFUe0FsWRzZpZd4mIjJKk3ir+grTCBa/7B8/mgB6JVI4GzI+v9o31JG8Xr2Q4vzrDrRSsg6v/dX0kkl2GeXGKo1/Meu0S7cJmM2DLPLEC0kDlhz17TJOMJ9GLa3TGiziCUpdSoElRYNn3zYRhfM1ohvhZmSskHVsHnP8qzBLkJA5XMAvasS09ICfj/+dYTXnhyhLlq6sxMFCZyO5rypC+DxuH5hcOl/YWukcZoRZJ7HORsqWG1uN2zYDa3lDGffGG6Wf8LGXjCKFPoxz4mwH+XVDwN0wVupkgnzMQD9hu+nivUEJwewJi2dWR3qx5r/btzZ1d0Ol5xL6tZ0UYssSpVeLDDf/zCNDMg9OCQ+qPolMLFW48kZAxKNy2sUXptDfCXhohVjVnMjNWPebFWGAEmOV882wPJ9VXeSAuZyjVnRgGEsF/blvMCS1v75B7ijpwlo/zsmIdYmENEIuM9wPTpoaLIe5523m02GuWy3bTgdqIlUYkVe3SJEDAcTsGOj9SbNISmnAb9iNc+yNdK83p7SHcz0/oppRYt3y/6KtMvXxttpJw8hDzndYc+x/PLAHieJgslF0sTJvA4qDtbhkqGKasxZwfUz8+TljhTscpxm/VOFD7UX+6/27l/5EUCSOcd6MRMgm3KQ5XM60YXKxEAKdAIiYjWUESXz9RM0wGWDwEWDLihW2waGOZrsgRV0MsYyFJMDEc0x+uKAO+WmnjdGcwCyF0TvcQEhr15pw6DWtJz8IQLd4jUf8h/REIrLZc2DPko/wRZUs/fEIQ7ItkhL14RAH6kz64YjKl0mdyUdgL7rObMu/GvZAH9C6N1isX+602oU90Yx2BPme1PtBHXzYrV+kdrm+ezG2R+MZe3PU7noXnX383kCWx5C+0wNx7hUQ51yy2OpeOgJGu6voVMnOa0mfQciIrIhQNoq7g6bQvM7GfnK6r/XDiehtqCkamRBaXhHHjycMJjpVD9f3SBtqtWhZCYQuwM3r8pScgm7o0UuUJjpM2dAz3mMue619Ag/22fmPDB68RW8+OV4IwqOBis1Bk5dI4NFFRp6TElC5r/3jZuSIdOu9+P7/W957XH7inWFH1qpPNFNfQPuFMhrqbsCO8idZ+wQ4V5RuOzuC8/tPGJfPVXyWDrI873zbCdZLsS7y8FjjxHxngfSVv9ppamjYUYQd/Jt6q/Gt24WaXHUCioi1gZvS7otyNhZGZ3OdpaXEvfybqqfd+vzxyfILG73nA2GRdi+qPEC2ijdV6eeFWSZF+xNwUQU2o4l1qOAzpNMqKT/5o= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1d409398-1465-4320-8cf3-08da01345245 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2022 18:49:05.8919 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zxYzZOVfRIdeKfL6/X6ean0Dox2d2lAVrCh7Z88EGCvrCsSwMZJqNtmMwP9f6Dpxomvy2BYKNgcC94JgC99IIg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4311 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding documentation for the Vivante DW100 dewarper engine found on NXP i.MX8MP SoC Signed-off-by: Xavier Roumegue Reviewed-by: Laurent Pinchart --- .../devicetree/bindings/media/nxp,dw100.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,dw100.yaml diff --git a/Documentation/devicetree/bindings/media/nxp,dw100.yaml b/Documentation/devicetree/bindings/media/nxp,dw100.yaml new file mode 100644 index 000000000000..2c3b82be0b74 --- /dev/null +++ b/Documentation/devicetree/bindings/media/nxp,dw100.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nxp,dw100.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP DW100 Dewarper core + +maintainers: + - Xavier Roumegue + +description: |- + The Dewarp Engine provides high-performance dewarp processing for the + correction of the distortion that is introduced in images produced by fisheye + and wide angle lenses. It is implemented with a line/tile-cache based + architecture. With configurable address mapping look up tables and per tile + processing, it successfully generates a corrected output image. + The engine can be used to perform scaling, cropping and pixel format + conversion. + +properties: + compatible: + enum: + - nxp,dw100 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The AXI clock + - description: The AHB clock + + clock-names: + items: + - const: axi + - const: ahb + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + + dewarp: dwe@32e30000 { + compatible = "nxp,dw100"; + reg = <0x32e30000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "ahb"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; + }; From patchwork Tue Mar 8 18:48:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue \(OSS\)" X-Patchwork-Id: 549425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1020DC4332F for ; Tue, 8 Mar 2022 18:49:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349692AbiCHSuQ (ORCPT ); Tue, 8 Mar 2022 13:50:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349672AbiCHSuO (ORCPT ); Tue, 8 Mar 2022 13:50:14 -0500 Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50071.outbound.protection.outlook.com [40.107.5.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09428532F6; Tue, 8 Mar 2022 10:49:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UQV3YIIGDBecRQOAiMAJbb2GOoabLnMpuOPVznNwAEuoNOpn2axMK+4Ljck0MqDpZIbumM7zdPShPyBbT0twehUmBEPCY5I79Fp2IDGo4PQtD5ewKX7vRAmNIA6bFd9dp92zt46fEGiRt5PzHklhN7wrgsdG/SH3R788mJ8SfB+Oyese3j5hZvZasLhGeOS0RZP0EJQUrDLO08CPtDKeSt5waGSFEZxk98QSVZInYomzRdTAcLxU/MElEsBZ7G1LaLVZrhkX+ghnkQKdr70CYklHq2WWayi2FNolVoXGmi4FfyWqKATFu4jYJ+OQ/llbGSrDUeWaZ6xYlX44aBGXgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dQ8iGHg8m84imwvvDMuZxq9H1ElWrxf2d9Dg/kxKURw=; b=hLzQMxhhIBXmCE5gW4VwcjTWls7ccumvspbgTSbD/pvl4tAZk7/KjPwz1ihA5sxRC7ZR3hYVAbXUaFu7ltYxIO+9wXKxjquvFPSTZup2xOfxQRAM2+ygcpEHfGrcVr0Y/FtCf2TTG75EedfA7cwqY9OvBlFHNUiRwVEINpBx9m7fJ78nszHeQnRRTpyE2Y7Z1SkM4TyvnL5IhMhH2QAuYSRqBuRpZsToiD6EobQ4jmhj1+HYFMb4YFJHbjtiC5OQ1CS7p5u2lACM4lK45aRmoloHZHsg3Zh2k86pPXRw7Yk1W84aQDHPlqOaZfJwYC17vO4k2veZwqXoqS+drR/u8A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dQ8iGHg8m84imwvvDMuZxq9H1ElWrxf2d9Dg/kxKURw=; b=StUPWRncEycB5iVbHk+p84WKmgSAzhxA1e5D5XvC7yrhBBl78XlpkqdVFXh/aUieAb8fZq9sYhM6gDWsH3w1RyNb3pNatxi7dL2l44VdYczt9tqAmmuJB9XT2s3SZ2i9+iU35dzLlfZnxnamNNtW0mzgmIKnFtt2ZgMINTORxW0= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by AM6PR04MB4311.eurprd04.prod.outlook.com (2603:10a6:209:40::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5038.15; Tue, 8 Mar 2022 18:49:06 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::a037:bc8:44b:5965]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::a037:bc8:44b:5965%3]) with mapi id 15.20.5038.027; Tue, 8 Mar 2022 18:49:06 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca Cc: Xavier Roumegue , linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 8/9] media: dw100: Add i.MX8MP dw100 dewarper driver Date: Tue, 8 Mar 2022 19:48:28 +0100 Message-Id: <20220308184829.38242-9-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308184829.38242-1-xavier.roumegue@oss.nxp.com> References: <20220308184829.38242-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR0P264CA0131.FRAP264.PROD.OUTLOOK.COM (2603:10a6:100:1a::23) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 45205f87-d769-423e-e68b-08da013452a2 X-MS-TrafficTypeDiagnostic: AM6PR04MB4311:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0irR5S8WNY4PQDRWyuoBRa147Nz2RPBHoCOV8mbPIVD3khbTrm+oLLnHMAgCMZHHyQ+JUhDdiZDDywqXWf/Zv0C+hUqTlw32FHGj2ritXkx4EfUerDuXlXYYz5dviAOGvpBaKNP9L7cY6NNK6KkzzsRjv9DC2bbmsodyZPGSgymLFUiOeskiUcWuWt8hauS181yya2W5WrsaJ0+zquoNy2pYBrkImFktSKPl9f2zEbmNWzXz9za2jo+melw/z4n4FeOy8uiWfhHVNixi4EVpxDp2vKuHoOirYrdhH7ZzVilVhywlL3T6/U+HvOXewZrx1sXmgc7AEn96pdbULUUCUdGOK5654gDeUSAg4l0K0M8Eussj7+WVdSwd3J1FZlFIDKt08jHqXrRnXWkdY0u5ifIcSus2JNkRKzeLXWO2bij4d+HCMkL/qu4BYXKN3A7fopUQMAr6TeVnHoo+8C/KH09GDi6uVQqVqqnh+m+G1XhZ200JKZaRupIvbf6Lm+AkJsgU5ZHoEfsP5MylRQRDIPCQaRGkzpc2QszEIS/JMh1R1UjkSuCI2NaTnLg+iil1kgWVQE+2Gg6Xt0n/DknTLQQqKAR/NfLE4/gyIlivbmBsUjPYPCniAo48Coh0qASgRovTNVLxHjLK9ChcIcCjFw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAXPR04MB8703.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(4636009)(366004)(66946007)(66476007)(4326008)(186003)(1076003)(83380400001)(6486002)(86362001)(5660300002)(8676002)(66556008)(38100700002)(2906002)(30864003)(44832011)(498600001)(8936002)(6512007)(52116002)(6666004)(6506007)(2616005)(579004)(559001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 22nEgd4yV9BNm/i05ECyP3ZTIOaunD2A8YOyyjec75HNk3ytn9JTV3z+h7QkInk1f1t6nKR6yD547Btq0bM4Xyo7yVGBoQj6KLGV4gBV6MxNFJ3Uc2W0tCIOgQS9ZdTviW1enqIwmI5OFZ43jYhyiqOCRKXuAS9+XX4kaQCwF3H1qL9pP73niLIpXt3t8qLWtpvArL03G1csl59HEE9QDQHXoWzJL/sE2hKRgdhQJ8OkzAgTy2WZm6K50wFyV5rx4i5vsWUhZ357Hsx02H4XpEMmRPIluJff2t/l/ijCVUY/1VxyHAYsbhKxALbGlBN/onl6sw7BcoDCc+9sLvPgMkH8FNQXfk/NmTKAvG6sbf6UG0PTwUAwRSCQcd3ryLk3IhYB4XZ7o1BzQvXHxYi3+efjydyRwVKCyHCSVan17MY44ZE6RRpEHzVfxXcrPqD0MXA5SCbmYhkL2NsXmszrcADlhyGkiCdsCGYO2LFDe9eIQ9lbkqijjc75WpL90VSFtTEnJ3r8rKbmoq6iT3cimw7iVWGJnRP5jKBi8Exj74+tY4WDJjnaCEQJJOUhDs948mAs89U1+gNk8RwHHPmwh9AfHrLqfDjQZmrfvXwKqXcPGPVvqd3YavpYBX7upNH2Cn8o9RqAwCriAZNwKIp5u32HU6jbPwzSGd7XatUOtePZAOECN2PlGFxhJ9WiYlQ3EaUtYK+JXMY6YRFnex3mD3tMf26e2FRtE51oEj7BbWM4uw2RBN1ozEXBd93aBrDOJtPSWb7MxjhiyPbJ2MRavLSS4kMV2yjKELJY8AYu+FOGm+ZoRzjRy+2mxVM73F+qItHptLFrsG2pAKwXJHfQ30QrJrAL5ZzNswGdRoyUHnvLyTfLhCToymKOH4JgT2RW9NhIl/eOWYjCtJzaccjO+qUv818xNAfNaF+4MRGLiNDNc1X+Pffv8s315OQ4yqq1A1LH3QgUwZPNn7PMrAhuaCxB1/tjgsTK2oQBbrQVUb/axDs3z0b7wUgGaE4RyTREUSwQw9Lp48QVaGOBbq1AQNSpHmh6AUtihs87RgL5ahYJL3u4JQYv7p+N3aNCgs74EU5dwyh+wdM2uO+ulP2gnSYMV9gFbo5m0G+dRmUpDGkubOZQ2UmkOi0HGYutFkfI8jctaSpcqNzPz8aW8jlTTVPEPwgtxL9PIdeNy1+Drvt2XWU1VhvqdQdi6F2VDpfAjp4oI3o+ju0jAmfR4rKTuLELCyvHdQKYKjGHx5d883rScsKjIH0t5c7KSWMS46zNfIN3N/3aFcbVHnVD8nu/R/xTqlX/lLUotewMu2pafiPsRY3jeWDIEFzo06A8vlX8laAU6BOJzBiU0D2L7oFixp+srMIi5xm0tcxj8N9OPStNzcig05oqggN77CmMZpiTSVwT0J2tnPcKg5Bup4U6P0hNNzpoZaXtRF7fs4BVEF0Yx4/D1gdvz/YEBiwFgqGrjZWPyGwr4oACGfKZh6Cw3Ki5VjJXcDl48W9Sim2OeFBHMq/uPdQk94COGGrOSzfrmga+C+Kckcq9NmGUFmlS7959rpVUw0+baDTYvCaWZU6a1xQe6ZQ7Pko2871nNriPRdbGOjmEkZ46Ru8U47mPrLdWi/0GvWvt3VwVyzFat1TSdTHV2unUpQIOVeaHpmx8ZpTis8AZHP1+rxhHaSupNL+6eB18H2NOG/IoaxCTiuc= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 45205f87-d769-423e-e68b-08da013452a2 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2022 18:49:06.5024 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OZa7DR4hbF4LHGpHgMmARbo8RVHCURurQEQcztk8uyE5C+PeJkVbuRiv7iWf+59sLoNoCnSj+R9tnycTme5lTw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4311 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a V4L2 mem-to-mem driver for the Vivante DW100 Dewarp Processor IP core found on i.MX8MP SoC. The processor core applies a programmable geometrical transformation on input image to correct distorsion introduced by lenses. The transformation function is exposed as a grid map with 16x16 pixel macroblocks indexed using X, Y vertex coordinates. The dewarping map can be set from application through dedicated a v4l2 control. If not set or invalid, the driver computes an identity map prior to start the processing engine. The driver supports scaling, cropping and pixel format conversion. Signed-off-by: Xavier Roumegue --- drivers/media/platform/Kconfig | 12 + drivers/media/platform/Makefile | 1 + drivers/media/platform/dw100/Makefile | 2 + drivers/media/platform/dw100/dw100.c | 1744 +++++++++++++++++++++ drivers/media/platform/dw100/dw100_regs.h | 118 ++ 5 files changed, 1877 insertions(+) create mode 100644 drivers/media/platform/dw100/Makefile create mode 100644 drivers/media/platform/dw100/dw100.c create mode 100644 drivers/media/platform/dw100/dw100_regs.h diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 4843fabb8bb2..e88e8569226f 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -258,6 +258,18 @@ config VIDEO_CODA Coda is a range of video codec IPs that supports H.264, MPEG-4, and other video formats. +config VIDEO_DW100 + tristate "DW100 dewarper" + depends on VIDEO_DEV && VIDEO_V4L2 && (ARCH_MXC || COMPILE_TEST) + select VIDEOBUF2_DMA_CONTIG + select V4L2_MEM2MEM_DEV + help + DW100 is a memory-to-memory engine performing geometrical + transformation on source image through a programmable dewarping map. + + To compile this driver as a module, choose M here: the module + will be called dw100. + config VIDEO_IMX_VDOA def_tristate VIDEO_CODA if SOC_IMX6Q || COMPILE_TEST diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 4032816f8e8a..4f3d7ada4eac 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -19,6 +19,7 @@ obj-y += ti-vpe/ obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o obj-$(CONFIG_VIDEO_CODA) += coda/ +obj-$(CONFIG_VIDEO_DW100) += dw100/ obj-$(CONFIG_VIDEO_IMX) += imx/ obj-$(CONFIG_VIDEO_IMX_PXP) += imx-pxp.o diff --git a/drivers/media/platform/dw100/Makefile b/drivers/media/platform/dw100/Makefile new file mode 100644 index 000000000000..102c5d1c70f5 --- /dev/null +++ b/drivers/media/platform/dw100/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_VIDEO_DW100) += dw100.o diff --git a/drivers/media/platform/dw100/dw100.c b/drivers/media/platform/dw100/dw100.c new file mode 100644 index 000000000000..7e1fcdfe5b91 --- /dev/null +++ b/drivers/media/platform/dw100/dw100.c @@ -0,0 +1,1744 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DW100 Hardware dewarper + * + * Copyright 2022 NXP + * Author: Xavier Roumegue (xavier.roumegue@oss.nxp.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "dw100_regs.h" + +#define DRV_NAME "dw100" + +#define MIN_W 176 +#define MIN_H 144 +#define MAX_W 4096 +#define MAX_H 3072 +#define ALIGN_W 3 +#define ALIGN_H 3 + +#define DW100_BLOCK_SIZE 16 + +#define DW100_MIN_LUT_NELEMS (((MIN_W / DW100_BLOCK_SIZE) + 1) \ + * ((MIN_H / DW100_BLOCK_SIZE) + 1)) + +#define DW100_MAX_LUT_NELEMS (((MAX_W / DW100_BLOCK_SIZE) + 1) \ + * ((MAX_H / DW100_BLOCK_SIZE) + 1)) + +static unsigned int debug; +module_param(debug, uint, 0644); +MODULE_PARM_DESC(debug, "Activate debug info"); + +#define dprintk(lvl, dev, fmt, arg...) \ + v4l2_dbg(lvl, debug, &dev->v4l2_dev, "%s: " fmt, __func__, ## arg) + +enum { + V4L2_M2M_SRC = 0, + V4L2_M2M_DST = 1, +}; + +enum { + V4L2_M2M_CAPTURE = 1, + V4L2_M2M_OUTPUT = 2, +}; + +static struct dw100_fmt { + u32 fourcc; + int depth; + u32 types; + u32 reg_format; + bool reg_swap_uv; +} formats[] = { + { + .fourcc = V4L2_PIX_FMT_NV16, + .depth = 16, + .types = V4L2_M2M_OUTPUT | V4L2_M2M_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, + .reg_swap_uv = false, + }, { + .fourcc = V4L2_PIX_FMT_NV61, + .depth = 16, + .types = V4L2_M2M_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, + .reg_swap_uv = true, + }, { + .fourcc = V4L2_PIX_FMT_YUYV, + .depth = 16, + .types = V4L2_M2M_OUTPUT | V4L2_M2M_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED, + .reg_swap_uv = false, + }, { + .fourcc = V4L2_PIX_FMT_UYVY, + .depth = 16, + .types = V4L2_M2M_OUTPUT | V4L2_M2M_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED, + .reg_swap_uv = true, + }, { + .fourcc = V4L2_PIX_FMT_NV12, + .depth = 12, + .types = V4L2_M2M_OUTPUT | V4L2_M2M_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, + .reg_swap_uv = false, + }, { + .fourcc = V4L2_PIX_FMT_NV21, + .depth = 12, + .types = V4L2_M2M_OUTPUT | V4L2_M2M_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, + .reg_swap_uv = true, + }, +}; + +static inline int to_dw100_fmt_type(enum v4l2_buf_type type) +{ + if (V4L2_TYPE_IS_OUTPUT(type)) + return V4L2_M2M_OUTPUT; + else + return V4L2_M2M_CAPTURE; +} + +#define NUM_FORMATS ARRAY_SIZE(formats) + +static struct dw100_fmt *find_format(struct v4l2_format *f) +{ + struct dw100_fmt *fmt; + unsigned int k; + + for (k = 0; k < NUM_FORMATS; k++) { + fmt = &formats[k]; + if ((fmt->fourcc == f->fmt.pix.pixelformat) + && (fmt->types & to_dw100_fmt_type(f->type))) + return fmt; + } + + return NULL; +} + +static inline u32 dw100_bytesperline(struct dw100_fmt *fmt, u32 width) +{ + + switch (fmt->reg_format) { + case DW100_DEWARP_CTRL_FORMAT_YUV422_SP: + case DW100_DEWARP_CTRL_FORMAT_YUV420_SP: + return width; + case DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED: + default: + return (fmt->depth * width) >> 3; + } +} + +static inline u32 dw100_sizeimage(struct dw100_fmt *fmt, u32 width, u32 height) +{ + return (fmt->depth * width * height) >> 3; +} + +struct dw100_device { + struct platform_device *pdev; + struct v4l2_m2m_dev *m2m_dev; + struct v4l2_device v4l2_dev; + struct video_device vfd; +#ifdef CONFIG_MEDIA_CONTROLLER + struct media_device mdev; +#endif + struct mutex vfd_mutex; + spinlock_t irqlock; + void __iomem *mmio; + struct clk_bulk_data *clks; + int num_clks; + struct dentry *debugfs_root; +}; + +static int dw100_dump_regs(struct dw100_device *dw_dev) +{ +#define __DECLARE_REG(x) { #x, x } + int i; + struct reg_desc { + const char * const name; + unsigned int addr; + } dw100_regs[] = { + __DECLARE_REG(DW100_DEWARP_ID), + __DECLARE_REG(DW100_DEWARP_CTRL), + __DECLARE_REG(DW100_MAP_LUT_ADDR), + __DECLARE_REG(DW100_MAP_LUT_SIZE), + __DECLARE_REG(DW100_MAP_LUT_ADDR2), + __DECLARE_REG(DW100_MAP_LUT_SIZE2), + __DECLARE_REG(DW100_SRC_IMG_Y_BASE), + __DECLARE_REG(DW100_SRC_IMG_UV_BASE), + __DECLARE_REG(DW100_SRC_IMG_SIZE), + __DECLARE_REG(DW100_SRC_IMG_STRIDE), + __DECLARE_REG(DW100_DST_IMG_Y_BASE), + __DECLARE_REG(DW100_DST_IMG_UV_BASE), + __DECLARE_REG(DW100_DST_IMG_SIZE), + __DECLARE_REG(DW100_DST_IMG_STRIDE), + __DECLARE_REG(DW100_DST_IMG_Y_SIZE1), + __DECLARE_REG(DW100_DST_IMG_UV_SIZE1), + __DECLARE_REG(DW100_SRC_IMG_Y_BASE2), + __DECLARE_REG(DW100_SRC_IMG_UV_BASE2), + __DECLARE_REG(DW100_SRC_IMG_SIZE2), + __DECLARE_REG(DW100_SRC_IMG_STRIDE2), + __DECLARE_REG(DW100_DST_IMG_Y_BASE2), + __DECLARE_REG(DW100_DST_IMG_UV_BASE2), + __DECLARE_REG(DW100_DST_IMG_SIZE2), + __DECLARE_REG(DW100_DST_IMG_STRIDE2), + __DECLARE_REG(DW100_DST_IMG_Y_SIZE2), + __DECLARE_REG(DW100_DST_IMG_UV_SIZE2), + __DECLARE_REG(DW100_SWAP_CONTROL), + __DECLARE_REG(DW100_VERTICAL_SPLIT_LINE), + __DECLARE_REG(DW100_HORIZON_SPLIT_LINE), + __DECLARE_REG(DW100_SCALE_FACTOR), + __DECLARE_REG(DW100_ROI_START), + __DECLARE_REG(DW100_BOUNDARY_PIXEL), + __DECLARE_REG(DW100_INTERRUPT_STATUS), + __DECLARE_REG(DW100_BUS_CTRL), + __DECLARE_REG(DW100_BUS_CTRL1), + __DECLARE_REG(DW100_BUS_TIME_OUT_CYCLE), + }; + + for (i = 0; i < ARRAY_SIZE(dw100_regs); i++) { + dev_info(&dw_dev->pdev->dev, "%s: %#x\n", + dw100_regs[i].name, + readl(dw_dev->mmio + dw100_regs[i].addr)); + } + + return 0; +} + +struct dw100_q_data { + unsigned int width; + unsigned int height; + unsigned int bytesperline; + unsigned int sizeimage; + unsigned int sequence; + struct dw100_fmt *fmt; + struct v4l2_rect crop; +}; + +struct dw100_ctx { + struct v4l2_fh fh; + struct dw100_device *dw_dev; + struct v4l2_ctrl_handler hdl; + + /* Look Up Table for pixel remapping */ + unsigned int *map; + dma_addr_t map_dma; + size_t map_size; + unsigned int map_width; + unsigned int map_height; + + /* Related colorspace properties propagated from input to output */ + enum v4l2_colorspace colorspace; + enum v4l2_xfer_func xfer_func; + enum v4l2_ycbcr_encoding ycbcr_enc; + enum v4l2_quantization quant; + + /* Source and destination queue data */ + struct dw100_q_data q_data[2]; +}; + +static inline struct dw100_ctx *file2ctx(struct file *file) +{ + return container_of(file->private_data, struct dw100_ctx, fh); +} + +static struct dw100_q_data *get_q_data(struct dw100_ctx *ctx, + enum v4l2_buf_type type) +{ + if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT) + return &ctx->q_data[V4L2_M2M_SRC]; + else + return &ctx->q_data[V4L2_M2M_DST]; +} + +static u32 dw100_get_n_vertices_from_length(u32 length) +{ + u32 n; + + n = length / DW100_BLOCK_SIZE + 1; + if (length % DW100_BLOCK_SIZE) + n += 1; + + return n; +} + +static u16 dw_map_convert_to_UQ12_4(u32 a) +{ + return (u16)((a & 0xFFF) << 4); +} + +static u32 dw_map_format_coordinates(u16 xq, u16 yq) +{ + return (u32)((yq << 16) | xq); +} + + +static u32 *dw100_get_user_map(struct dw100_ctx *ctx) +{ + struct v4l2_ctrl *ctrl = v4l2_ctrl_find(&ctx->hdl, V4L2_CID_DW100_MAPPING); + size_t user_map_size; + + if (ctrl == NULL) { + v4l2_err(&ctx->dw_dev->v4l2_dev, "Mapping control not found !"); + return NULL; + } + + if ((ctrl->elems < DW100_MIN_LUT_NELEMS) + || (ctrl->elems > DW100_MAX_LUT_NELEMS)) + return NULL; + + user_map_size = ctrl->elems * ctrl->elem_size; + + if ((ctrl->elems * ctrl->elem_size) == ctx->map_size) + return ctrl->p_cur.p_u32; + + v4l2_warn(&ctx->dw_dev->v4l2_dev, + "Skipping invalid user map (%zu != %zu)\n", + user_map_size, + ctx->map_size); + + return NULL; +} + +/* + * Create an identity map if not set by the application + * + * A 16 pixels cell size grid is mapped on the destination image. + * The last cells width/height might be lesser than 16 if the destination image + * width/height is not divisible by 16. This dewarping grid map specifies the + * source image pixel location (x, y) on each grid intersection point. + * Bilinear interpolation is used to compute inner cell points locations. + * + * The coordinates are saved in UQ12.4 fixed point format. + * + */ +static int dw100_create_mapping(struct dw100_ctx *ctx) +{ + u32 sw, sh, dw, dh, mw, mh, i, j; + u16 qx, qy, qdx, qdy, qsh, qsw; + bool is_user_map = false; + u32 *user_map; + + sw = ctx->q_data[V4L2_M2M_SRC].width; + dw = ctx->q_data[V4L2_M2M_DST].width; + sh = ctx->q_data[V4L2_M2M_SRC].height; + dh = ctx->q_data[V4L2_M2M_DST].height; + + mw = dw100_get_n_vertices_from_length(dw); + mh = dw100_get_n_vertices_from_length(dh); + + qdx = dw_map_convert_to_UQ12_4(sw) / (mw - 1); + qdy = dw_map_convert_to_UQ12_4(sh) / (mh - 1); + qsh = dw_map_convert_to_UQ12_4(sh); + qsw = dw_map_convert_to_UQ12_4(sw); + + if (ctx->map) + dma_free_coherent(&ctx->dw_dev->pdev->dev, + ctx->map_size, + ctx->map, + ctx->map_dma); + + ctx->map_width = mw; + ctx->map_height = mh; + ctx->map_size = mh * mw * sizeof(u32); + + ctx->map = dma_alloc_coherent(&ctx->dw_dev->pdev->dev, + ctx->map_size, + &ctx->map_dma, + GFP_KERNEL); + + if (!ctx->map) + return -ENOMEM; + + user_map = dw100_get_user_map(ctx); + if (user_map) { + is_user_map = true; + memcpy(ctx->map, user_map, ctx->map_size); + goto out; + } + + for (i = 0, qy = 0, qx = 0; i < mh; i++, qy += qdy, qx = 0) { + if (qy > qsh) + qy = qsh; + for (j = 0; j < mw; j++, qx += qdx) { + if (qx > qsw) + qx = qsw; + ctx->map[i * mw + j] = dw_map_format_coordinates(qx, qy); + } + } +out: + dprintk(1, ctx->dw_dev, + "%dx%d %s mapping created (d:%pa-c:%p) for stream %dx%d->%dx%d\n", + mw, mh, is_user_map ? "user" : "identity", + &ctx->map_dma, ctx->map, sw, sh, dw, dh); + + return 0; +} + +static const struct v4l2_ctrl_config ctrl_custom_lut = { + .id = V4L2_CID_DW100_MAPPING, + .name = "Look-Up Table", + .type = V4L2_CTRL_TYPE_U32, + .min = 0x00000000, + .max = 0xFFFFFFFF, + .step = 1, + .def = 0, + .dims = { DW100_MAX_LUT_NELEMS }, + .flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, +}; + +static int dw100_queue_setup(struct vb2_queue *vq, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], struct device *alloc_devs[]) +{ + struct dw100_ctx *ctx = vb2_get_drv_priv(vq); + struct dw100_q_data *q_data; + unsigned int size, count = *nbuffers; + + q_data = get_q_data(ctx, vq->type); + + size = q_data->sizeimage; + + *nbuffers = count; + + if (*nplanes) + return sizes[0] < size ? -EINVAL : 0; + + *nplanes = 1; + sizes[0] = size; + + dprintk(1, ctx->dw_dev, "Queue %p: get %d buffer(s) of size %d each.\n", + vq, count, size); + + return 0; +} + +static int dw100_buf_prepare(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + struct dw100_device *dw_dev = ctx->dw_dev; + struct dw100_q_data *q_data; + + dprintk(1, dw_dev, "Queue %p: Preparing buffer %p, type: %d\n", + vb->vb2_queue, vb, vb->vb2_queue->type); + + q_data = get_q_data(ctx, vb->vb2_queue->type); + if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { + if (vbuf->field == V4L2_FIELD_ANY) + vbuf->field = V4L2_FIELD_NONE; + if (vbuf->field != V4L2_FIELD_NONE) { + v4l2_err(&dw_dev->v4l2_dev, "%x field isn't supported\n", + vbuf->field); + return -EINVAL; + } + } + + if (vb2_plane_size(vb, 0) < q_data->sizeimage) { + v4l2_err(&dw_dev->v4l2_dev, + "%s data will not fit into plane (%lu < %lu)\n", + __func__, vb2_plane_size(vb, 0), + (long)q_data->sizeimage); + return -EINVAL; + } + + vb2_set_plane_payload(vb, 0, q_data->sizeimage); + + return 0; +} + +static void dw100_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + + dprintk(2, ctx->dw_dev, "Queue %p: Queuing buffer %p.\n", + vb->vb2_queue, vb); + v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); +} + +static int dw100_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct dw100_ctx *ctx = vb2_get_drv_priv(q); + struct dw100_q_data *q_data = get_q_data(ctx, q->type); + + dprintk(1, ctx->dw_dev, "Queue %p: Start Streaming.\n", q); + + q_data->sequence = 0; + + return pm_runtime_resume_and_get(&ctx->dw_dev->pdev->dev); +} + +static void dw100_stop_streaming(struct vb2_queue *q) +{ + struct dw100_ctx *ctx = vb2_get_drv_priv(q); + struct vb2_v4l2_buffer *vbuf; + unsigned long flags; + + dprintk(1, ctx->dw_dev, "Queue %p: Stop Streaming.\n", q); + for (;;) { + if (V4L2_TYPE_IS_OUTPUT(q->type)) + vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + else + vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + if (vbuf == NULL) + break; + spin_lock_irqsave(&ctx->dw_dev->irqlock, flags); + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); + spin_unlock_irqrestore(&ctx->dw_dev->irqlock, flags); + } + + pm_runtime_put_sync(&ctx->dw_dev->pdev->dev); + + if (ctx->map) { + dma_free_coherent(&ctx->dw_dev->pdev->dev, + ctx->map_size, + ctx->map, + ctx->map_dma); + ctx->map = NULL; + } +} + +static const struct vb2_ops dw100_qops = { + .queue_setup = dw100_queue_setup, + .buf_prepare = dw100_buf_prepare, + .buf_queue = dw100_buf_queue, + .start_streaming = dw100_start_streaming, + .stop_streaming = dw100_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +static int dw100_m2m_queue_init(void *priv, struct vb2_queue *src_vq, + struct vb2_queue *dst_vq) +{ + struct dw100_ctx *ctx = priv; + int ret; + + src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; + src_vq->io_modes = VB2_MMAP | VB2_DMABUF; + src_vq->drv_priv = ctx; + src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); + src_vq->ops = &dw100_qops; + src_vq->mem_ops = &vb2_dma_contig_memops; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->lock = &ctx->dw_dev->vfd_mutex; + src_vq->dev = ctx->dw_dev->v4l2_dev.dev; + + ret = vb2_queue_init(src_vq); + if (ret) + return ret; + + dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; + dst_vq->drv_priv = ctx; + dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); + dst_vq->ops = &dw100_qops; + dst_vq->mem_ops = &vb2_dma_contig_memops; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->lock = &ctx->dw_dev->vfd_mutex; + dst_vq->dev = ctx->dw_dev->v4l2_dev.dev; + + return vb2_queue_init(dst_vq); +} + +static int dw100_open(struct file *file) +{ + struct dw100_device *dw_dev = video_drvdata(file); + struct dw100_ctx *ctx; + struct v4l2_ctrl_handler *hdl; + int ret = 0; + + if (mutex_lock_interruptible(&dw_dev->vfd_mutex)) + return -ERESTARTSYS; + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + ret = -ENOMEM; + goto open_unlock; + } + + v4l2_fh_init(&ctx->fh, video_devdata(file)); + file->private_data = &ctx->fh; + ctx->dw_dev = dw_dev; + + hdl = &ctx->hdl; + v4l2_ctrl_handler_init(hdl, 1); + v4l2_ctrl_new_custom(hdl, &ctrl_custom_lut, NULL); + ctx->fh.ctrl_handler = hdl; + + ctx->q_data[V4L2_M2M_SRC].fmt = &formats[0]; + ctx->q_data[V4L2_M2M_SRC].width = 640; + ctx->q_data[V4L2_M2M_SRC].height = 480; + ctx->q_data[V4L2_M2M_SRC].bytesperline = + dw100_bytesperline(&formats[0], 640); + ctx->q_data[V4L2_M2M_SRC].sizeimage = + dw100_sizeimage(&formats[0], 640, 480); + + ctx->q_data[V4L2_M2M_SRC].crop.top = 0; + ctx->q_data[V4L2_M2M_SRC].crop.left = 0; + ctx->q_data[V4L2_M2M_SRC].crop.width = 640; + ctx->q_data[V4L2_M2M_SRC].crop.height = 480; + + ctx->q_data[V4L2_M2M_DST] = ctx->q_data[V4L2_M2M_SRC]; + + ctx->colorspace = V4L2_COLORSPACE_REC709; + ctx->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(ctx->colorspace); + ctx->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(ctx->colorspace); + ctx->quant = V4L2_MAP_QUANTIZATION_DEFAULT(false, + ctx->colorspace, ctx->ycbcr_enc); + + ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dw_dev->m2m_dev, + ctx, &dw100_m2m_queue_init); + + if (IS_ERR(ctx->fh.m2m_ctx)) { + ret = PTR_ERR(ctx->fh.m2m_ctx); + + v4l2_ctrl_handler_free(hdl); + v4l2_fh_exit(&ctx->fh); + kfree(ctx); + goto open_unlock; + } + + v4l2_fh_add(&ctx->fh); + + dprintk(1, dw_dev, "M2M instance created: %p", ctx->fh.m2m_ctx); + +open_unlock: + mutex_unlock(&dw_dev->vfd_mutex); + return ret; +} + +static int dw100_release(struct file *file) +{ + struct dw100_device *dw_dev = video_drvdata(file); + struct dw100_ctx *ctx = file2ctx(file); + + dprintk(1, dw_dev, "Releasing M2M instance: %p", ctx->fh.m2m_ctx); + + v4l2_fh_del(&ctx->fh); + v4l2_fh_exit(&ctx->fh); + v4l2_ctrl_handler_free(&ctx->hdl); + + mutex_lock(&dw_dev->vfd_mutex); + v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); + mutex_unlock(&dw_dev->vfd_mutex); + + if (ctx->map) + dma_free_coherent(&ctx->dw_dev->pdev->dev, + ctx->map_size, + ctx->map, + ctx->map_dma); + + kfree(ctx); + + return 0; +} + +static const struct v4l2_file_operations dw100_fops = { + .owner = THIS_MODULE, + .open = dw100_open, + .release = dw100_release, + .poll = v4l2_m2m_fop_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = v4l2_m2m_fop_mmap, +}; + +static int dw100_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + strscpy(cap->driver, DRV_NAME, sizeof(cap->driver)); + strscpy(cap->card, "DW100 dewarper", sizeof(cap->card)); + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", DRV_NAME); + + return 0; +} + +static int dw100_enum_fmt(struct v4l2_fmtdesc *f) +{ + int i, num = 0; + + for (i = 0; i < NUM_FORMATS; i++) { + if (formats[i].types & to_dw100_fmt_type(f->type)) { + if (num == f->index) { + f->pixelformat = formats[i].fourcc; + return 0; + } + ++num; + } + } + + return -EINVAL; +} + +static int dw100_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + return dw100_enum_fmt(f); +} + +static int dw100_enum_fmt_vid_out(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + return dw100_enum_fmt(f); +} + +static int dw100_g_fmt(struct dw100_ctx *ctx, struct v4l2_format *f) +{ + struct vb2_queue *vq; + struct dw100_q_data *q_data; + + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); + if (!vq) + return -EINVAL; + + q_data = get_q_data(ctx, f->type); + + f->fmt.pix.width = q_data->width; + f->fmt.pix.height = q_data->height; + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.pixelformat = q_data->fmt->fourcc; + f->fmt.pix.bytesperline = q_data->bytesperline; + f->fmt.pix.sizeimage = q_data->sizeimage; + f->fmt.pix.colorspace = ctx->colorspace; + f->fmt.pix.xfer_func = ctx->xfer_func; + f->fmt.pix.ycbcr_enc = ctx->ycbcr_enc; + f->fmt.pix.quantization = ctx->quant; + + return 0; +} + +static int dw100_g_fmt_vid_out(struct file *file, void *priv, + struct v4l2_format *f) +{ + return dw100_g_fmt(file2ctx(file), f); +} + +static int dw100_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + return dw100_g_fmt(file2ctx(file), f); +} + +static int dw100_try_fmt(struct v4l2_format *f, struct dw100_fmt *fmt) +{ + + v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W, ALIGN_W, + &f->fmt.pix.height, MIN_H, MAX_H, ALIGN_H, 0); + + f->fmt.pix.bytesperline = dw100_bytesperline(fmt, f->fmt.pix.width); + f->fmt.pix.sizeimage = dw100_sizeimage(fmt, f->fmt.pix.width, + f->fmt.pix.height); + f->fmt.pix.field = V4L2_FIELD_NONE; + + return 0; +} + +static int dw100_s_fmt(struct dw100_ctx *ctx, struct v4l2_format *f) +{ + struct dw100_q_data *q_data; + struct vb2_queue *vq; + + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); + if (!vq) + return -EINVAL; + + q_data = get_q_data(ctx, f->type); + if (!q_data) + return -EINVAL; + + if (vb2_is_busy(vq)) { + v4l2_err(&ctx->dw_dev->v4l2_dev, "%s queue busy\n", __func__); + return -EBUSY; + } + + q_data->fmt = find_format(f); + q_data->width = f->fmt.pix.width; + q_data->height = f->fmt.pix.height; + q_data->bytesperline = f->fmt.pix.bytesperline; + q_data->sizeimage = f->fmt.pix.sizeimage; + + q_data->crop.top = 0; + q_data->crop.left = 0; + q_data->crop.width = f->fmt.pix.width; + q_data->crop.height = f->fmt.pix.height; + + dprintk(1, ctx->dw_dev, + "Setting format for type %d, wxh: %dx%d, fmt: %d\n", + f->type, q_data->width, q_data->height, q_data->fmt->fourcc); + + return 0; +} + +static int dw100_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct dw100_fmt *fmt; + struct dw100_ctx *ctx = file2ctx(file); + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + fmt = find_format(f); + if (!fmt) { + f->fmt.pix.pixelformat = formats[0].fourcc; + fmt = find_format(f); + } + + f->fmt.pix.colorspace = ctx->colorspace; + f->fmt.pix.xfer_func = ctx->xfer_func; + f->fmt.pix.ycbcr_enc = ctx->ycbcr_enc; + f->fmt.pix.quantization = ctx->quant; + + return dw100_try_fmt(f, fmt); +} + +static int dw100_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct dw100_ctx *ctx = file2ctx(file); + int ret; + + ret = dw100_try_fmt_vid_cap(file, priv, f); + if (ret) + return ret; + + ret = dw100_s_fmt(ctx, f); + if (ret) + return ret; + + return 0; +} + +static int dw100_try_fmt_vid_out(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct dw100_fmt *fmt; + + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + + fmt = find_format(f); + if (!fmt) { + f->fmt.pix.pixelformat = formats[0].fourcc; + fmt = find_format(f); + } + + if (!f->fmt.pix.colorspace) + f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709; + + return dw100_try_fmt(f, fmt); +} + +static int dw100_s_fmt_vid_out(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct dw100_ctx *ctx = file2ctx(file); + int ret; + + ret = dw100_try_fmt_vid_out(file, priv, f); + if (ret) + return ret; + + ret = dw100_s_fmt(ctx, f); + if (ret) + return ret; + + ctx->colorspace = f->fmt.pix.colorspace; + ctx->xfer_func = f->fmt.pix.xfer_func; + ctx->ycbcr_enc = f->fmt.pix.ycbcr_enc; + ctx->quant = f->fmt.pix.quantization; + + return 0; +} + +static int dw100_g_selection(struct file *file, void *fh, + struct v4l2_selection *sel) +{ + struct dw100_ctx *ctx = file2ctx(file); + struct dw100_q_data *src_q_data, *dst_q_data; + + if ((sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) && + (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) + return -EINVAL; + + src_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); + dst_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); + + switch (sel->target) { + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + sel->r.top = 0; + sel->r.left = 0; + sel->r.width = src_q_data->width; + sel->r.height = src_q_data->height; + break; + case V4L2_SEL_TGT_CROP: + sel->r.top = src_q_data->crop.top; + sel->r.left = src_q_data->crop.left; + sel->r.width = src_q_data->crop.width; + sel->r.height = src_q_data->crop.height; + break; + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + case V4L2_SEL_TGT_COMPOSE: + sel->r.top = 0; + sel->r.left = 0; + sel->r.width = dst_q_data->width; + sel->r.height = dst_q_data->height; + break; + default: + return -EINVAL; + } + + dprintk(1, ctx->dw_dev, + "<<< Buffer Type: %d Target: %d Rect: %dx%d@%d.%d\n", + sel->type, sel->target, + sel->r.width, sel->r.height, sel->r.left, sel->r.top); + + return 0; +} + +#define MIN(a, b) ((a) < (b) ? (a):(b)) +#define MAX(a, b) ((a) > (b) ? (a):(b)) +static int dw100_s_selection(struct file *file, void *fh, + struct v4l2_selection *sel) +{ + struct dw100_ctx *ctx = file2ctx(file); + struct dw100_q_data *src_q_data, *dst_q_data; + u32 qscalex, qscaley, qscale; + int x, y, w, h; + + if ((sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) && + (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) + return -EINVAL; + + src_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); + dst_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); + + dprintk(1, ctx->dw_dev, + ">>> Buffer Type: %d Target: %d Rect: %dx%d@%d.%d\n", + sel->type, sel->target, + sel->r.width, sel->r.height, sel->r.left, sel->r.top); + + if ((sel->r.top < 0) || (sel->r.left < 0)) + return -EINVAL; + + switch (sel->target) { + case V4L2_SEL_TGT_CROP: + /* UQ16.16 for float operations */ + if ((sel->r.left + sel->r.width > src_q_data->width) || + (sel->r.top + sel->r.height > src_q_data->height)) + return -EINVAL; + qscalex = (sel->r.width << 16) / src_q_data->width; + qscaley = (sel->r.height << 16) / src_q_data->height; + y = sel->r.top; + x = sel->r.left; + if (qscalex == qscaley) { + qscale = qscalex; + } else { + switch (sel->flags) { + case 0: + qscale = (qscalex + qscaley) / 2; + break; + case V4L2_SEL_FLAG_GE: + qscale = MAX(qscaley, qscalex); + break; + case V4L2_SEL_FLAG_LE: + qscale = MIN(qscaley, qscalex); + break; + case V4L2_SEL_FLAG_LE | V4L2_SEL_FLAG_GE: + return -ERANGE; + default: + return -EINVAL; + } + } + + w = (u32)((((u64)src_q_data->width << 16) * qscale) >> 32); + h = (u32)((((u64)src_q_data->height << 16) * qscale) >> 32); + x = x + (sel->r.width - w) / 2; + y = y + (sel->r.height - h) / 2; + x = MIN(src_q_data->width - w, MAX(0, x)); + y = MIN(src_q_data->height - h, MAX(0, y)); + + src_q_data->crop.top = sel->r.top = y; + src_q_data->crop.left = sel->r.left = x; + src_q_data->crop.width = sel->r.width = w; + src_q_data->crop.height = sel->r.height = h; + break; + case V4L2_SEL_TGT_COMPOSE: + if ((sel->r.left + sel->r.width > dst_q_data->width) || + (sel->r.top + sel->r.height > dst_q_data->height)) + return -EINVAL; + sel->r.top = 0; + sel->r.left = 0; + sel->r.width = dst_q_data->width; + sel->r.height = dst_q_data->height; + break; + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + default: + return -EINVAL; + } + + dprintk(1, ctx->dw_dev, + "<<< Buffer Type: %d Target: %d Rect: %dx%d@%d.%d\n", + sel->type, sel->target, + sel->r.width, sel->r.height, sel->r.left, sel->r.top); + + return 0; +} + +static const struct v4l2_ioctl_ops dw100_ioctl_ops = { + .vidioc_querycap = dw100_querycap, + + .vidioc_enum_fmt_vid_cap = dw100_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = dw100_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = dw100_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = dw100_s_fmt_vid_cap, + + .vidioc_enum_fmt_vid_out = dw100_enum_fmt_vid_out, + .vidioc_g_fmt_vid_out = dw100_g_fmt_vid_out, + .vidioc_try_fmt_vid_out = dw100_try_fmt_vid_out, + .vidioc_s_fmt_vid_out = dw100_s_fmt_vid_out, + + .vidioc_g_selection = dw100_g_selection, + .vidioc_s_selection = dw100_s_selection, + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, + + .vidioc_streamon = v4l2_m2m_ioctl_streamon, + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, + + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static void dw100_job_finish(struct dw100_device *dw_dev, bool with_error) +{ + struct dw100_ctx *curr_ctx; + struct vb2_v4l2_buffer *src_vb, *dst_vb; + unsigned long flags; + enum vb2_buffer_state buf_state; + + curr_ctx = v4l2_m2m_get_curr_priv(dw_dev->m2m_dev); + + if (curr_ctx == NULL) { + v4l2_err(&dw_dev->v4l2_dev, + "Instance released before the end of transaction\n"); + return; + } + + src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx); + dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx); + + if (likely(!with_error)) + buf_state = VB2_BUF_STATE_DONE; + else + buf_state = VB2_BUF_STATE_ERROR; + + spin_lock_irqsave(&dw_dev->irqlock, flags); + v4l2_m2m_buf_done(src_vb, buf_state); + v4l2_m2m_buf_done(dst_vb, buf_state); + spin_unlock_irqrestore(&dw_dev->irqlock, flags); + + dprintk(2, dw_dev, "Finishing transaction with%s error(s)\n", + with_error ? "" : "out"); + + v4l2_m2m_job_finish(dw_dev->m2m_dev, curr_ctx->fh.m2m_ctx); +} + +static void dw100_hw_reset(struct dw100_device *dw_dev) +{ + u32 val; + + val = readl(dw_dev->mmio + DW100_DEWARP_CTRL); + val |= DW100_DEWARP_CTRL_ENABLE; + val |= DW100_DEWARP_CTRL_SOFT_RESET; + writel(val, dw_dev->mmio + DW100_DEWARP_CTRL); + val &= ~DW100_DEWARP_CTRL_SOFT_RESET; + writel(val, dw_dev->mmio + DW100_DEWARP_CTRL); +} + +static void _dw100_hw_set_master_bus_enable( + struct dw100_device *dw_dev, unsigned int enable) +{ + u32 val; + void __iomem *addr = dw_dev->mmio + DW100_BUS_CTRL; + + dprintk(3, dw_dev, "%sable master bus\n", enable ? "En" : "Dis"); + + val = readl(addr); + + if (enable) + val |= DW100_BUS_CTRL_AXI_MASTER_ENABLE; + else + val &= ~DW100_BUS_CTRL_AXI_MASTER_ENABLE; + + writel(val, addr); +} + +static void dw100_hw_master_bus_enable(struct dw100_device *dw_dev) +{ + _dw100_hw_set_master_bus_enable(dw_dev, 1); +} + +static void dw100_hw_master_bus_disable(struct dw100_device *dw_dev) +{ + + _dw100_hw_set_master_bus_enable(dw_dev, 0); +} + +static void dw100_hw_dewarp_start(struct dw100_device *dw_dev) +{ + u32 val; + void __iomem *addr = dw_dev->mmio + DW100_DEWARP_CTRL; + + val = readl(addr); + + dprintk(3, dw_dev, "Starting Hardware CTRL:%x\n", val); + writel(val | DW100_DEWARP_CTRL_START, addr); + writel(val, addr); +} + +static void dw100_hw_init_ctrl(struct dw100_device *dw_dev) +{ + u32 val; + void __iomem *addr = dw_dev->mmio + DW100_DEWARP_CTRL; + /* + * Input format YUV422_SP + * Output format YUV422_SP + * No hardware handshake (SW) + * No automatic double src buffering (Single) + * No automatic double dst buffering (Single) + * No Black Line + * Prefetch image pixel traversal + */ + + val = DW100_DEWARP_CTRL_ENABLE + /* Valid only for auto prefetch mode*/ + | DW100_DEWARP_CTRL_PREFETCH_THRESHOLD(32); + + /* + * Calculation mode required to support any scaling factor, + * but x4 slower than traversal mode. + * + * DW100_DEWARP_CTRL_PREFETCH_MODE_TRAVERSAL + * DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION + * DW100_DEWARP_CTRL_PREFETCH_MODE_AUTO + * + * TODO: Find heuristics requiring calculation mode + * + */ + val |= DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION; + + writel(val, addr); +} + +static void dw100_hw_set_pixel_boundary(struct dw100_device *dw_dev) +{ + u32 val; + void __iomem *addr = dw_dev->mmio + DW100_BOUNDARY_PIXEL; + + val = DW100_BOUNDARY_PIXEL_V(128) + | DW100_BOUNDARY_PIXEL_U(128) + | DW100_BOUNDARY_PIXEL_Y(0); + + writel(val, addr); +} + +static void dw100_hw_set_scale(struct dw100_device *dw_dev, u8 scale) +{ + void __iomem *addr = dw_dev->mmio + DW100_SCALE_FACTOR; + + dprintk(1, dw_dev, "Setting scale factor to %d\n", scale); + + writel(scale, addr); +} + +static void dw100_hw_set_roi(struct dw100_device *dw_dev, u32 x, u32 y) +{ + u32 val; + void __iomem *addr = dw_dev->mmio + DW100_ROI_START; + + dprintk(1, dw_dev, "Setting ROI region to %d.%d\n", x, y); + + val = DW100_ROI_START_X(x) | DW100_ROI_START_Y(y); + + writel(val, addr); +} + +static void dw100_hw_set_src_crop(struct dw100_device *dw_dev, + struct dw100_q_data *src_q_data, + struct dw100_q_data *dst_q_data) +{ + struct v4l2_rect *rect = &src_q_data->crop; + u32 src_scale, qscale, left_scale, top_scale; + + /* HW Scale is UQ1.7 encoded */ + src_scale = (rect->width << 7) / src_q_data->width; + dw100_hw_set_scale(dw_dev, src_scale); + + qscale = (dst_q_data->width << 7) / src_q_data->width; + + left_scale = (((rect->left << 7) * qscale) >> 14); + top_scale = (((rect->top << 7) * qscale) >> 14); + + dw100_hw_set_roi(dw_dev, left_scale, top_scale); +} + +static void dw100_hw_set_source(struct dw100_device *dw_dev, + struct dw100_q_data *q_data, + dma_addr_t addr) +{ + u32 width, height, stride, fourcc, val; + struct dw100_fmt *fmt = q_data->fmt; + + width = q_data->width; + height = q_data->height; + stride = q_data->bytesperline; + fourcc = q_data->fmt->fourcc; + + dprintk(3, dw_dev, "Set HW source registers for %dx%d - stride %d, pixfmt: %x, dma:%pa\n", + width, height, stride, fourcc, &addr); + + /* Pixel Format */ + val = readl(dw_dev->mmio + DW100_DEWARP_CTRL); + + val &= ~DW100_DEWARP_CTRL_INPUT_FORMAT_MASK; + val |= DW100_DEWARP_CTRL_INPUT_FORMAT(fmt->reg_format); + + writel(val, dw_dev->mmio + DW100_DEWARP_CTRL); + + /* Swap */ + val = readl(dw_dev->mmio + DW100_SWAP_CONTROL); + + val &= ~DW100_SWAP_CONTROL_SRC_MASK; + /* + * Data swapping is performed only on Y plane for source image. + */ + if (fmt->reg_swap_uv + && (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)) + val |= DW100_SWAP_CONTROL_SRC( + DW100_SWAP_CONTROL_Y( + DW100_SWAP_CONTROL_BYTE + ) + ); + + writel(val, dw_dev->mmio + DW100_SWAP_CONTROL); + + /* Image resolution */ + writel(DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height), + dw_dev->mmio + DW100_SRC_IMG_SIZE); + + writel(stride, dw_dev->mmio + DW100_SRC_IMG_STRIDE); + + /* Buffers */ + writel(DW100_IMG_Y_BASE(addr), dw_dev->mmio + DW100_SRC_IMG_Y_BASE); + writel(DW100_IMG_UV_BASE((addr + (stride * height))), + dw_dev->mmio + DW100_SRC_IMG_UV_BASE); +} + +static void dw100_hw_set_destination(struct dw100_device *dw_dev, + struct dw100_q_data *q_data, + struct dw100_fmt *ifmt, + dma_addr_t addr) +{ + u32 width, height, stride, fourcc, val; + struct dw100_fmt *fmt = q_data->fmt; + + width = q_data->width; + height = q_data->height; + stride = q_data->bytesperline; + fourcc = q_data->fmt->fourcc; + + dprintk(3, dw_dev, "Set HW source registers for %dx%d - stride %d, pixfmt: %x, dma:%pa\n", + width, height, stride, fourcc, &addr); + + /* Pixel Format */ + val = readl(dw_dev->mmio + DW100_DEWARP_CTRL); + + val &= ~DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK; + val |= DW100_DEWARP_CTRL_OUTPUT_FORMAT(fmt->reg_format); + + writel(val, dw_dev->mmio + DW100_DEWARP_CTRL); + + /* Swap */ + val = readl(dw_dev->mmio + DW100_SWAP_CONTROL); + + val &= ~DW100_SWAP_CONTROL_DST_MASK; + + /* + * Avoid to swap twice + */ + if (fmt->reg_swap_uv + ^ (ifmt->reg_swap_uv + && (ifmt->reg_format != DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED) + ) + ) { + if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED) + val |= DW100_SWAP_CONTROL_DST( + DW100_SWAP_CONTROL_Y( + DW100_SWAP_CONTROL_BYTE + ) + ); + else + val |= DW100_SWAP_CONTROL_DST( + DW100_SWAP_CONTROL_UV( + DW100_SWAP_CONTROL_BYTE) + ); + } + + writel(val, dw_dev->mmio + DW100_SWAP_CONTROL); + + /* Image resolution */ + writel(DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height), + dw_dev->mmio + DW100_DST_IMG_SIZE); + writel(stride, dw_dev->mmio + DW100_DST_IMG_STRIDE); + + val = ALIGN(stride * height, 16); + writel(DW100_IMG_Y_BASE(addr), dw_dev->mmio + DW100_DST_IMG_Y_BASE); + writel(DW100_IMG_UV_BASE(addr + val), + dw_dev->mmio + DW100_DST_IMG_UV_BASE); + writel(DW100_DST_IMG_Y_SIZE(val), + dw_dev->mmio + DW100_DST_IMG_Y_SIZE1); + + if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV420_SP) + val /= 2; + + writel(DW100_DST_IMG_UV_SIZE(val), + dw_dev->mmio + DW100_DST_IMG_UV_SIZE1); +} + +static void dw100_hw_set_mapping(struct dw100_device *dw_dev, + dma_addr_t addr, + u32 width, + u32 height) +{ + dprintk(1, dw_dev, "Set HW mapping registers for %dx%d addr:%pa", + width, height, &addr); + + writel(DW100_MAP_LUT_ADDR_ADDR(addr), dw_dev->mmio + DW100_MAP_LUT_ADDR); + writel(DW100_MAP_LUT_SIZE_WIDTH(width) + | DW100_MAP_LUT_SIZE_HEIGHT(height), + dw_dev->mmio + DW100_MAP_LUT_SIZE); +} + +static void dw100_hw_clear_irq(struct dw100_device *dw_dev, unsigned int irq) +{ + writel(DW100_INTERRUPT_STATUS_INT_CLEAR(irq), + dw_dev->mmio + DW100_INTERRUPT_STATUS); +} + +static void dw100_hw_enable_irq(struct dw100_device *dw_dev) +{ + writel(DW100_INTERRUPT_STATUS_INT_ENABLE_MASK, + dw_dev->mmio + DW100_INTERRUPT_STATUS); +} + +static void dw100_hw_disable_irq(struct dw100_device *dw_dev) +{ + writel(0, dw_dev->mmio + DW100_INTERRUPT_STATUS); +} + +static bool dw100_hw_is_frame_running(struct dw100_device *dw_dev) +{ + bool is_running = readl(dw_dev->mmio + DW100_INTERRUPT_STATUS) + & DW100_INTERRUPT_STATUS_FRAME_BUSY; + + return is_running; +} + +static u32 dw_hw_get_pending_irqs(struct dw100_device *dw_dev) +{ + u32 val; + + val = readl(dw_dev->mmio + DW100_INTERRUPT_STATUS); + + return DW100_INTERRUPT_STATUS_INT_STATUS(val); +} + +static irqreturn_t dw100_irq_handler(int irq, void *dev_id) +{ + struct dw100_device *dw_dev = dev_id; + u32 pending_irqs, err_irqs, frame_done_irq; + bool with_error = true; + + pending_irqs = dw_hw_get_pending_irqs(dw_dev); + frame_done_irq = pending_irqs & DW100_INTERRUPT_STATUS_INT_FRAME_DONE; + err_irqs = DW100_INTERRUPT_STATUS_INT_ERR_STATUS(pending_irqs); + + if (frame_done_irq) { + dprintk(3, dw_dev, "Frame done interrupt\n"); + with_error = false; + err_irqs &= ~DW100_INTERRUPT_STATUS_INT_ERR_STATUS( + DW100_INTERRUPT_STATUS_INT_ERR_FRAME_DONE); + } + + if (err_irqs) + v4l2_err(&dw_dev->v4l2_dev, "Interrupt error: %#x\n", err_irqs); + + dw100_hw_disable_irq(dw_dev); + dw100_hw_master_bus_disable(dw_dev); + dw100_hw_clear_irq(dw_dev, pending_irqs + | DW100_INTERRUPT_STATUS_INT_ERR_TIME_OUT); + + dw100_job_finish(dw_dev, with_error); + + return IRQ_HANDLED; +} + +static void dw100_start(struct dw100_ctx *ctx, struct vb2_v4l2_buffer *in_vb, + struct vb2_v4l2_buffer *out_vb) +{ + struct dw100_device *dw_dev = ctx->dw_dev; + dma_addr_t p_in, p_out; + + p_in = vb2_dma_contig_plane_dma_addr(&in_vb->vb2_buf, 0); + p_out = vb2_dma_contig_plane_dma_addr(&out_vb->vb2_buf, 0); + if (!p_in || !p_out) { + v4l2_err(&dw_dev->v4l2_dev, + "Acquiring DMA addresses of buffers failed\n"); + return; + } + + out_vb->sequence = + get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE)->sequence++; + in_vb->sequence = + get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT)->sequence++; + + dprintk(1, ctx->dw_dev, + "Starting queues %p->%p buffers d:%pa->d:%pa, sequence %d->%d\n", + v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT), + v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE), + &p_in, &p_out, in_vb->sequence, out_vb->sequence); + + out_vb->vb2_buf.timestamp = in_vb->vb2_buf.timestamp; + out_vb->field = in_vb->field; + if (in_vb->flags & V4L2_BUF_FLAG_TIMECODE) + out_vb->timecode = in_vb->timecode; + out_vb->flags = in_vb->flags & + (V4L2_BUF_FLAG_TIMECODE | + V4L2_BUF_FLAG_KEYFRAME | + V4L2_BUF_FLAG_PFRAME | + V4L2_BUF_FLAG_BFRAME | + V4L2_BUF_FLAG_TIMESTAMP_MASK | + V4L2_BUF_FLAG_TSTAMP_SRC_MASK); + + /* Now, let's deal with hardware ... */ + dw100_hw_master_bus_disable(dw_dev); + if (!ctx->map) + dw100_create_mapping(ctx); + + dw100_hw_init_ctrl(dw_dev); + dw100_hw_set_pixel_boundary(dw_dev); + dw100_hw_set_src_crop(dw_dev, &ctx->q_data[V4L2_M2M_SRC], + &ctx->q_data[V4L2_M2M_DST]); + dw100_hw_set_source(dw_dev, &ctx->q_data[V4L2_M2M_SRC], p_in); + dw100_hw_set_destination(dw_dev, &ctx->q_data[V4L2_M2M_DST], + ctx->q_data[V4L2_M2M_SRC].fmt, p_out); + dw100_hw_set_mapping(dw_dev, ctx->map_dma, + ctx->map_width, ctx->map_height); + dw100_hw_enable_irq(dw_dev); + dw100_hw_dewarp_start(dw_dev); + + /* Enable Bus */ + dw100_hw_master_bus_enable(dw_dev); +} + +static void dw100_device_run(void *priv) +{ + struct dw100_ctx *ctx = priv; + struct vb2_v4l2_buffer *src_buf, *dst_buf; + + src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); + + dw100_start(ctx, src_buf, dst_buf); +} + +static int dw100_job_ready(void *priv) +{ + struct dw100_ctx *ctx = priv; + + if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < 1 || + v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < 1) { + dprintk(1, ctx->dw_dev, "Not enough buffers available\n"); + return 0; + } + + if (dw100_hw_is_frame_running(ctx->dw_dev)) { + dprintk(1, ctx->dw_dev, "HW still running a frame\n"); + return 0; + } + + return 1; +} + +static const struct v4l2_m2m_ops dw100_m2m_ops = { + .device_run = dw100_device_run, + .job_ready = dw100_job_ready, +}; + +#ifdef CONFIG_MEDIA_CONTROLLER +static const struct media_device_ops dw100_media_ops = { + .req_validate = vb2_request_validate, + .req_queue = v4l2_m2m_request_queue, +}; +#endif + +static struct video_device *dw100_init_video_device(struct dw100_device *dw_dev) +{ + struct video_device *vfd = &dw_dev->vfd; + + vfd->vfl_dir = VFL_DIR_M2M; + vfd->fops = &dw100_fops; + vfd->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING; + vfd->ioctl_ops = &dw100_ioctl_ops; + vfd->minor = -1; + vfd->release = video_device_release_empty; + vfd->v4l2_dev = &dw_dev->v4l2_dev; + vfd->lock = &dw_dev->vfd_mutex; + + strncpy(vfd->name, DRV_NAME, sizeof(vfd->name)); + mutex_init(vfd->lock); + video_set_drvdata(vfd, dw_dev); + + return vfd; +} + +static int dw100_dump_regs_show(struct seq_file *m, void *private) +{ + struct dw100_device *dw_dev = m->private; + int ret; + + ret = pm_runtime_resume_and_get(&dw_dev->pdev->dev); + if (ret < 0) + return ret; + + ret = dw100_dump_regs(dw_dev); + + pm_runtime_put_sync(&dw_dev->pdev->dev); + + return ret; +} +DEFINE_SHOW_ATTRIBUTE(dw100_dump_regs); + +static void dw100_debugfs_init(struct dw100_device *dw_dev) +{ + dw_dev->debugfs_root = + debugfs_create_dir(dev_name(&dw_dev->pdev->dev), NULL); + + debugfs_create_file("dump_regs", 0600, dw_dev->debugfs_root, dw_dev, + &dw100_dump_regs_fops); +} + +static void dw100_debugfs_exit(struct dw100_device *dw_dev) +{ + debugfs_remove_recursive(dw_dev->debugfs_root); +} + +static int dw100_probe(struct platform_device *pdev) +{ + struct dw100_device *dw_dev; + struct video_device *vfd; + struct resource *res; + int ret = 0; + int irq; + + dw_dev = devm_kzalloc(&pdev->dev, sizeof(*dw_dev), GFP_KERNEL); + if (!dw_dev) + return -ENOMEM; + dw_dev->pdev = pdev; + + ret = devm_clk_bulk_get_all(&pdev->dev, &dw_dev->clks); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to get clocks: %d\n", ret); + return ret; + } + dw_dev->num_clks = ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dw_dev->mmio = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dw_dev->mmio)) + return PTR_ERR(dw_dev->mmio); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, dw100_irq_handler, + IRQF_ONESHOT, dev_name(&pdev->dev), dw_dev); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, dw_dev); + + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to enable clks: %d\n", ret); + goto err_clk; + } + + dw100_hw_reset(dw_dev); + + pm_runtime_put_sync(&pdev->dev); + + spin_lock_init(&dw_dev->irqlock); + + ret = v4l2_device_register(&pdev->dev, &dw_dev->v4l2_dev); + if (ret) + goto err_clk; + + vfd = dw100_init_video_device(dw_dev); + + dw_dev->m2m_dev = v4l2_m2m_init(&dw100_m2m_ops); + if (IS_ERR(dw_dev->m2m_dev)) { + v4l2_err(&dw_dev->v4l2_dev, "Failed to init mem2mem device\n"); + ret = PTR_ERR(dw_dev->m2m_dev); + goto err_v4l2; + } + +#ifdef CONFIG_MEDIA_CONTROLLER + dw_dev->mdev.dev = &pdev->dev; + strscpy(dw_dev->mdev.model, "dw100", sizeof(dw_dev->mdev.model)); + strscpy(dw_dev->mdev.bus_info, "platform:dw100", + sizeof(dw_dev->mdev.bus_info)); + media_device_init(&dw_dev->mdev); + dw_dev->mdev.ops = &dw100_media_ops; + dw_dev->v4l2_dev.mdev = &dw_dev->mdev; +#endif + + ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1); + if (ret) { + v4l2_err(&dw_dev->v4l2_dev, "Failed to register video device\n"); + goto err_m2m; + } + +#ifdef CONFIG_MEDIA_CONTROLLER + ret = v4l2_m2m_register_media_controller(dw_dev->m2m_dev, vfd, + MEDIA_ENT_F_PROC_VIDEO_SCALER); + if (ret) { + v4l2_err(&dw_dev->v4l2_dev, "Failed to init mem2mem media controller\n"); + goto error_v4l2; + } + + ret = media_device_register(&dw_dev->mdev); + if (ret) { + v4l2_err(&dw_dev->v4l2_dev, "Failed to register mem2mem media device\n"); + goto error_m2m_mc; + } +#endif + + dw100_debugfs_init(dw_dev); + + v4l2_info(&dw_dev->v4l2_dev, + "dw100 v4l2 m2m registered as /dev/video%d\n", vfd->num); + + return 0; +#ifdef CONFIG_MEDIA_CONTROLLER +error_m2m_mc: + v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev); +error_v4l2: + video_unregister_device(vfd); +#endif +err_m2m: + v4l2_m2m_release(dw_dev->m2m_dev); +err_v4l2: + v4l2_device_unregister(&dw_dev->v4l2_dev); +err_clk: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int dw100_remove(struct platform_device *pdev) +{ + struct dw100_device *dw_dev = platform_get_drvdata(pdev); + + dw100_debugfs_exit(dw_dev); + + pm_runtime_disable(&pdev->dev); + +#ifdef CONFIG_MEDIA_CONTROLLER + media_device_unregister(&dw_dev->mdev); + v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev); + media_device_cleanup(&dw_dev->mdev); +#endif + + video_unregister_device(&dw_dev->vfd); + v4l2_m2m_release(dw_dev->m2m_dev); + v4l2_device_unregister(&dw_dev->v4l2_dev); + + return 0; +} + +static int __maybe_unused dw100_runtime_suspend(struct device *dev) +{ + struct dw100_device *dw_dev = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(dw_dev->num_clks, dw_dev->clks); + + return 0; +} + +static int __maybe_unused dw100_runtime_resume(struct device *dev) +{ + struct dw100_device *dw_dev = dev_get_drvdata(dev); + + return clk_bulk_prepare_enable(dw_dev->num_clks, dw_dev->clks); +} + +static const struct dev_pm_ops dw100_pm = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(dw100_runtime_suspend, + dw100_runtime_resume, NULL) +}; + +static const struct of_device_id dw100_dt_ids[] = { + { .compatible = "nxp,dw100", .data = NULL }, + { }, +}; +MODULE_DEVICE_TABLE(of, dw100_dt_ids); + +static struct platform_driver dw100_driver = { + .probe = dw100_probe, + .remove = dw100_remove, + .driver = { + .name = DRV_NAME, + .pm = &dw100_pm, + .of_match_table = dw100_dt_ids, + }, +}; + +module_platform_driver(dw100_driver); + +MODULE_DESCRIPTION("DW100 Hardware dewarper"); +MODULE_AUTHOR("Xavier Roumegue "); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/dw100/dw100_regs.h b/drivers/media/platform/dw100/dw100_regs.h new file mode 100644 index 000000000000..fe16dbaa5f06 --- /dev/null +++ b/drivers/media/platform/dw100/dw100_regs.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * DW100 Hardware dewarper + * + * Copyright 2022 NXP + * Author: Xavier Roumegue (xavier.roumegue@oss.nxp.com) + * + */ + +#ifndef _DW100_REGS_H_ +#define _DW100_REGS_H_ + +/* AHB register offset */ +#define DW100_DEWARP_ID 0x00 +#define DW100_DEWARP_CTRL 0x04 +#define DW100_DEWARP_CTRL_ENABLE BIT(0) +#define DW100_DEWARP_CTRL_START BIT(1) +#define DW100_DEWARP_CTRL_SOFT_RESET BIT(2) +#define DW100_DEWARP_CTRL_FORMAT_YUV422_SP (0UL) +#define DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED (1UL) +#define DW100_DEWARP_CTRL_FORMAT_YUV420_SP (2UL) +#define DW100_DEWARP_CTRL_INPUT_FORMAT_MASK GENMASK(5, 4) +#define DW100_DEWARP_CTRL_INPUT_FORMAT(x) ((x) << 4) +#define DW100_DEWARP_CTRL_OUTPUT_FORMAT(x) ((x) << 6) +#define DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK GENMASK(7, 6) +#define DW100_DEWARP_CTRL_SRC_AUTO_SHADOW BIT(8) +#define DW100_DEWARP_CTRL_HW_HANDSHAKE BIT(9) +#define DW100_DEWARP_CTRL_DST_AUTO_SHADOW BIT(10) +#define DW100_DEWARP_CTRL_SPLIT_LINE BIT(11) +#define DW100_DEWARP_CTRL_PREFETCH_MODE_MASK GENMASK(17, 16) +#define DW100_DEWARP_CTRL_PREFETCH_MODE_TRAVERSAL (0UL << 16) +#define DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION (1UL << 16) +#define DW100_DEWARP_CTRL_PREFETCH_MODE_AUTO (2UL << 16) +#define DW100_DEWARP_CTRL_PREFETCH_THRESHOLD_MASK GENMASK(24, 18) +#define DW100_DEWARP_CTRL_PREFETCH_THRESHOLD(x) ((x) << 18) + +#define DW100_MAP_LUT_ADDR 0x08 +#define DW100_MAP_LUT_ADDR_ADDR(addr) (((addr) >> 4) & GENMASK(29, 0)) +#define DW100_MAP_LUT_SIZE 0x0C +#define DW100_MAP_LUT_SIZE_WIDTH(w) (((w) & GENMASK(10, 0)) << 0) +#define DW100_MAP_LUT_SIZE_HEIGHT(h) (((h) & GENMASK(10, 0)) << 16) +#define DW100_SRC_IMG_Y_BASE 0x10 +#define DW100_IMG_Y_BASE(base) (((base) >> 4) & GENMASK(29, 0)) +#define DW100_SRC_IMG_UV_BASE 0x14 +#define DW100_IMG_UV_BASE(base) (((base) >> 4) & GENMASK(29, 0)) +#define DW100_SRC_IMG_SIZE 0x18 +#define DW100_IMG_SIZE_WIDTH(w) (((w) & GENMASK(12, 0)) << 0) +#define DW100_IMG_SIZE_HEIGHT(h) (((h) & GENMASK(12, 0)) << 16) + +#define DW100_SRC_IMG_STRIDE 0x1C +#define DW100_MAP_LUT_ADDR2 0x20 +#define DW100_MAP_LUT_SIZE2 0x24 +#define DW100_SRC_IMG_Y_BASE2 0x28 +#define DW100_SRC_IMG_UV_BASE2 0x2C +#define DW100_SRC_IMG_SIZE2 0x30 +#define DW100_SRC_IMG_STRIDE2 0x34 +#define DW100_DST_IMG_Y_BASE 0x38 +#define DW100_DST_IMG_UV_BASE 0x3C +#define DW100_DST_IMG_SIZE 0x40 +#define DW100_DST_IMG_STRIDE 0x44 +#define DW100_DST_IMG_Y_BASE2 0x48 +#define DW100_DST_IMG_UV_BASE2 0x4C +#define DW100_DST_IMG_SIZE2 0x50 +#define DW100_DST_IMG_STRIDE2 0x54 +#define DW100_SWAP_CONTROL 0x58 +#define DW100_SWAP_CONTROL_BYTE BIT(0) +#define DW100_SWAP_CONTROL_SHORT BIT(1) +#define DW100_SWAP_CONTROL_WORD BIT(2) +#define DW100_SWAP_CONTROL_LONG BIT(3) +#define DW100_SWAP_CONTROL_Y(x) (((x) & GENMASK(3, 0)) << 0) +#define DW100_SWAP_CONTROL_UV(x) (((x) & GENMASK(3, 0)) << 4) +#define DW100_SWAP_CONTROL_SRC(x) (((x) & GENMASK(7, 0)) << 0) +#define DW100_SWAP_CONTROL_DST(x) (((x) & GENMASK(7, 0)) << 8) +#define DW100_SWAP_CONTROL_SRC2(x) (((x) & GENMASK(7, 0)) << 16) +#define DW100_SWAP_CONTROL_DST2(x) (((x) & GENMASK(7, 0)) << 24) +#define DW100_SWAP_CONTROL_SRC_MASK GENMASK(7, 0) +#define DW100_SWAP_CONTROL_DST_MASK GENMASK(15, 8) +#define DW100_SWAP_CONTROL_SRC2_MASK GENMASK(23, 16) +#define DW100_SWAP_CONTROL_DST2_MASK GENMASK(31, 24) +#define DW100_VERTICAL_SPLIT_LINE 0x5C +#define DW100_HORIZON_SPLIT_LINE 0x60 +#define DW100_SCALE_FACTOR 0x64 +#define DW100_ROI_START 0x68 +#define DW100_ROI_START_X(x) (((x) & GENMASK(12, 0)) << 0) +#define DW100_ROI_START_Y(y) (((y) & GENMASK(12, 0)) << 16) +#define DW100_BOUNDARY_PIXEL 0x6C +#define DW100_BOUNDARY_PIXEL_V(v) (((v) & GENMASK(7, 0)) << 0) +#define DW100_BOUNDARY_PIXEL_U(u) (((u) & GENMASK(7, 0)) << 8) +#define DW100_BOUNDARY_PIXEL_Y(y) (((y) & GENMASK(7, 0)) << 16) + +#define DW100_INTERRUPT_STATUS 0x70 +#define DW100_INTERRUPT_STATUS_INT_FRAME_DONE BIT(0) +#define DW100_INTERRUPT_STATUS_INT_ERR_TIME_OUT BIT(1) +#define DW100_INTERRUPT_STATUS_INT_ERR_AXI_RESP BIT(2) +#define DW100_INTERRUPT_STATUS_INT_ERR_X BIT(3) +#define DW100_INTERRUPT_STATUS_INT_ERR_MB_FETCH BIT(4) +#define DW100_INTERRUPT_STATUS_INT_ERR_FRAME2 BIT(5) +#define DW100_INTERRUPT_STATUS_INT_ERR_FRAME3 BIT(6) +#define DW100_INTERRUPT_STATUS_INT_ERR_FRAME_DONE BIT(7) +#define DW100_INTERRUPT_STATUS_INT_ERR_STATUS(x) (((x) >> 1) & 0x7F) +#define DW100_INTERRUPT_STATUS_INT_STATUS(x) ((x) & 0xFF) + +#define DW100_INTERRUPT_STATUS_INT_ENABLE_MASK GENMASK(15, 8) +#define DW100_INTERRUPT_STATUS_INT_ENABLE(x) (((x) & GENMASK(7, 0)) << 8) +#define DW100_INTERRUPT_STATUS_FRAME_BUSY BIT(16) +#define DW100_INTERRUPT_STATUS_INT_CLEAR(x) (((x) & GENMASK(7, 0)) << 24) +#define DW100_BUS_CTRL 0x74 +#define DW100_BUS_CTRL_AXI_MASTER_ENABLE BIT(31) +#define DW100_BUS_CTRL1 0x78 +#define DW100_BUS_TIME_OUT_CYCLE 0x7C +#define DW100_DST_IMG_Y_SIZE1 0x80 +#define DW100_DST_IMG_Y_SIZE(sz) (((sz) >> 4) & GENMASK(29, 0)) +#define DW100_DST_IMG_UV_SIZE(sz) (((sz) >> 4) & GENMASK(29, 0)) +#define DW100_DST_IMG_UV_SIZE1 0x84 +#define DW100_DST_IMG_Y_SIZE2 0x88 +#define DW100_DST_IMG_UV_SIZE2 0x8C + +#endif /* _DW100_REGS_H_ */