From patchwork Wed Dec 5 18:50:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 152925 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp9640808ljp; Wed, 5 Dec 2018 10:50:28 -0800 (PST) X-Google-Smtp-Source: AFSGD/Vutpp2/UhE+eZZEO3E3/KlOzMnGQaib97YMi6+spofiECDfNNVd5VNNgcfxVh2uTU1BbOW X-Received: by 2002:a63:f658:: with SMTP id u24mr21545773pgj.267.1544035828819; Wed, 05 Dec 2018 10:50:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544035828; cv=none; d=google.com; s=arc-20160816; b=FXz4MWQQ6SnZCdcMoPawLZjwDGq4gtiYj916/HAWrQS8sqIUbZn1RVhDKbEmvYTqq5 ko4Rfasf7Lf9gOqbvLXbVoTlpozbJ51TSAzy9xU+jjHZzufJZupcZdmZj9knqOg6b1IK j6aSY+CDCcncxPEnneIwFvRAbLnBaAwzPQB+sq3DFMRt6AOVDSZ0EQzeskKsVJjSPNmz Vsyv1f3ltbvr6IVsWL/nxQ1aDvsY0x80ITR5mqKvbTlcnozZ1P7MoQ4sRdyQBnbfkzEf SZCFC+sUa8nAVTN0GmHqA2O/SNJg1CCMcZW6Di9WfBZP27M3zaLg7eJAFwo3h1auSdUg rbWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:dkim-signature:delivered-to; bh=xbLi9p2kFaEJHi1hNTrRebyUNaio4+FKpETMe3xk9e4=; b=kUO+UGGm91c6LE7cW37S74CZ7rRF7zrZZ6kAnUgFwDs2EJPpXgm7YOnF8zH1AA4kJK iqof73Csq0grTP/pMIL7zxuz4eaos6tF8MaZlBoEQmuTF2C++CuEcHXtrtkwDN4PTmsy /leK6Xli5JZTo2DiJC8qkQ6FTKFVcxI5zJQfmzdBrg02r5V/GhkTHaXlrhPWJQm7Sr3W xWXoqWpcPXzLoY0K6YZEAKjni+j81G22mVV+JRWnQmHf3WLQWt3HOLHY4nqnnNkIwu7e sO09HT1hJ0eNuoPpVf3ZBnMc9B6a+WSbZLwmLMTEfx4meAK4DRM1riAwbwVCw7/rPolR MMHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=a1oFPVIn; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id x3si18589258pgj.493.2018.12.05.10.50.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=a1oFPVIn; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 115AC21199264; Wed, 5 Dec 2018 10:50:28 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 83FE4211982C9 for ; Wed, 5 Dec 2018 10:50:26 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id q18so20777021wrx.9 for ; Wed, 05 Dec 2018 10:50:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NCvZDJXswWfPyXzuoG9wrhqYajJJheQJ1vp945q5J8Q=; b=a1oFPVIn6IiafvQQ1damYFF9ro770Gn0cNay7xvcPVLrypJ344yKSBhXe2ZFCf38zz ivfOp/WgDtagLKsa40kbtArdgTEsm38XSPEPkctOmI63rkW/dkomHVVmVDB+RuryuLq1 vjB44+/M/0k53orqBNgKX9XCyueIm5CCRP9Ik= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NCvZDJXswWfPyXzuoG9wrhqYajJJheQJ1vp945q5J8Q=; b=gOntetg6Ppf0sbDWlNgVOctQymwiMU10NFhcmuky+ZcKm40ry8AR8AZpCJZcERmJei MnV2kqi3iyeIsWwTFWcVHPd9ubQ/uUSwVDkMgSZJGNDNhv+ZS5QivakdwLIc98jRVafc 7UM8A7LE/rNkQyFI3YudqMKAa+g4pARfz0622z1BT5bDTHs8FYwIrHtzO3A2+nGKbRww RzERAXO2XNvRSH2QNH6aESzMHzUozARRQbHwMi2lDhefvM6gidW3/j3kRd73lr5PVwoQ aAFNDMx8HcE9ADihXKKr475F5WiDIMGL4ovVLJ3oAyQYxQRssoAaADM0tzVXXgCeJXe9 sTdw== X-Gm-Message-State: AA+aEWa5Z9LpaZFZOI5xCIEPO5ueF/xpQEv9NIz32dNtisj9nORr7XRC IpHyMi230bNoberwQYUZRSGe25NU3eq5BA== X-Received: by 2002:adf:c612:: with SMTP id n18mr21928809wrg.174.1544035824640; Wed, 05 Dec 2018 10:50:24 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:816d:4a95:a2ca:814d]) by smtp.gmail.com with ESMTPSA id c8sm14825186wrx.42.2018.12.05.10.50.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:23 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Dec 2018 19:50:15 +0100 Message-Id: <20181205185020.21441-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181205185020.21441-1-ard.biesheuvel@linaro.org> References: <20181205185020.21441-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 1/6] Silicon/AMD/Styx: move SOC version macros to common header X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Instead of adding yet another redefinition in the next patch, move the silicon revision testing macros into a shared header file. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/AMD/Styx/Common/SocVersion.h | 19 +++++++++++++++++++ Silicon/AMD/Styx/AcpiTables/Iort.c | 6 +----- Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c | 7 ++----- Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 7 ++----- 4 files changed, 24 insertions(+), 15 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/AMD/Styx/Common/SocVersion.h b/Silicon/AMD/Styx/Common/SocVersion.h new file mode 100644 index 000000000000..fc270b7c3431 --- /dev/null +++ b/Silicon/AMD/Styx/Common/SocVersion.h @@ -0,0 +1,19 @@ +#/** @file +# SoC specific defines +# +# Copyright (c) 2018 Linaro, Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +#define STYX_SOC_VERSION_MASK 0xFFF +#define STYX_SOC_VERSION_A0 0x000 +#define STYX_SOC_VERSION_B0 0x010 +#define STYX_SOC_VERSION_B1 0x011 diff --git a/Silicon/AMD/Styx/AcpiTables/Iort.c b/Silicon/AMD/Styx/AcpiTables/Iort.c index 370e71e13610..9c232379eff5 100644 --- a/Silicon/AMD/Styx/AcpiTables/Iort.c +++ b/Silicon/AMD/Styx/AcpiTables/Iort.c @@ -14,6 +14,7 @@ #include #include +#include #define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) @@ -354,11 +355,6 @@ STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = { #pragma pack() -#define STYX_SOC_VERSION_MASK 0xFFF -#define STYX_SOC_VERSION_A0 0x000 -#define STYX_SOC_VERSION_B0 0x010 -#define STYX_SOC_VERSION_B1 0x011 - EFI_ACPI_DESCRIPTION_HEADER * IortHeader ( VOID diff --git a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c index ea49cae9890f..1d2bca3d57ba 100644 --- a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c +++ b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c @@ -22,6 +22,8 @@ #include +#include + STATIC VOID ResetSataController ( @@ -144,11 +146,6 @@ InitializeSataController ( AhciBaseAddr, SIZE_4KB); } -#define STYX_SOC_VERSION_MASK 0xFFF -#define STYX_SOC_VERSION_A0 0x000 -#define STYX_SOC_VERSION_B0 0x010 -#define STYX_SOC_VERSION_B1 0x011 - EFI_STATUS EFIAPI StyxSataPlatformDxeEntryPoint ( diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index 7e8f918b11b4..b9dfa2367ab2 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -28,6 +28,8 @@ #include +#include + #define PMU_INT_FLAG_SPI 0 #define PMU_INT_TYPE_HIGH_LEVEL 4 @@ -230,11 +232,6 @@ DisableSmmu ( } } -#define STYX_SOC_VERSION_MASK 0xFFF -#define STYX_SOC_VERSION_A0 0x000 -#define STYX_SOC_VERSION_B0 0x010 -#define STYX_SOC_VERSION_B1 0x011 - STATIC VOID SetSocIdStatus ( From patchwork Wed Dec 5 18:50:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 152926 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp9640858ljp; Wed, 5 Dec 2018 10:50:32 -0800 (PST) X-Google-Smtp-Source: AFSGD/U24WdgMpWBF2TPfWZOiYKa6+IvjAR/MswsNhRkamuxWsX5xv95M7MTXSthx2E8+vbLsTcR X-Received: by 2002:a65:6392:: with SMTP id h18mr21797965pgv.107.1544035831934; Wed, 05 Dec 2018 10:50:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544035831; cv=none; d=google.com; s=arc-20160816; b=XtdRBkCegOnOOc5DYTJwAkYCpYGXj3ssjrorerE1dISX66gmAT1iTTk+KkK2Cs5q/G ev65FFcjcDbvO9iyyJNE2QSln33F3CPJ0p7/Tub1U1brADzSJS7qDZnX/SvkSsqDonj7 cm7RhF3hVc9HCPq4S23/fjNEfqbaYQRo4iH7Bpkhfbi4f53h8H3hURXrGSQ2i5xM2AgK 8VFin+/B8F6CW1HQxp6XSfXOY2F2ligz3VwKa33bjFW+doYcIyTRwP6Yrk56gxdQB+kG H/ZehKV95zjJ23IrB77HbpL0IduzSXqqh8Tk2D+kXO8tpJUOpcEdFpmGriubz2JwlZfV Mqhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:dkim-signature:delivered-to; bh=2RxHbX+5RI2mC/tLwJefxgEngoAb3wDAP0+5+Zvguwo=; b=RhpGx0zHc9QAaBq287jBd/sGUE45qvPHaI8lYL2iNo9eOD0SoMwwqLhLVjn+d79JOb M1F45vNgA+pdmMHK3IaDSv/lO+wVt6ag8sbFUl0GMSMFGZzt6B35rThdhRtmIk7x8de3 6cLypJI0AYC6I/QXfUQbTI5tAkKvKPMjZtyMPNgz9IlwK1Tboh1696edmwHX7j72Gf1H 8PDqsEcNk5wJivbY6vhIF9e1ru6BSJT2sifT4UPHZrucGRiCg/Vow19Nlb6EhQmPjYFD zqtkFVPQnvy8Q2u8THfjzodBNFazhXpyeqTKZYRWhjDtf9XPv6gYXbppiGl1Qhh9Uc0j fGfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Oi4aXoHY; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id z61si20889200plb.49.2018.12.05.10.50.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Oi4aXoHY; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 404522119926A; Wed, 5 Dec 2018 10:50:30 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AE02421197B2F for ; Wed, 5 Dec 2018 10:50:28 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id 96so20825616wrb.2 for ; Wed, 05 Dec 2018 10:50:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OetyPm3iZnHAbXn6SSPHfSYSw5LK5X81QrpMxEJIJp4=; b=Oi4aXoHYgXczd0LNIIZdh+7Ft1mTu8cXtoO7tyPqQndOySSSL3AoBrSQASwaOfHXR1 qu5xE/+sTYrjm8rXadyeRLRVFJwtduDhjUMo9rgQk4xQYQjWmX8BOUp09exTw7fVBFAB FP1jOMjpR5EkIffCft4GzpUgK36Ky6UtjFvCs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OetyPm3iZnHAbXn6SSPHfSYSw5LK5X81QrpMxEJIJp4=; b=PKvGCydHHokYpD90bgV7x1RDsmq9MwhgzhLWL188rpkyQlMqTLMX8sGtBWLc1QY4XG gr7CAVmwLX3zBQJPLqPv00Q8PEi4ZjHEy+eMmae62FA0rsNdu4RBlJutJgRyKKxG2lBX zXEgUNmXv5zEcglD6qBz/h6qo8dBFBGoya2yZk6w4W4XOgJD/FT+LC17LRV0WWsbE61p Zubs4iTNC3583mUEcNZxhyawaewXfr/MeqPP+y/tKxZYIRGKESgXBnznPLyapCT3F7xB Sqi1eqVR0m7MwSIwa5xa7FToufACsalNhyYTAqll2Q204IZ8EatRKWtHQiQFTIOByckP ASuA== X-Gm-Message-State: AA+aEWbaretkZWzfmdjlQ8XHE4y52HY3S5CvhHDpFMGtMn48YMT5VbqD 9vCQHLCSDTL1ATWEecpxQl9kM6iqmZHS5w== X-Received: by 2002:adf:81b6:: with SMTP id 51mr24536311wra.240.1544035826449; Wed, 05 Dec 2018 10:50:26 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:816d:4a95:a2ca:814d]) by smtp.gmail.com with ESMTPSA id c8sm14825186wrx.42.2018.12.05.10.50.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:25 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Dec 2018 19:50:16 +0100 Message-Id: <20181205185020.21441-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181205185020.21441-1-ard.biesheuvel@linaro.org> References: <20181205185020.21441-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 2/6] Silicon/AMD/Styx: move B1 revision peripherals to separate SSDT table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Instead of poking DSDT _STA method bytecode to make it return something else depending on whether we are running on B1 silicon, move the B1 only peripherals to a separate SSDT and only install it when running on compatible hardware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 1 + Platform/LeMaker/CelloBoard/CelloBoard.fdf | 1 + Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf | 1 + Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 7 ++ Silicon/AMD/Styx/AcpiTables/Dsdt.c | 39 --------- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 62 ++++++++++++-- Silicon/AMD/Styx/AcpiTables/Dsdt.asl | 67 --------------- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtB1.asl | 86 ++++++++++++++++++++ 8 files changed, 150 insertions(+), 114 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf index bf4e6f3283eb..cc082031621c 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf @@ -454,6 +454,7 @@ CAPSULE_HEADER_INIT_VERSION = 0x1 DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional + RAW ASL Optional |.aml } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.fdf b/Platform/LeMaker/CelloBoard/CelloBoard.fdf index 0f412ba90e54..45fc850c36cb 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.fdf +++ b/Platform/LeMaker/CelloBoard/CelloBoard.fdf @@ -365,6 +365,7 @@ READ_LOCK_STATUS = TRUE DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional + RAW ASL Optional |.aml } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf index 2800d5d1f536..fec3acdd767c 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf @@ -367,6 +367,7 @@ READ_LOCK_STATUS = TRUE DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional + RAW ASL Optional |.aml } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 3c484c43ac41..245724aa8ea2 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -28,6 +28,7 @@ [Sources] AcpiPlatform.c + SsdtB1.asl [Packages] ArmPkg/ArmPkg.dec @@ -39,12 +40,18 @@ [LibraryClasses] AmdStyxAcpiLib DebugLib + DxeServicesLib + MemoryAllocationLib PcdLib UefiBootServicesTableLib UefiDriverEntryPoint [Pcd] gAmdStyxTokenSpaceGuid.PcdEnableSmmus + gAmdStyxTokenSpaceGuid.PcdSocCpuId + +[FixedPcd] + gAmdStyxTokenSpaceGuid.PcdSata1PortCount [Protocols] gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.c b/Silicon/AMD/Styx/AcpiTables/Dsdt.c index 360a446f7631..dd432ce03ad1 100644 --- a/Silicon/AMD/Styx/AcpiTables/Dsdt.c +++ b/Silicon/AMD/Styx/AcpiTables/Dsdt.c @@ -130,41 +130,12 @@ OverrideMacAddr ( } } -VOID -OverrideStatus ( - IN UINT8 *DSD_Data, - IN BOOLEAN Enable - ) -{ - if (Enable) { - // AML encoding: ReturnOp + BytePrefix - if (DSD_Data[1] == 0xA4 && DSD_Data[2] == 0x0A) { - DSD_Data[3] = 0x0F; - } - } else { - // AML encoding: ReturnOp - if (DSD_Data[1] == 0xA4) { - // AML encoding: BytePrefix? - if (DSD_Data[2] == 0x0A) { - DSD_Data[3] = 0x00; - } else { - DSD_Data[2] = 0x00; - } - } - } -} - EFI_ACPI_DESCRIPTION_HEADER * DsdtHeader ( VOID ) { AML_OFFSET_TABLE_ENTRY *Table; - BOOLEAN EnableOnB1; - UINT32 CpuId = PcdGet32 (PcdSocCpuId); - - // Enable features on Styx-B1 or later - EnableOnB1 = (CpuId & 0xFF0) && (CpuId & 0x00F); Table = &DSDT_SEATTLE__OffsetTable[0]; while (Table->Pathname) { @@ -174,16 +145,6 @@ DsdtHeader ( else if (AsciiStrCmp(Table->Pathname, "_SB_.ETH1._DSD") == 0) { OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacB)); } - else if (AsciiStrCmp(Table->Pathname, "_SB_.AHC1._STA") == 0) { - OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], - EnableOnB1 && FixedPcdGet8(PcdSata1PortCount) > 0); - } - else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO2._STA") == 0) { - OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1); - } - else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO3._STA") == 0) { - OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1); - } ++Table; } diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 901eac105932..0d0033b4d6c6 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -24,13 +24,57 @@ #include #include +#include +#include #include #include +#include + +#include + #define MAX_ACPI_TABLES 16 EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES]; +STATIC EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol; + +STATIC +VOID +InstallSystemDescriptionTables ( + VOID + ) +{ + EFI_ACPI_DESCRIPTION_HEADER *Table; + EFI_STATUS Status; + UINT32 CpuId; + UINTN Index; + UINTN TableSize; + UINTN TableHandle; + + Status = EFI_SUCCESS; + for (Index = 0; !EFI_ERROR (Status); Index++) { + Status = GetSectionFromFv (&gEfiCallerIdGuid, EFI_SECTION_RAW, Index, + (VOID **) &Table, &TableSize); + if (EFI_ERROR (Status)) { + break; + } + + switch (Table->OemTableId) { + case SIGNATURE_64 ('S', 't', 'y', 'x', 'B', '1', ' ', ' '): + CpuId = PcdGet32 (PcdSocCpuId); + if ((CpuId & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) { + continue; + } + break; + } + + Status = mAcpiTableProtocol->InstallAcpiTable (mAcpiTableProtocol, Table, + TableSize, &TableHandle); + ASSERT_EFI_ERROR (Status); + FreePool (Table); + } +} /** Entrypoint of Acpi Platform driver. @@ -51,7 +95,6 @@ AcpiPlatformEntryPoint ( ) { EFI_STATUS Status; - EFI_ACPI_TABLE_PROTOCOL *AcpiTable; UINTN TableHandle; UINTN TableIndex; @@ -77,7 +120,8 @@ AcpiPlatformEntryPoint ( // // Find the AcpiTable protocol // - Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable); + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, + (VOID**)&mAcpiTableProtocol); if (EFI_ERROR (Status)) { DEBUG((EFI_D_ERROR, "Failed to locate AcpiTable protocol. Status = %r\n", Status)); ASSERT_EFI_ERROR(Status); @@ -96,12 +140,12 @@ AcpiPlatformEntryPoint ( AcpiTableList[TableIndex]->Revision, AcpiTableList[TableIndex]->Length)); - Status = AcpiTable->InstallAcpiTable ( - AcpiTable, - AcpiTableList[TableIndex], - (AcpiTableList[TableIndex])->Length, - &TableHandle - ); + Status = mAcpiTableProtocol->InstallAcpiTable ( + mAcpiTableProtocol, + AcpiTableList[TableIndex], + (AcpiTableList[TableIndex])->Length, + &TableHandle + ); if (EFI_ERROR (Status)) { DEBUG((DEBUG_ERROR,"Error adding ACPI Table. Status = %r\n", Status)); ASSERT_EFI_ERROR(Status); @@ -110,6 +154,8 @@ AcpiPlatformEntryPoint ( ASSERT( TableIndex < MAX_ACPI_TABLES ); } + InstallSystemDescriptionTables (); + return EFI_SUCCESS; } diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.asl b/Silicon/AMD/Styx/AcpiTables/Dsdt.asl index 4741bb487cc7..e9991644e6a0 100644 --- a/Silicon/AMD/Styx/AcpiTables/Dsdt.asl +++ b/Silicon/AMD/Styx/AcpiTables/Dsdt.asl @@ -105,35 +105,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) }) } - Device (AHC1) - { - Name (_HID, "AMDI0600") // _HID: Hardware ID - Name (_UID, 0x01) // _UID: Unique ID - Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute - Name (_CLS, Package (0x03) // _CLS: Class Code - { - 0x01, - 0x06, - 0x01 - }) - Method (_STA) - { - Return (0x0F) - } - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0xE0D00000, // Address Base (MMIO) - 0x00010000, // Address Length - ) - Memory32Fixed (ReadWrite, - 0xE000007C, // Address Base (SGPIO) - 0x00000001, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, } - }) - } - #if DO_XGBE Device (ETH0) { @@ -344,44 +315,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) }) } - Device (GIO2) - { - Name (_HID, "AMDI0400") // _HID: Hardware ID - Name (_CID, "ARMH0061") // _CID: Compatible ID - Name (_UID, 0x02) // _UID: Unique ID - Method (_STA) - { - Return (0x0F) - } - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0xE0020000, // Address Base - 0x00001000, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, } - }) - } - - Device (GIO3) - { - Name (_HID, "AMDI0400") // _HID: Hardware ID - Name (_CID, "ARMH0061") // _CID: Compatible ID - Name (_UID, 0x03) // _UID: Unique ID - Method (_STA) - { - Return (0x0F) - } - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0xE0030000, // Address Base - 0x00001000, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, } - }) - } - Device (I2C0) { Name (_HID, "AMDI0510") // _HID: Hardware ID diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtB1.asl b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtB1.asl new file mode 100644 index 000000000000..78aa220a0457 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtB1.asl @@ -0,0 +1,86 @@ +/** @file + + SSDT for peripherals that are only enabled on B1 silicon + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+ Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ("SsdtB1.aml", "SSDT", 2, "AMDINC", "StyxB1 ", 3) +{ + Scope (_SB) + { + Device (AHC1) + { + Name (_HID, "AMDI0600") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + Method (_STA) + { + If (LEqual (FixedPcdGet8 (PcdSata1PortCount), 0)) { + Return (0x0) + } + Return (0xF) + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xE0D00000, // Address Base (MMIO) + 0x00010000, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xE000007C, // Address Base (SGPIO) + 0x00000001, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, } + }) + } + + Device (GIO2) + { + Name (_HID, "AMDI0400") // _HID: Hardware ID + Name (_CID, "ARMH0061") // _CID: Compatible ID + Name (_UID, 0x02) // _UID: Unique ID + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xE0020000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, } + }) + } + + Device (GIO3) + { + Name (_HID, "AMDI0400") // _HID: Hardware ID + Name (_CID, "ARMH0061") // _CID: Compatible ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xE0030000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, } + }) + } + } +} From patchwork Wed Dec 5 18:50:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 152927 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp9640916ljp; Wed, 5 Dec 2018 10:50:35 -0800 (PST) X-Google-Smtp-Source: AFSGD/UlgEDoYNLqoipHKQZJfkaWxGjhfbQwUjxwJu59TegxzPJXuieJXHhkviLnAsrrJsKH0buq X-Received: by 2002:a62:1e45:: with SMTP id e66mr25238268pfe.152.1544035834990; Wed, 05 Dec 2018 10:50:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544035834; cv=none; d=google.com; s=arc-20160816; b=YXiKq/l09amOMhOkr11XHTHaRIOS/XhGIZXlR6kvPldANBAyvgt52XC5tq/CgMagUE p1+kxvAt8/7JupyhZdbg7FX6Yc9caNsjr/8nWJdSmz6ifq+WBiEUgtL5+wJXsgi2tvFD 2hiKAqVwBVTw1hE4o6ItLDBPvXY0I6e2s8rchUDB60NhGHzAIsLUrEqeAaQyz1j1cm7g FY9ppib7cuWvhWU/kmCD3d0Plx2N6Tgiwxv6kQQMCwvtJFZjlLIZeW+XNP+rQdcnkAsz nezi3/NNXUpRxFnI3TBkf7UPWSeeL4u2z9KC2ffpXnD4WaJvju9x8A+TD2zmPTpf+4NV y2YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:dkim-signature:delivered-to; bh=GBF8DEWiMQiuxNK5/n19FtE7PxB51V/e4raMN4cYASQ=; b=L4qEJ4QlPGJJ+CbkKq007igl9qe+IrT58s+ZCkGdH68GNY/MjFgeUZ1E+najz3n/EG fzsnvu6gla1/SwdHb6+K4BTDskHh0w2WHCjfELpLWHxiVjmuqMevu3lFaQ0LFe6RFlyP vArjC4XrFmgH7RDRMbaiwmHUtNO+EDb5oKR5iIeJrTUF2hf/mlHpyvjmhrElUEpnnm4Z cBbUQ7EqblFW9BEpZsdHGNXTrellEZfWVC7SLse2r62Vbe6QtoJB9j+Vpo3IEr+Vd0w3 koBiGD7ghKdJ7pvEO4g1USAq5VvGZ7Si2Pyu23VT0Cbo5R692DWSPzyWnNxJuM60Ge/w mMTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=encOteyI; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id t75si21275490pfa.170.2018.12.05.10.50.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=encOteyI; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6E5D82119926E; Wed, 5 Dec 2018 10:50:32 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BD3EE21197B2F for ; Wed, 5 Dec 2018 10:50:30 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id b14so7207388wru.12 for ; Wed, 05 Dec 2018 10:50:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GN8TdIF0mE4qWYpVMpAW6Cd35d7EocIwYm6/k24703s=; b=encOteyIVB3cEqmTV22p1lzRGTF5ynXEzWPsJoxCvSZBISCiZi7DeyO2DjV/7YsSwS GOuxnpfPfmOTct7Ujbau/XuA97i+yqa86UdFmFzyv+KCqfQ9c4rucybNv4/ZL0A6P0f+ l48pIZNUQlyjnUyU6jsUw+hT9wHHSG+4F7+Ck= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GN8TdIF0mE4qWYpVMpAW6Cd35d7EocIwYm6/k24703s=; b=epGkxPkyUzKr92NqqgM1ppDjoZatDKOxEABllrROMKKIEjc5jtjLV0yVG3W1wwlkfa wQhDF/zOFsq64QyJZqQHRorMWZsnAJ58owjQoNF4uNrE9WIYrUTv6ws2vfOcs+dLr091 P0Bo9H0vAWSYEpDYyFAZL0HD3tYZHa9L2Er3jdkKe+uNwJ61l+6KL2/Bv2umoR5JQGtF dJZvCLEeBihp7Kr6EnQa4FG1Ipy9UyowfoyAX4MloWUu7KnuA6bAkE5oy8sbwjEfd1gk 6YgGO3ydxqsf3/oYv7QWYwbBWiUiJJDwcWEKVQ03PcGKAfHJ+KQ/ijClLjF1Y+xz9+B3 j5AA== X-Gm-Message-State: AA+aEWaGgmPTsWmRKcBl86vZYefKXEs2Q8bZ/FgEHnibbDML5/OGYO5G Np/TeKwJ40L615gIpvbOTkbQzzocUs6+RQ== X-Received: by 2002:a5d:49cd:: with SMTP id t13mr8465704wrs.144.1544035827791; Wed, 05 Dec 2018 10:50:27 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:816d:4a95:a2ca:814d]) by smtp.gmail.com with ESMTPSA id c8sm14825186wrx.42.2018.12.05.10.50.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:26 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Dec 2018 19:50:17 +0100 Message-Id: <20181205185020.21441-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181205185020.21441-1-ard.biesheuvel@linaro.org> References: <20181205185020.21441-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 3/6] Silicon/AMD/Styx: move XGBE declarations to separate SSDT table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Move the XGBE out of the DSDT, and along with it the logic that patches the correct MAC address into the device nodes. However, this time we patch the SSDT binary directly rather than relying on intermediate output of an outdated version of the iasl compiler. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 2 - Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 5 + Silicon/AMD/Styx/AcpiTables/Dsdt.c | 127 ------------------ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 74 +++++++++++ Silicon/AMD/Styx/AcpiTables/Dsdt.asl | 113 ---------------- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtXgbe.asl | 135 ++++++++++++++++++++ 6 files changed, 214 insertions(+), 242 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf index 4ae64ac22665..692717950f40 100644 --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf @@ -58,8 +58,6 @@ [Pcd] gAmdStyxTokenSpaceGuid.PcdSocCoreCount gAmdStyxTokenSpaceGuid.PcdSocCpuId - gAmdStyxTokenSpaceGuid.PcdEthMacA - gAmdStyxTokenSpaceGuid.PcdEthMacB [FixedPcd] gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 245724aa8ea2..cc2320e4262d 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -29,6 +29,7 @@ [Sources] AcpiPlatform.c SsdtB1.asl + SsdtXgbe.asl [Packages] ArmPkg/ArmPkg.dec @@ -39,6 +40,8 @@ [LibraryClasses] AmdStyxAcpiLib + BaseLib + BaseMemoryLib DebugLib DxeServicesLib MemoryAllocationLib @@ -47,6 +50,8 @@ UefiDriverEntryPoint [Pcd] + gAmdStyxTokenSpaceGuid.PcdEthMacA + gAmdStyxTokenSpaceGuid.PcdEthMacB gAmdStyxTokenSpaceGuid.PcdEnableSmmus gAmdStyxTokenSpaceGuid.PcdSocCpuId diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.c b/Silicon/AMD/Styx/AcpiTables/Dsdt.c index dd432ce03ad1..25e654acabbc 100644 --- a/Silicon/AMD/Styx/AcpiTables/Dsdt.c +++ b/Silicon/AMD/Styx/AcpiTables/Dsdt.c @@ -15,139 +15,12 @@ **/ #include -#include -#include -#include - #include -#include - - -UINTN -ShiftLeftByteToUlong ( - IN UINT8 Byte, - IN UINTN Shift - ) -{ - UINTN Data; - - Data = (UINTN)Byte; - Data <<= Shift; - return Data; -} - -UINTN -AmlGetPkgLength ( - IN UINT8 *Buffer, - OUT UINTN *PkgLength - ) -{ - UINTN Bytes, Length; - - Bytes = (UINTN)((Buffer[0] >> 6) & 0x3) + 1; - switch (Bytes) { - case 1: - Length = (UINTN)Buffer[0]; - break; - - case 2: - Length = ShiftLeftByteToUlong(Buffer[1], 4) + - (UINTN)(Buffer[0] & 0x0F); - break; - - case 3: - Length = ShiftLeftByteToUlong(Buffer[2], 12) + - ShiftLeftByteToUlong(Buffer[1], 4) + - (UINTN)(Buffer[0] & 0x0F); - break; - - default: /* 4 bytes */ - Length = ShiftLeftByteToUlong(Buffer[3], 20) + - ShiftLeftByteToUlong(Buffer[2], 12) + - ShiftLeftByteToUlong(Buffer[1], 4) + - (UINTN)(Buffer[0] & 0x0F); - break; - } - - *PkgLength = Length; - return Bytes; -} - -UINT8 * -AmlSearchStringPackage ( - IN UINT8 *Buffer, - IN UINTN Length, - IN CHAR8 *String - ) -{ - UINTN StrLength; - - StrLength = AsciiStrLen (String) + 1; - if (Length > StrLength ) { - Length -= StrLength; - while (AsciiStrCmp((CHAR8 *)Buffer, String) != 0 && Length) { - --Length; - ++Buffer; - } - if (Length) { - return &Buffer[StrLength]; - } - } - return NULL; -} - -VOID -OverrideMacAddr ( - IN UINT8 *DSD_Data, - IN UINT64 MacAddr - ) -{ - UINT8 *MacAddrPkg; - UINTN Bytes, Length, Index = 0; - - // AML encoding: PackageOp - if (DSD_Data[0] == 0x12) { - // AML encoding: PkgLength - Bytes = AmlGetPkgLength (&DSD_Data[1], &Length); - - // Search for "mac-address" property - MacAddrPkg = AmlSearchStringPackage (&DSD_Data[Bytes + 1], - Length - Bytes, - "mac-address"); - if (MacAddrPkg && - MacAddrPkg[0] == 0x12 && // PackageOp - MacAddrPkg[1] == 0x0E && // PkgLength - MacAddrPkg[2] == 0x06) { // NumElements (element must have a BytePrefix) - - MacAddrPkg += 3; - do { - MacAddrPkg[0] = 0x0A; // BytePrefix - MacAddrPkg[1] = (UINT8)(MacAddr & 0xFF); - MacAddrPkg += 2; - MacAddr >>= 8; - } while (++Index < 6); - } - } -} EFI_ACPI_DESCRIPTION_HEADER * DsdtHeader ( VOID ) { - AML_OFFSET_TABLE_ENTRY *Table; - - Table = &DSDT_SEATTLE__OffsetTable[0]; - while (Table->Pathname) { - if (AsciiStrCmp(Table->Pathname, "_SB_.ETH0._DSD") == 0) { - OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacA)); - } - else if (AsciiStrCmp(Table->Pathname, "_SB_.ETH1._DSD") == 0) { - OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacB)); - } - - ++Table; - } - return (EFI_ACPI_DESCRIPTION_HEADER *) &AmlCode[0]; } diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 0d0033b4d6c6..460fb4c480c3 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -39,6 +40,57 @@ EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES]; STATIC EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol; +#if DO_XGBE + +STATIC CONST UINT8 mDefaultMacPackageA[] = { + 0x12, 0xe, 0x6, 0xa, 0x2, 0xa, 0xa1, 0xa, 0xa2, 0xa, 0xa3, 0xa, 0xa4, 0xa, 0xa5 +}; + +STATIC CONST UINT8 mDefaultMacPackageB[] = { + 0x12, 0xe, 0x6, 0xa, 0x2, 0xa, 0xb1, 0xa, 0xb2, 0xa, 0xb3, 0xa, 0xb4, 0xa, 0xb5 +}; + +#define PACKAGE_MAC_OFFSET 4 +#define PACKAGE_MAC_INCR 2 + +STATIC +VOID +SetPackageAddress ( + UINT8 *Package, + UINT64 MacAddress, + UINTN Size + ) +{ + UINTN Index; + + for (Index = PACKAGE_MAC_OFFSET; Index < Size; Index += PACKAGE_MAC_INCR) { + Package[Index] = (UINT8)MacAddress; + MacAddress >>= 8; + } +} + +STATIC +VOID +PatchAmlPackage ( + CONST UINT8 *Pattern, + CONST UINT8 *Replacement, + UINTN PatternLength, + UINT8 *SsdtTable, + UINTN TableSize + ) +{ + UINTN Offset; + + for (Offset = 0; Offset < (TableSize - PatternLength); Offset++) { + if (CompareMem (SsdtTable + Offset, Pattern, PatternLength) == 0) { + CopyMem (SsdtTable + Offset, Replacement, PatternLength); + break; + } + } +} + +#endif + STATIC VOID InstallSystemDescriptionTables ( @@ -51,6 +103,9 @@ InstallSystemDescriptionTables ( UINTN Index; UINTN TableSize; UINTN TableHandle; +#if DO_XGBE + UINT8 MacPackage[sizeof(mDefaultMacPackageA)]; +#endif Status = EFI_SUCCESS; for (Index = 0; !EFI_ERROR (Status); Index++) { @@ -67,6 +122,25 @@ InstallSystemDescriptionTables ( continue; } break; + + case SIGNATURE_64 ('S', 't', 'y', 'x', 'X', 'g', 'b', 'e'): +#if DO_XGBE + // + // Patch the SSDT binary with the correct MAC addresses + // + CopyMem (MacPackage, mDefaultMacPackageA, sizeof (MacPackage)); + + SetPackageAddress (MacPackage, PcdGet64 (PcdEthMacA), sizeof (MacPackage)); + PatchAmlPackage (mDefaultMacPackageA, MacPackage, sizeof (MacPackage), + (UINT8 *)Table, TableSize); + + SetPackageAddress (MacPackage, PcdGet64 (PcdEthMacB), sizeof (MacPackage)); + PatchAmlPackage (mDefaultMacPackageB, MacPackage, sizeof (MacPackage), + (UINT8 *)Table, TableSize); + + break; +#endif + continue; } Status = mAcpiTableProtocol->InstallAcpiTable (mAcpiTableProtocol, Table, diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.asl b/Silicon/AMD/Styx/AcpiTables/Dsdt.asl index e9991644e6a0..c1417e7e1cd7 100644 --- a/Silicon/AMD/Styx/AcpiTables/Dsdt.asl +++ b/Silicon/AMD/Styx/AcpiTables/Dsdt.asl @@ -105,119 +105,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) }) } -#if DO_XGBE - Device (ETH0) - { - Name (_HID, "AMDI8001") // _HID: Hardware ID - Name (_UID, 0x00) // _UID: Unique ID - Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - - { - Memory32Fixed (ReadWrite, - 0xE0700000, // Address Base (XGMAC) - 0x00010000, // Address Length - ) - Memory32Fixed (ReadWrite, - 0xE0780000, // Address Base (XPCS) - 0x00080000, // Address Length - ) - Memory32Fixed (ReadWrite, - 0xE1240800, // Address Base (SERDES_RxTx) - 0x00000400, // Address Length - ) - Memory32Fixed (ReadWrite, - 0xE1250000, // Address Base (SERDES_IR_1) - 0x00000060, // Address Length - ) - Memory32Fixed (ReadWrite, - 0xE12500F8, // Address Base (SERDES_IR_2) - 0x00000004, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000165, } // XGMAC - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017A, } // DMA0 - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017B, } // DMA1 - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017C, } // DMA2 - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017D, } // DMA3 - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000163, } // XPCS - }) - Name (_DSD, Package (0x02) // _DSD: Device-Specific Data - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package (0x02) {"mac-address", Package (0x06) {0x02, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}}, - Package (0x02) {"phy-mode", "xgmii"}, - Package (0x02) {"amd,speed-set", 0x00}, - Package (0x02) {"amd,dma-freq", 0x0EE6B280}, - Package (0x02) {"amd,ptp-freq", 0x0EE6B280}, - Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}}, - Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}}, - Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}}, - Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}}, - Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}}, - Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}}, - Package (0x02) {"amd,per-channel-interrupt", 0x01} - } - }) - } - - Device (ETH1) - { - Name (_HID, "AMDI8001") // _HID: Hardware ID - Name (_UID, 0x01) // _UID: Unique ID - Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0xE0900000, // Address Base (XGMAC) - 0x00010000, // Address Length - ) - Memory32Fixed (ReadWrite, - 0xE0980000, // Address Base (XPCS) - 0x00080000, // Address Length - ) - Memory32Fixed (ReadWrite, - 0xE1240C00, // Address Base (SERDES_RxTx) - 0x00000400, // Address Length - ) - Memory32Fixed (ReadWrite, - 0xE1250080, // Address Base (SERDES_IR_1) - 0x00000060, // Address Length - ) - Memory32Fixed (ReadWrite, - 0xE12500FC, // Address Base (SERDES_IR_2) - 0x00000004, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000164, } // XGMAC - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000175, } // DMA0 - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000176, } // DMA1 - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000177, } // DMA2 - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000178, } // DMA3 - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000162, } // XPCS - }) - Name (_DSD, Package (0x02) // _DSD: Device-Specific Data - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package (0x02) {"mac-address", Package (0x06) {0x02, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5}}, - Package (0x02) {"phy-mode", "xgmii"}, - Package (0x02) {"amd,speed-set", 0x00}, - Package (0x02) {"amd,dma-freq", 0x0EE6B280}, - Package (0x02) {"amd,ptp-freq", 0x0EE6B280}, - Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}}, - Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}}, - Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}}, - Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}}, - Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}}, - Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}}, - Package (0x02) {"amd,per-channel-interrupt", 0x01} - } - }) - } -#endif // DO_XGBE - Device (SPI0) { Name (_HID, "AMDI0500") // _HID: Hardware ID diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtXgbe.asl b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtXgbe.asl new file mode 100644 index 000000000000..503c47365f15 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtXgbe.asl @@ -0,0 +1,135 @@ +/** @file + + SSDT for 10GbE network controllers + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+ Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ("SsdtXgbe.aml", "SSDT", 2, "AMDINC", "StyxXgbe", 3) +{ + Scope (_SB) + { + Device (ETH0) + { + Name (_HID, "AMDI8001") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + + { + Memory32Fixed (ReadWrite, + 0xE0700000, // Address Base (XGMAC) + 0x00010000, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xE0780000, // Address Base (XPCS) + 0x00080000, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xE1240800, // Address Base (SERDES_RxTx) + 0x00000400, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xE1250000, // Address Base (SERDES_IR_1) + 0x00000060, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xE12500F8, // Address Base (SERDES_IR_2) + 0x00000004, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000165, } // XGMAC + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017A, } // DMA0 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017B, } // DMA1 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017C, } // DMA2 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017D, } // DMA3 + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000163, } // XPCS + }) + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02) {"mac-address", Package (0x06) {0x02, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}}, + Package (0x02) {"phy-mode", "xgmii"}, + Package (0x02) {"amd,speed-set", 0x00}, + Package (0x02) {"amd,dma-freq", 0x0EE6B280}, + Package (0x02) {"amd,ptp-freq", 0x0EE6B280}, + Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}}, + Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}}, + Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}}, + Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}}, + Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}}, + Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}}, + Package (0x02) {"amd,per-channel-interrupt", 0x01} + } + }) + } + + Device (ETH1) + { + Name (_HID, "AMDI8001") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xE0900000, // Address Base (XGMAC) + 0x00010000, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xE0980000, // Address Base (XPCS) + 0x00080000, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xE1240C00, // Address Base (SERDES_RxTx) + 0x00000400, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xE1250080, // Address Base (SERDES_IR_1) + 0x00000060, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xE12500FC, // Address Base (SERDES_IR_2) + 0x00000004, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000164, } // XGMAC + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000175, } // DMA0 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000176, } // DMA1 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000177, } // DMA2 + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000178, } // DMA3 + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000162, } // XPCS + }) + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (0x02) {"mac-address", Package (0x06) {0x02, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5}}, + Package (0x02) {"phy-mode", "xgmii"}, + Package (0x02) {"amd,speed-set", 0x00}, + Package (0x02) {"amd,dma-freq", 0x0EE6B280}, + Package (0x02) {"amd,ptp-freq", 0x0EE6B280}, + Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}}, + Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}}, + Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}}, + Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}}, + Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}}, + Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}}, + Package (0x02) {"amd,per-channel-interrupt", 0x01} + } + }) + } + } +} + From patchwork Wed Dec 5 18:50:18 2018 Content-Type: text/plain; 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[198.145.21.10]) by mx.google.com with ESMTPS id b36si17280741pla.354.2018.12.05.10.50.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fmjnqFZO; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9CE802194D3AE; Wed, 5 Dec 2018 10:50:32 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BF67E2194D3AE for ; Wed, 5 Dec 2018 10:50:30 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id v13so20779041wrw.5 for ; Wed, 05 Dec 2018 10:50:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3zApOp0YMAYweeZ/GFoj29Zrs04+W65qo3DjEdQNEcc=; b=fmjnqFZOW1yWymMQb1/UtWtv1vM0gvNoGm/vFaVYlefZQJvWp8RgOj0vaXNOSmPwmB q4joGDVhC5FCN0QkFqun5AE3gbSG8ZfHzD3+Pp1txUMxBXZV50BgD9MboGOBL2q6VcGU 2AJZqiQIIxEz3siYiwelrpUA6vAU5ZysITtAo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3zApOp0YMAYweeZ/GFoj29Zrs04+W65qo3DjEdQNEcc=; b=OBCazBGo5XN5PYnDcSSNWhLmSsvaoop+SFmMw7i+n5Sdi4sUAkOaspRtp4MKOzicdL m4MPAPsx5VUi2KHY6fOYtmCxXHw2Iya/XarzpH1bI2xZomsHhHW29TMrMiJOyO7USec5 o1qKY8upvN6gt1+qwZx036A1rEAdQ3YDAeVDkCKm9Bs5otGHMfCP7tu0eRC6d+nSkun2 nRxqH9Ztqt3hwFnQwBgf/Yfx6zWF6uXwdFnQaC+R+FvNaHBOr1OzUvLwPEWpFXEnteA8 1QJG6ns+6sPQqTLzi445+kVFoBXFoD5raS+Lk3PkJ43hFvNV70e/D1w/oVXPiwZX602c XTBg== X-Gm-Message-State: AA+aEWYpfSOM70Ix0rTIZwIKBIE+y/ZCY79DLctKfQ5L32qN+O5tNc8Q ZMxYUh6b3N0d3hxsaZXPnSPJemYOY/4vEg== X-Received: by 2002:a5d:454f:: with SMTP id p15mr24233742wrr.39.1544035828983; Wed, 05 Dec 2018 10:50:28 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:816d:4a95:a2ca:814d]) by smtp.gmail.com with ESMTPSA id c8sm14825186wrx.42.2018.12.05.10.50.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:28 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Dec 2018 19:50:18 +0100 Message-Id: <20181205185020.21441-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181205185020.21441-1-ard.biesheuvel@linaro.org> References: <20181205185020.21441-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 4/6] Silicon/AMD/Styx: emit DSDT as aml directly X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Instead of emitting the DSDT by incorporating the intermediate output of [some version of] the iasl compiler, move the DSDT source file to the ACPI platform driver, which will install it directly. This permits us to drop a lot of cruft related to handling of this intermediate output. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 3 -- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 4 --- Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 3 -- Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 1 - Platform/LeMaker/CelloBoard/CelloBoard.fdf | 1 - Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf | 1 - Silicon/AMD/Styx/AcpiTables/AcpiAml.inf | 29 -------------------- Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 1 - Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 1 + Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h | 1 - Silicon/AMD/Styx/AcpiTables/Dsdt.c | 26 ------------------ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 1 - Silicon/AMD/Styx/{AcpiTables => Drivers/AcpiPlatformDxe}/Dsdt.asl | 0 13 files changed, 1 insertion(+), 71 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index b062f671f57f..7c66af6128c5 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -272,8 +272,6 @@ DEFINE DO_CAPSULE = FALSE GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 - GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT - [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 @@ -683,7 +681,6 @@ DEFINE DO_CAPSULE = FALSE NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf } - Silicon/AMD/Styx/AcpiTables/AcpiAml.inf Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index 103c2fb74114..7c22bbbfa90f 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -264,8 +264,6 @@ DEFINE DO_FLASHER = FALSE GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 - GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT - [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 @@ -617,8 +615,6 @@ DEFINE DO_FLASHER = FALSE NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf } - - Silicon/AMD/Styx/AcpiTables/AcpiAml.inf Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf # diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 1927ef3ebafb..793bd5359a23 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -262,8 +262,6 @@ DEFINE DO_FLASHER = FALSE GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 - GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT - [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 @@ -612,7 +610,6 @@ DEFINE DO_FLASHER = FALSE NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf } - Silicon/AMD/Styx/AcpiTables/AcpiAml.inf Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf # diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf index cc082031621c..96df83e0da5a 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf @@ -219,7 +219,6 @@ READ_LOCK_STATUS = TRUE # ACPI Support # INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - INF RuleOverride=ACPITABLE Silicon/AMD/Styx/AcpiTables/AcpiAml.inf INF Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.fdf b/Platform/LeMaker/CelloBoard/CelloBoard.fdf index 45fc850c36cb..fc977f14b5a1 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.fdf +++ b/Platform/LeMaker/CelloBoard/CelloBoard.fdf @@ -204,7 +204,6 @@ READ_LOCK_STATUS = TRUE # ACPI Support # INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - INF RuleOverride=ACPITABLE Silicon/AMD/Styx/AcpiTables/AcpiAml.inf INF Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf # diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf index fec3acdd767c..8fc9a979aebc 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf @@ -217,7 +217,6 @@ READ_LOCK_STATUS = TRUE # ACPI Support # INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - INF RuleOverride=ACPITABLE Silicon/AMD/Styx/AcpiTables/AcpiAml.inf INF Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf # diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiAml.inf b/Silicon/AMD/Styx/AcpiTables/AcpiAml.inf deleted file mode 100644 index 08a7aabe8256..000000000000 --- a/Silicon/AMD/Styx/AcpiTables/AcpiAml.inf +++ /dev/null @@ -1,29 +0,0 @@ -#/** @file -# -# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = AcpiAml - FILE_GUID = 2df2a2ee-5f34-4dea-b4b6-da724e455f33 - MODULE_TYPE = USER_DEFINED - VERSION_STRING = 1.0 - -[Sources] - Dsdt.asl - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/AMD/Styx/AmdStyx.dec - diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf index 692717950f40..0bc5b1e98964 100644 --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf @@ -36,7 +36,6 @@ Madt.c Mcfg.c Csrt.c - Dsdt.c Iort.c Pptt.c diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index cc2320e4262d..92f185fa4bee 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -28,6 +28,7 @@ [Sources] AcpiPlatform.c + Dsdt.asl SsdtB1.asl SsdtXgbe.asl diff --git a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h index 58e160b6d727..0dfd7635e897 100644 --- a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h +++ b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h @@ -22,7 +22,6 @@ EFI_ACPI_DESCRIPTION_HEADER *FadtTable (void); EFI_ACPI_DESCRIPTION_HEADER *FacsTable (void); EFI_ACPI_DESCRIPTION_HEADER *MadtHeader (void); EFI_ACPI_DESCRIPTION_HEADER *GtdtHeader (void); -EFI_ACPI_DESCRIPTION_HEADER *DsdtHeader (void); EFI_ACPI_DESCRIPTION_HEADER *McfgHeader (void); EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void); EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void); diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.c b/Silicon/AMD/Styx/AcpiTables/Dsdt.c deleted file mode 100644 index 25e654acabbc..000000000000 --- a/Silicon/AMD/Styx/AcpiTables/Dsdt.c +++ /dev/null @@ -1,26 +0,0 @@ -/** @file - - C language wrapper to build DSDT generated data. - - Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include - -EFI_ACPI_DESCRIPTION_HEADER * -DsdtHeader ( - VOID - ) -{ - return (EFI_ACPI_DESCRIPTION_HEADER *) &AmlCode[0]; -} diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 460fb4c480c3..a00bd3bd2215 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -176,7 +176,6 @@ AcpiPlatformEntryPoint ( TableIndex = 0; AcpiTableList[TableIndex++] = FadtTable(); - AcpiTableList[TableIndex++] = DsdtHeader(); AcpiTableList[TableIndex++] = MadtHeader(); AcpiTableList[TableIndex++] = GtdtHeader(); AcpiTableList[TableIndex++] = Dbg2Header(); diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.asl b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl similarity index 100% rename from Silicon/AMD/Styx/AcpiTables/Dsdt.asl rename to Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl From patchwork Wed Dec 5 18:50:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 152929 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp9641006ljp; Wed, 5 Dec 2018 10:50:42 -0800 (PST) X-Google-Smtp-Source: AFSGD/X6Q5j7bhOT9wU5cmv6JuFIcxVWXSf5CmlE0w17j1ko/1qR++BeLoy2/wLrFo1rShniuKAk X-Received: by 2002:a65:48c4:: with SMTP id o4mr20738376pgs.371.1544035842831; Wed, 05 Dec 2018 10:50:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544035842; cv=none; d=google.com; s=arc-20160816; b=KShtapF/uCCDtWseKFqQubWTRDmblzvIjatEnGDbaFh2h5J/37JRNUgRHn2ZpkYWKg c1UOB2eli2jvnhy3KX6MA7z9m2ia8xfYo9JPw3GmNXHjXKb+3lSgP870w0BGTqDlo/SD YLehD/SDpZI1pYDUOQbzxN/rhc+9w2gKZ1uE+77KUOknoOEGAhZHbVAdWTEm+tmh5v17 RUN2Osl4+HvHcZSGusZ7VdLhP2t8JTxxPqo6/YNEiW1ErZW8KWqnSO7FEDnjS004q04p w8WAqAOT5+Uj5FQUH5e1/zewHFeLalvJrsYEymKrCA5GsSE2mYtdaJ9HzovYjTht5kr/ B96g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:dkim-signature:delivered-to; bh=iqjA/2JlV9cLxIPAJK1N6ntV3S4aNu7HSP7uPJR0Lzo=; b=fzxrOcv/i4LwdSVJopPfoERsB9wnUU74Dha2YynNOgb4tLAtDGyo3dIz20B14DBpXS F1oCTgLsrpZnBXL188hd8iZJTWg9MtMZz7c0o67InNQ32T54AoIzlnwRFhThxhlvYXK2 q66stqic4vKZLQatkjaDuTfa+raIJXlLt9kM5JcHb+cvkiflj//2aynjJR1cYhJufjtG dMxprDFx+dmndbS61wxV075mL1Vq3uO+8KvrZQC5wULkmh4QoC4S5VvDrWY4wJyIAXw0 zgoVPk2ekemOhAmLWazGDiupxpKXGleN/LYkaXCWsUuEXrBZenky3576qz8vtFGkKgXw jWkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LyhLZGxD; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id n3si17998718pgk.405.2018.12.05.10.50.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LyhLZGxD; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CA6FE21199274; Wed, 5 Dec 2018 10:50:33 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DC8BE21BADAB3 for ; Wed, 5 Dec 2018 10:50:32 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id g67so13957227wmd.2 for ; Wed, 05 Dec 2018 10:50:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JPYyx9/Z0oUqXu2Ggk5sE4P9bYRvxoGjTJihdji1Vro=; b=LyhLZGxDQidkZY+ohtEMPUf7yFq6B/J0AgOE7d1BcPryaCa5vIAH4GhHGVEDwxxaMZ KVDNJO6sMEBwC9feWQrM52IENGzZ0wYli/+egrGyij7xAE1TfyTLcpWxwt3MPIDN4u9B JsDdntRNS9y9pNgP63U1Aug7cmW/p7LqXH67g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JPYyx9/Z0oUqXu2Ggk5sE4P9bYRvxoGjTJihdji1Vro=; b=nv06eZm3U6re1XsTSmlkb96vRVPd0Z4XpyxRmIbGzGIl0t0UM6HepSKLUVJoTx9LMC nsbrVXGZsCp2DoUDWnD2zyzryEpTJn3deJZfktFtpXO4Eo4qQC6dFf08zerZlqxA1roa rygCV6Zo705HBv8BuMXIuWnAA5Gc01BrMEOkqkUmO8svbBtaphEr60X8X00SlnmdjCdf OKZ89VJfc/zYiCfV73OBSlqxCde6wnVPriYkWXwoYuhP7RBQiyYDklDoSt78Hj/dJThi utqruHUIssIHqskX+HkFmJRaXK7RhByB6gG0DnXaPfFzsZhBrmVSCh6U/5Ki+dU3ZyW5 WfSg== X-Gm-Message-State: AA+aEWa7RaTo4tMUHJH+MEq4tDXc9+S0ZPFr8K/iz7J8t7HgCxxcxfsg 7eoZFN4B6ILUtNAaDM6TzibyKmquC4n8vA== X-Received: by 2002:a7b:c44d:: with SMTP id l13mr17234696wmi.144.1544035830308; Wed, 05 Dec 2018 10:50:30 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:816d:4a95:a2ca:814d]) by smtp.gmail.com with ESMTPSA id c8sm14825186wrx.42.2018.12.05.10.50.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:29 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Dec 2018 19:50:19 +0100 Message-Id: <20181205185020.21441-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181205185020.21441-1-ard.biesheuvel@linaro.org> References: <20181205185020.21441-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 5/6] Platform: add acpiview to Seattle/Styx platforms X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Enable the 'acpiview' UEFI shell command so we can inspect the ACPI tables at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 1 + Platform/LeMaker/CelloBoard/CelloBoard.dsc | 1 + Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 1 + 3 files changed, 3 insertions(+) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Jaben Carsey diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 7c66af6128c5..ed67c986b7db 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -731,6 +731,7 @@ DEFINE DO_CAPSULE = FALSE NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index 7c22bbbfa90f..057bf0eb67de 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -663,6 +663,7 @@ DEFINE DO_FLASHER = FALSE NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 793bd5359a23..985ba2253a90 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -658,6 +658,7 @@ DEFINE DO_FLASHER = FALSE NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf From patchwork Wed Dec 5 18:50:20 2018 Content-Type: text/plain; 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[198.145.21.10]) by mx.google.com with ESMTPS id j65si18920393pge.444.2018.12.05.10.50.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=M3dqxeTu; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0146021199251; Wed, 5 Dec 2018 10:50:35 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::441; helo=mail-wr1-x441.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C750221199269 for ; Wed, 5 Dec 2018 10:50:33 -0800 (PST) Received: by mail-wr1-x441.google.com with SMTP id v13so20779214wrw.5 for ; Wed, 05 Dec 2018 10:50:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z8ZZZHEfsBZCni79fiMXTqfWgD9x9+ssdXC8qYA1Buw=; b=M3dqxeTuUmNvcGNXeWmgF+MrGOtQDc5LZlKv46gBRaUd6vrSfguGntMVQX/XzZFpFC os2p30UeAG2kDqCly1UC4oiZ0yK8XXiJU0Vm3rmDlqAASnq3Io3tUbHj35WLr/76rkKf RgZ2YuFtE8vLUbUwc+aHvalZUWTM+K6NMcqbE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z8ZZZHEfsBZCni79fiMXTqfWgD9x9+ssdXC8qYA1Buw=; b=DRaWCxjxL5hTUJJvFpbgfai1/QM1PIW6P8QNr+k1Fhx7M0/DohRuL7HE6Y+V0AL1tV gaS/yJ5W/9OsEQ067h4yXluXf4NWvjCyEhpo0b10wcfwkGi8AKNaT2HepD5wg1dbkvXr wOc05hLRJroobX7ZmelXoyjCg/JYcBNvJ5/469jovn2GyGnEuQzQdj0gLV6E0T7/QN1p J6/IkkQNlW6jr2zfJ1Q/gG1Pg3TVNHPZQXPbnqGXtZLQjXi6d5YjNM60Q8Qi1W/YBcgr hub128I60MJvr/TBlogyQ4L/fiWVWAbv30gLt2d6txWlVNDA0usM7LOAn1pHTCnLZe9W /03Q== X-Gm-Message-State: AA+aEWZtb51PtuoAq9AkyzbzTpuZkWZquThGlYHbmUCqHBmL5h41nJyX BVucKiqpNCwYWL5WYYO87iyKC+8jJl+Lng== X-Received: by 2002:adf:fb4c:: with SMTP id c12mr21847636wrs.297.1544035831993; Wed, 05 Dec 2018 10:50:31 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:816d:4a95:a2ca:814d]) by smtp.gmail.com with ESMTPSA id c8sm14825186wrx.42.2018.12.05.10.50.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:30 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Dec 2018 19:50:20 +0100 Message-Id: <20181205185020.21441-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181205185020.21441-1-ard.biesheuvel@linaro.org> References: <20181205185020.21441-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 6/6] Platform/AMD/OverdriveBoard: use default resolution for GOP X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Set the GOP resolution to 0x0 so that the resolution will be chosen by the driver, usually based on the capabilities of the connected display. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 3 +++ 1 file changed, 3 insertions(+) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index ed67c986b7db..05433d4472e8 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -485,6 +485,9 @@ DEFINE DO_CAPSULE = FALSE gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1 gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 + [PcdsDynamicDefault.common] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES) gArmTokenSpaceGuid.PcdSystemMemorySize|0x0400000000