From patchwork Tue Mar 8 14:24:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 550301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FA6AC4321E for ; Tue, 8 Mar 2022 14:24:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347403AbiCHOZY (ORCPT ); Tue, 8 Mar 2022 09:25:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347322AbiCHOZX (ORCPT ); Tue, 8 Mar 2022 09:25:23 -0500 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 699D249F92; Tue, 8 Mar 2022 06:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646749467; x=1678285467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tK6Q1jDnBvijOHqCEkvoL00vEaJl4FM8rW1EITUDKrs=; b=ltNCn1criIAwWcvhYb4S7NnaH3fluZAvXzh65Pd3+sMtsNZHFChXA4Ro IypkuG9vitQ6QjH931nPRNR2WNMAhtpWHNWtEMq7zivlDuOTviqIcIvDU 54OXk1IWIYHSQv0i15Fd2fzMNzMpE5qLtJ/BzgWSeOxCEgHlO51wkDtX9 gXQeMQ39X0EAAYAZli70R2DZPC8FjDd8iLJtZMEiUZ2Qrn7eEe5Dl/hOl B79ggAr8nAbtCpbYevD5GfGSv2sOqnUUBM4jHmeWQ40Lg/JODeh/3zU3N rSpy6QSBsBdRVucbluuEmmF2J7FaY/R13PT/oGQpT724BqWk+NFmCretc w==; From: Vincent Whitchurch To: , , CC: , , , , , , , Vincent Whitchurch Subject: [PATCH v2 1/4] dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT Date: Tue, 8 Mar 2022 15:24:07 +0100 Message-ID: <20220308142410.3193729-2-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220308142410.3193729-1-vincent.whitchurch@axis.com> References: <20220308142410.3193729-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This SoC has an MCT with 4 global and 8 local timer interrupts, add a specific compatible to match it as is done for the other platforms with this hardware block. Signed-off-by: Vincent Whitchurch --- Notes: v2: New. Requires Krzysztof's "dt-bindings: timer: exynos4210-mct: describe hardware and its interrupts". .../devicetree/bindings/timer/samsung,exynos4210-mct.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 1584944c7ac4..dce42f1f7574 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos4412-mct - items: - enum: + - axis,artpec8-mct - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -102,6 +103,7 @@ allOf: compatible: contains: enum: + - axis,artpec8-mct - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct From patchwork Tue Mar 8 14:24:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 549595 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DBF0C433F5 for ; Tue, 8 Mar 2022 14:24:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343682AbiCHOZZ (ORCPT ); Tue, 8 Mar 2022 09:25:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347353AbiCHOZX (ORCPT ); Tue, 8 Mar 2022 09:25:23 -0500 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A236347AF5; Tue, 8 Mar 2022 06:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646749467; x=1678285467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6KwAXn4jvSph/kkMgeY9egBCzjFV3kNndn+PTRpZ548=; b=gKmdEYXwJY8KE9ZYdnBVVQtB70opXBFB+odyd2FHOGMCIoxFBwUyFEa1 XPgSZNVeLUtEGYmjhhBb625SYjZLOIx7otitfxn5691lBZzcoGl9+Z+0z WpbM0YIphiocp0362ZP4M0yVQtjWzFFpWlqQuE6qDox+Fi32ylZMvfEtD HvwH3vOuHoT9PfWHb5A7N68h7P7QlyRBeKtX7KerqdF3g/KoaBpGMiNk3 4/DMvuaBcbLJWGNA5OymjYGNy8iOG2+QUinBq3Qck+rPZ8Zj6BlPRvzaM Vx+4vhyt3IqIqkOJBOFs3EVozN4Frnjgw7wQ/hV0Jto63X/YMpbTQQlEx g==; From: Vincent Whitchurch To: , , CC: , , , , , , , Vincent Whitchurch Subject: [PATCH v2 2/4] dt-bindings: timer: exynos4210-mct: Support using only local timer Date: Tue, 8 Mar 2022 15:24:08 +0100 Message-ID: <20220308142410.3193729-3-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220308142410.3193729-1-vincent.whitchurch@axis.com> References: <20220308142410.3193729-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The ARTPEC-8 SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global FRC and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots, we should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this usecase, add a property to the binding to specify the first local timer index to be used. If this parameter is non-zero, the global timer interrupts will also not be used. Signed-off-by: Vincent Whitchurch --- Notes: v2: New. .../bindings/timer/samsung,exynos4210-mct.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index dce42f1f7574..46f466081836 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -47,6 +47,15 @@ properties: reg: maxItems: 1 + local-timer-index: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maximum: 15 # Last local timer index + description: | + If present, sets the first local timer index to use. If this value is + set to a non-default value, the global timer will not be used for + interrupts. + interrupts: description: | Interrupts should be put in specific order. This is, the local timer From patchwork Tue Mar 8 14:24:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 550302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6530C4332F for ; Tue, 8 Mar 2022 14:24:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347095AbiCHOZX (ORCPT ); Tue, 8 Mar 2022 09:25:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230433AbiCHOZV (ORCPT ); Tue, 8 Mar 2022 09:25:21 -0500 Received: from smtp2.axis.com (smtp2.axis.com [195.60.68.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 690CC4B859; Tue, 8 Mar 2022 06:24:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646749463; x=1678285463; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rFioSpH+5uUKbkMGJw1iA2/404Dx7lV4IUNdiyH/vxw=; b=JMpGYNo9FAtHlhNQqdUWImuQ8GADoh/QigC1WxRr82ppGbKGzv02i2en Vuvz3SOelwX4x/seJSxoPDxseaassK7HLel1PCsD7WF2NLM8Oa+TDEqGG NwUvSmdd43ZUbmOnv+ZKRVN1URhz5Hl5xC1FpK7CFOB2jrr+TbxLYkM1f SnB4sm7M36fI9lf2vRzaSBgdCLRxAgd0NVwH4y4/yPJdK4E61xxJzBAyV NfTQte/S9+hDL9rSSarMw0JZ2GV7IVr68dlKvB0siOebz02raAyEPqRAC 6FwUA1+/2doAaQz/b8QvixdnhSVme7rNudk64qsZ99uev7YE1MYYqt/lM Q==; From: Vincent Whitchurch To: , , CC: , , , , , , , Vincent Whitchurch Subject: [PATCH v2 3/4] clocksource/drivers/exynos_mct: Support local-timer-index property Date: Tue, 8 Mar 2022 15:24:09 +0100 Message-ID: <20220308142410.3193729-4-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220308142410.3193729-1-vincent.whitchurch@axis.com> References: <20220308142410.3193729-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Support the documented semantics of the local-timer-index property: Use it as the first index of the local timer, ensure that global timer clock events device is not registered, and don't write to the global FRC if it is already started. Signed-off-by: Vincent Whitchurch --- Notes: v2: Use devicetree property instead of module parameter. drivers/clocksource/exynos_mct.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index f29c812b70c9..5f8b516614eb 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -33,7 +33,7 @@ #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) -#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) +#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * (x))) #define EXYNOS4_MCT_L_MASK (0xffffff00) #define MCT_L_TCNTB_OFFSET (0x00) @@ -75,6 +75,7 @@ enum { static void __iomem *reg_base; static unsigned long clk_rate; static unsigned int mct_int_type; +static unsigned int mct_local_idx; static int mct_irqs[MCT_NR_IRQS]; struct mct_clock_event_device { @@ -157,6 +158,17 @@ static void exynos4_mct_frc_start(void) u32 reg; reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); + + /* + * If the FRC is already running, we don't need to start it again. We + * could probably just do this on all systems, but, to avoid any risk + * for regressions, we only do it on systems where it's absolutely + * necessary (i.e., on systems where writes to the global registers + * need to be avoided). + */ + if (mct_local_idx && (reg & MCT_G_TCON_START)) + return; + reg |= MCT_G_TCON_START; exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); } @@ -449,7 +461,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) per_cpu_ptr(&percpu_mct_tick, cpu); struct clock_event_device *evt = &mevt->evt; - mevt->base = EXYNOS4_MCT_L_BASE(cpu); + mevt->base = EXYNOS4_MCT_L_BASE(mct_local_idx + cpu); snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); evt->name = mevt->name; @@ -554,13 +566,14 @@ static int __init exynos4_timer_interrupts(struct device_node *np, } else { for_each_possible_cpu(cpu) { int mct_irq; + unsigned int irqidx = MCT_L0_IRQ + mct_local_idx + cpu; struct mct_clock_event_device *pcpu_mevt = per_cpu_ptr(&percpu_mct_tick, cpu); pcpu_mevt->evt.irq = -1; - if (MCT_L0_IRQ + cpu >= ARRAY_SIZE(mct_irqs)) + if (irqidx >= ARRAY_SIZE(mct_irqs)) break; - mct_irq = mct_irqs[MCT_L0_IRQ + cpu]; + mct_irq = mct_irqs[irqidx]; irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); if (request_irq(mct_irq, @@ -607,6 +620,8 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type) { int ret; + of_property_read_u32(np, "local-timer-index", &mct_local_idx); + ret = exynos4_timer_resources(np); if (ret) return ret; @@ -619,7 +634,7 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type) if (ret) return ret; - return exynos4_clockevent_init(); + return (mct_local_idx == 0) ? exynos4_clockevent_init() : ret; } From patchwork Tue Mar 8 14:24:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 549597 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 711FCC433FE for ; Tue, 8 Mar 2022 14:24:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245687AbiCHOZW (ORCPT ); Tue, 8 Mar 2022 09:25:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343682AbiCHOZU (ORCPT ); Tue, 8 Mar 2022 09:25:20 -0500 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 439D84B849; Tue, 8 Mar 2022 06:24:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646749463; x=1678285463; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gchs80jcH+/5TFd0a5Cy8wkt4l2VcoMbwk5kapLsbnY=; b=YecgrHTgaYodtEGv0gXOUJy10uw57FE8fGJKquWmmLk69aponOEHrFNa znlWt91z98sQSQ6pEML2n+Y76vFXDsqDONHbLrkTiUMo/RmNN32cJ3Z+5 y9Lm4VFzP2kgPzxArDiK4Aw9Ubhi2A7du40fyLqWX0eztSH2lgipU5q7U 9BcKFmwT62RJXQdSFTAL5ZOVbzKOLNyNLykaAl3LXTP5cAfY5JIg2XINC yBZQ5SWdCCxvgBgqpyWF+Gbg9VJq7bAt/zam0LdmypHoPEpJ6xpZgGitX AoVk8ylL62wVFShbZxohe0+TF+qrYKZIIBdBcKI9hIUFakXIOLyEGA04A Q==; From: Vincent Whitchurch To: , , CC: , , , , , , , Vincent Whitchurch Subject: [PATCH v2 4/4] clocksource/drivers/exynos_mct: Enable building on ARTPEC Date: Tue, 8 Mar 2022 15:24:10 +0100 Message-ID: <20220308142410.3193729-5-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220308142410.3193729-1-vincent.whitchurch@axis.com> References: <20220308142410.3193729-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This timer block is used on ARTPEC-8. Signed-off-by: Vincent Whitchurch Reviewed-by: Krzysztof Kozlowski --- Notes: v2: No changes. drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index ae95d06a4a8f..2ea981ef23af 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -419,7 +419,7 @@ config ATMEL_TCB_CLKSRC config CLKSRC_EXYNOS_MCT bool "Exynos multi core timer driver" if COMPILE_TEST depends on ARM || ARM64 - depends on ARCH_EXYNOS || COMPILE_TEST + depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST help Support for Multi Core Timer controller on Exynos SoCs.