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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Mar 2022 13:05:50.3844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03d92f48-8667-4e59-63f9-08da003b342f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5566 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta Carry out runtime-resume of PCI tunnelled root port to handle hotplug interrupts synchronously. Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/acpi.c | 3 +++ drivers/thunderbolt/tb.c | 11 +++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/thunderbolt/acpi.c b/drivers/thunderbolt/acpi.c index 79b5abf..10dd61b 100644 --- a/drivers/thunderbolt/acpi.c +++ b/drivers/thunderbolt/acpi.c @@ -96,6 +96,9 @@ static acpi_status tb_acpi_add_link(acpi_handle handle, u32 level, void *data, dev_name(&pdev->dev)); } + pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put(&pdev->dev); } diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c index cbd0ad8..2a53fa6 100644 --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c @@ -1066,6 +1066,7 @@ static int tb_tunnel_pci(struct tb *tb, struct tb_switch *sw) struct tb_cm *tcm = tb_priv(tb); struct tb_switch *parent_sw; struct tb_tunnel *tunnel; + struct device_link *link; up = tb_switch_find_port(sw, TB_TYPE_PCIE_UP); if (!up) @@ -1099,6 +1100,16 @@ static int tb_tunnel_pci(struct tb *tb, struct tb_switch *sw) if (tb_switch_pcie_l1_enable(sw)) tb_sw_warn(sw, "failed to enable PCIe L1 for Titan Ridge\n"); + list_for_each_entry(link, &tb->nhi->pdev->dev.links.consumers, s_node) { + if (pci_pcie_type(to_pci_dev(link->consumer)) == PCI_EXP_TYPE_ROOT_PORT) { + if (pm_runtime_status_suspended(link->consumer)) { + pm_runtime_get_sync(link->consumer); + pm_runtime_mark_last_busy(link->consumer); + pm_runtime_put_sync_autosuspend(link->consumer); + } + } + } + list_add_tail(&tunnel->list, &tcm->tunnel_list); return 0; }