From patchwork Mon Mar 14 21:31:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BF60C43219 for ; Mon, 14 Mar 2022 21:32:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245293AbiCNVdY (ORCPT ); Mon, 14 Mar 2022 17:33:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245254AbiCNVdY (ORCPT ); Mon, 14 Mar 2022 17:33:24 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D151E33E33 for ; Mon, 14 Mar 2022 14:32:12 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 8AAF42C0B80; Mon, 14 Mar 2022 21:32:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647293527; bh=2RPTSAdyVtpUg1sJZUHpNlYQIyVzDQpmpXfR39uDo9w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=1i7Bf996rtYlwG96l34FTa72f1IO/3VaEs8//EjQF5uXuNvxyfLa02xWbwk7KyfD0 7t3oYAwUtGMWzZboPmHtb55lEBnQ/jF/0jVrz+KqDpPSRSnJRIz6RK0k6pjujMQHoB EuKJ3jSsoPP8l+5MQV1NHsxF3v3WQvOs5BVEjmWdPs1qHMkNkGd7CcTYgjTWPR15lj ifgp9qjKSyARR327jOTe/dIRPE5/14GQ0e5NcOCasd4Pz4t0s5i4aaSmlM1LYkQdag UkzbJkOSw4dj4FwlbMDEOIiEtxJ671QzkmiMjUE+Nk7h02hGcrz5XPpMMc3cJmH0af C3kXr6PW0Z1PA== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 15 Mar 2022 10:32:07 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 0892313EE3F; Tue, 15 Mar 2022 10:32:07 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id E14F42A2677; Tue, 15 Mar 2022 10:32:03 +1300 (NZDT) From: Chris Packham To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org, davem@davemloft.net, kuba@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, adrian.hunter@intel.com, thomas.petazzoni@bootlin.com, kostap@marvell.com, robert.marko@sartura.hr Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 1/8] dt-bindings: pinctrl: mvebu: Document bindings for AC5 Date: Tue, 15 Mar 2022 10:31:36 +1300 Message-Id: <20220314213143.2404162-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> References: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=gEfo2CItAAAA:8 a=neyTTwDIlupdRa_uz6AA:9 a=sptkURWiP4Gy88Gu7hUp:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add JSON schema for marvell,ac5-pinctrl present on the Marvell 98DX2530 SoC. Signed-off-by: Chris Packham --- Notes: Changes in v2: - Remove syscon and simple-mfd compatibles .../bindings/pinctrl/marvell,ac5-pinctrl.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml new file mode 100644 index 000000000000..65af1d5f5fe0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,ac5-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell AC5 pin controller + +maintainers: + - Chris Packham + +description: + Bindings for Marvell's AC5 memory-mapped pin controller. + +properties: + compatible: + const: marvell,ac5-pinctrl + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + + properties: + marvell,function: + $ref: "/schemas/types.yaml#/definitions/string" + description: + Indicates the function to select. + enum: [ gpio, i2c0, i2c1, nand, sdio, spi0, spi1, uart0, uart1, uart2, uart3 ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + items: + enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, mpp19, + mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, mpp26, mpp27, mpp28, mpp29, + mpp30, mpp31, mpp32, mpp33, mpp34, mpp35, mpp36, mpp37, mpp38, mpp39, + mpp40, mpp41, mpp42, mpp43, mpp44, mpp45 ] + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + - | + system-controller@80020100 { + compatible = "syscon", "simple-mfd"; + reg = <0x80020000 0x20>; + + pinctrl0: pinctrl { + compatible = "marvell,ac5-pinctrl"; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c0"; + }; + + i2c0_gpio: i2c0-gpio-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + }; + }; From patchwork Mon Mar 14 21:31:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02CB5C433EF for ; Mon, 14 Mar 2022 21:32:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245270AbiCNVdX (ORCPT ); Mon, 14 Mar 2022 17:33:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245254AbiCNVdX (ORCPT ); Mon, 14 Mar 2022 17:33:23 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A0583388B for ; Mon, 14 Mar 2022 14:32:10 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id EC1B32C0C23; Mon, 14 Mar 2022 21:32:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647293527; bh=L4VCOUAX7o5pSVh/zKud04ppcqVy8H/eB4l1M5HSVy0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AGU44anjyAvxn1CkK7IQsm9DXOwsSNvpHEs6TWsiueC2vDsZOp4R29uB2SOePwlB2 kB/eY116C5kpjzfodqts9x9NeEIx1DmUhBvd1ep87lEeX1Q2ycruZSPB0veTQGZlEZ Max+dhTprmWYDJLVRvpbocBxHlF2Y/5X7DLxvAtVhrCZ4DhQ4RvKTJJt/308CjVDfU Xt+j6kX0ksC0Ten2FDDgxkXPSjDvfWRZvsjxdWRuIFUTdRG2mJEKEexwRvfgZh2y2H Xq06OfDLgvhdQ3Z4sQJTJBCuuKUEn/xf7DICfFZeSj8RnmWbNx59fut1k1Y2ccG2Ca C10nZ9mzWsESg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 15 Mar 2022 10:32:07 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 0B2D013EE56; Tue, 15 Mar 2022 10:32:07 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id E541D2A267A; Tue, 15 Mar 2022 10:32:03 +1300 (NZDT) From: Chris Packham To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org, davem@davemloft.net, kuba@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, adrian.hunter@intel.com, thomas.petazzoni@bootlin.com, kostap@marvell.com, robert.marko@sartura.hr Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 2/8] dt-bindings: net: mvneta: Add marvell,armada-ac5-neta Date: Tue, 15 Mar 2022 10:31:37 +1300 Message-Id: <20220314213143.2404162-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> References: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=GiZJWJlgZr2mIF3OtF0A:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The out of band port on the 98DX2530 SoC is similar to the armada-3700 except it requires a slightly different MBUS window configuration. Add a new compatible string so this difference can be accounted for. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- Notes: Changes in v2: - New .../devicetree/bindings/net/marvell-armada-370-neta.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt index 691f886cfc4a..2bf31572b08d 100644 --- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt +++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt @@ -5,6 +5,7 @@ Required properties: "marvell,armada-370-neta" "marvell,armada-xp-neta" "marvell,armada-3700-neta" + "marvell,armada-ac5-neta" - reg: address and length of the register set for the device. - interrupts: interrupt for the device - phy: See ethernet.txt file in the same directory. From patchwork Mon Mar 14 21:31:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551510 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CE0EC433F5 for ; Mon, 14 Mar 2022 21:32:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245321AbiCNVdb (ORCPT ); Mon, 14 Mar 2022 17:33:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245266AbiCNVdX (ORCPT ); Mon, 14 Mar 2022 17:33:23 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A56D033A38 for ; Mon, 14 Mar 2022 14:32:12 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 5F02A2C049B; Mon, 14 Mar 2022 21:32:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647293527; bh=tk1E4VagxLubGQCwJVnsW/0dqlT2PhJSY91Py3AQRjI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aLFHu1LVVtnH+HDj69dWPBHDKFzQ9qkU+Uo5GrBMMLanflF/rRV63kqqTrtg2pu7L UrD9BsyniTBZ4i0blG0Qg2EniPkOkMPeJz5UfkF71voYP7NZxzBMAtjZwMM8w8BoZe jaAytWpz8SywlrnIwm9TiWDyLxhSPNZqK0xzII9D3b6mTvOREe9Sg8XZq51nPVnwV+ c0yU8wqimYp+xz/+W5dKd0wmJvf670O8wySRi5/Fy6v8q9BJamfkREXX49mpbyXpVI M7v8mJYhoHfDk13bUGwgq6AX2jfbdNN+Yqi/1vg44lQcKOTJWCNpkMz0eSLvUnonJ5 wMNt6Q+HIrr9A== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 15 Mar 2022 10:32:07 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 0D90D13EE8E; Tue, 15 Mar 2022 10:32:07 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id E8A162A2678; Tue, 15 Mar 2022 10:32:03 +1300 (NZDT) From: Chris Packham To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org, davem@davemloft.net, kuba@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, adrian.hunter@intel.com, thomas.petazzoni@bootlin.com, kostap@marvell.com, robert.marko@sartura.hr Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 3/8] dt-bindings: mmc: xenon: add AC5 compatible string Date: Tue, 15 Mar 2022 10:31:38 +1300 Message-Id: <20220314213143.2404162-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> References: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=ZuYvX9HxE-CSu40lHJ4A:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Import binding documentation from the Marvell SDK which adds marvell,ac5-sdhci compatible string and documents the requirements for the for the Xenon SDHCI controller on the 98DX2530. Signed-off-by: Chris Packham --- Notes: Changes in v2: - New .../bindings/mmc/marvell,xenon-sdhci.txt | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt index c51a62d751dc..43df466f0cb3 100644 --- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt @@ -14,6 +14,7 @@ Required Properties: - "marvell,armada-ap806-sdhci": For controllers on Armada AP806. - "marvell,armada-ap807-sdhci": For controllers on Armada AP807. - "marvell,armada-cp110-sdhci": For controllers on Armada CP110. + - "marvell,ac5-sdhci": For CnM on AC5, AC5X and derived. - clocks: Array of clocks required for SDHC. @@ -33,6 +34,13 @@ Required Properties: in below. Please also check property marvell,pad-type in below. + * For "marvell,ac5-sdhci", one or two register areas. + (reg-names "ctrl" & "decoder"). + The first one is mandatory for the Xenon IP registers. + The second one is for systems where DMA mapping is required and is the + related address decoder register (the value to configure is derived from + the parent "dma-ranges"). + * For other compatible strings, one register area for Xenon IP. Optional Properties: @@ -171,3 +179,47 @@ Example: marvell,pad-type = "sd"; }; + + +- For eMMC with compatible "marvell,ac5-sdhci" with one reg range (no dma): + sdhci0: sdhci@805c0000 { + compatible = "marvell,ac5-sdhci"; + reg = <0x0 0x805c0000 0x0 0x300>; + reg-names = "ctrl", "decoder"; + interrupts = ; + clocks = <&core_clock>; + clock-names = "core"; + status = "okay"; + bus-width = <8>; + /*marvell,xenon-phy-slow-mode;*/ + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + +- For eMMC with compatible "marvell,ac5-sdhci" with two reg ranges (with dma): + mmc_dma: mmc-dma-peripherals@80500000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + dma-ranges = <0x2 0x0 0x2 0x80000000 0x1 0x0>; + dma-coherent; + + sdhci0: sdhci@805c0000 { + compatible = "marvell,ac5-sdhci", "marvell,armada-ap806-sdhci"; + reg = <0x0 0x805c0000 0x0 0x300>, <0x0 0x80440230 0x0 0x4>; + reg-names = "ctrl", "decoder"; + interrupts = ; + clocks = <&core_clock>; + clock-names = "core"; + status = "okay"; + bus-width = <8>; + /*marvell,xenon-phy-slow-mode;*/ + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + }; From patchwork Mon Mar 14 21:31:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551128 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8946C433EF for ; Mon, 14 Mar 2022 21:32:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245316AbiCNVd2 (ORCPT ); Mon, 14 Mar 2022 17:33:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245272AbiCNVdX (ORCPT ); Mon, 14 Mar 2022 17:33:23 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABD4633E21 for ; Mon, 14 Mar 2022 14:32:12 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 00B942C0C2A; Mon, 14 Mar 2022 21:32:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647293528; bh=fyeaQDUHhP/ZXergWd2lC+OvXrTtCNTg4n9clMIJ8Sc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UHxbeSG2SUfHH0t7EG0pEueewAM0BHGhn2apaXbIOnCaLJ1fxDfwcDPfACU5DRiXj WR/je/TcJRDj2GduQn82nD4hlEGij6qw4J7vmGsrL+IgI7BjAHUBs6sYvDZuTRS0Li UP3tG4ZMDKG+zJK2jimN9XS0sR6QmIAIEY/HqVH77iBuiaIlIXze8G6W+SvCJllKNS HpazooKWLd9UwW5QpPLRd1m70k6G89EhWKM+WbKvq6dbLhTvKbUi+oiVAILCfqmgSz cwnT2e2uw425D6GFVI4/LFk45mrFrsz2zVD0G1XJ/MlieBgZueWDClpbIlrvAPzu/J 4UgxnwoWxNWjg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 15 Mar 2022 10:32:07 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 10FA313EEA1; Tue, 15 Mar 2022 10:32:07 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id EBE402A2678; Tue, 15 Mar 2022 10:32:03 +1300 (NZDT) From: Chris Packham To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org, davem@davemloft.net, kuba@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, adrian.hunter@intel.com, thomas.petazzoni@bootlin.com, kostap@marvell.com, robert.marko@sartura.hr Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 4/8] pinctrl: mvebu: pinctrl driver for 98DX2530 SoC Date: Tue, 15 Mar 2022 10:31:39 +1300 Message-Id: <20220314213143.2404162-5-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> References: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=M5GUcnROAAAA:8 a=gBXrc1Pfy3FSj49WI4IA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This pinctrl driver supports the 98DX25xx and 98DX35xx family of chips from Marvell. It is based on the Marvell SDK with additions for various (non-gpio) pin configurations based on the datasheet. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- Notes: Changes in v2: - Make pinctrl a child of a syscon node like the armada-7k-pinctrl drivers/pinctrl/mvebu/Kconfig | 4 + drivers/pinctrl/mvebu/Makefile | 1 + drivers/pinctrl/mvebu/pinctrl-ac5.c | 226 ++++++++++++++++++++++++++++ 3 files changed, 231 insertions(+) create mode 100644 drivers/pinctrl/mvebu/pinctrl-ac5.c diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig index 0d12894d3ee1..aa5883f09d7b 100644 --- a/drivers/pinctrl/mvebu/Kconfig +++ b/drivers/pinctrl/mvebu/Kconfig @@ -45,6 +45,10 @@ config PINCTRL_ORION bool select PINCTRL_MVEBU +config PINCTRL_AC5 + bool + select PINCTRL_MVEBU + config PINCTRL_ARMADA_37XX bool select GENERIC_PINCONF diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile index cd082dca4482..23458ab17c53 100644 --- a/drivers/pinctrl/mvebu/Makefile +++ b/drivers/pinctrl/mvebu/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_PINCTRL_ARMADA_CP110) += pinctrl-armada-cp110.o obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o obj-$(CONFIG_PINCTRL_ARMADA_37XX) += pinctrl-armada-37xx.o obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o +obj-$(CONFIG_PINCTRL_AC5) += pinctrl-ac5.o diff --git a/drivers/pinctrl/mvebu/pinctrl-ac5.c b/drivers/pinctrl/mvebu/pinctrl-ac5.c new file mode 100644 index 000000000000..8bc0bbff7c1b --- /dev/null +++ b/drivers/pinctrl/mvebu/pinctrl-ac5.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Marvell ac5 pinctrl driver based on mvebu pinctrl core + * + * Copyright (C) 2021 Marvell + * + * Noam Liron + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-mvebu.h" + +static struct mvebu_mpp_mode ac5_mpp_modes[] = { + MPP_MODE(0, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d0"), + MPP_FUNCTION(2, "nand", "io4")), + MPP_MODE(1, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d1"), + MPP_FUNCTION(2, "nand", "io3")), + MPP_MODE(2, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d2"), + MPP_FUNCTION(2, "nand", "io2")), + MPP_MODE(3, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d3"), + MPP_FUNCTION(2, "nand", "io7")), + MPP_MODE(4, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d4"), + MPP_FUNCTION(2, "nand", "io6"), + MPP_FUNCTION(3, "uart3", "txd"), + MPP_FUNCTION(4, "uart2", "txd")), + MPP_MODE(5, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d5"), + MPP_FUNCTION(2, "nand", "io5"), + MPP_FUNCTION(3, "uart3", "rxd"), + MPP_FUNCTION(4, "uart2", "rxd")), + MPP_MODE(6, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d6"), + MPP_FUNCTION(2, "nand", "io0"), + MPP_FUNCTION(3, "i2c1", "sck")), + MPP_MODE(7, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d7"), + MPP_FUNCTION(2, "nand", "io1"), + MPP_FUNCTION(3, "i2c1", "sda")), + MPP_MODE(8, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "clk"), + MPP_FUNCTION(2, "nand", "wen")), + MPP_MODE(9, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "cmd"), + MPP_FUNCTION(2, "nand", "ale")), + MPP_MODE(10, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "ds"), + MPP_FUNCTION(2, "nand", "cle")), + MPP_MODE(11, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "rst"), + MPP_FUNCTION(2, "nand", "cen")), + MPP_MODE(12, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "spi0", "clk")), + MPP_MODE(13, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "spi0", "csn")), + MPP_MODE(14, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "spi0", "mosi")), + MPP_MODE(15, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "spi0", "miso")), + MPP_MODE(16, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "spi0", "wpn"), + MPP_FUNCTION(2, "nand", "ren"), + MPP_FUNCTION(3, "uart1", "txd")), + MPP_MODE(17, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "spi0", "hold"), + MPP_FUNCTION(2, "nand", "rb"), + MPP_FUNCTION(3, "uart1", "rxd")), + MPP_MODE(18, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(2, "uart2", "rxd")), + MPP_MODE(19, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(2, "uart2", "txd")), + MPP_MODE(20, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(2, "i2c1", "sck"), + MPP_FUNCTION(3, "spi1", "clk"), + MPP_FUNCTION(4, "uart3", "txd")), + MPP_MODE(21, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(2, "i2c1", "sda"), + MPP_FUNCTION(3, "spi1", "csn"), + MPP_FUNCTION(4, "uart3", "rxd")), + MPP_MODE(22, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(3, "spi1", "mosi")), + MPP_MODE(23, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(3, "spi1", "miso")), + MPP_MODE(24, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(2, "uart2", "txd")), + MPP_MODE(25, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(2, "uart2", "rxd")), + MPP_MODE(26, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "i2c0", "sck"), + MPP_FUNCTION(3, "uart3", "txd")), + MPP_MODE(27, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "i2c0", "sda"), + MPP_FUNCTION(3, "uart3", "rxd")), + MPP_MODE(28, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(3, "uart3", "txd")), + MPP_MODE(29, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(3, "uart3", "rxd")), + MPP_MODE(30, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(31, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(32, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "uart0", "txd")), + MPP_MODE(33, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "uart0", "rxd")), + MPP_MODE(34, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(2, "uart3", "rxd")), + MPP_MODE(35, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(2, "uart3", "txd")), + MPP_MODE(36, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(37, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(38, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(39, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(40, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(41, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(4, "uart2", "txd"), + MPP_FUNCTION(5, "i2c1", "sck")), + MPP_MODE(42, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(4, "uart2", "rxd"), + MPP_FUNCTION(5, "i2c1", "sda")), + MPP_MODE(43, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(44, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(45, + MPP_FUNCTION(0, "gpio", NULL)), +}; + +static struct mvebu_pinctrl_soc_info ac5_pinctrl_info; + +static const struct of_device_id ac5_pinctrl_of_match[] = { + { + .compatible = "marvell,ac5-pinctrl", + }, + { }, +}; + +static const struct mvebu_mpp_ctrl ac5_mpp_controls[] = { + MPP_FUNC_CTRL(0, 45, NULL, mvebu_regmap_mpp_ctrl), }; + +static struct pinctrl_gpio_range ac5_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 46), }; + +static int ac5_pinctrl_probe(struct platform_device *pdev) +{ + struct mvebu_pinctrl_soc_info *soc = &ac5_pinctrl_info; + const struct of_device_id *match = + of_match_device(ac5_pinctrl_of_match, &pdev->dev); + + if (!match || !pdev->dev.parent) + return -ENODEV; + + soc->variant = 0; /* no variants for ac5 */ + soc->controls = ac5_mpp_controls; + soc->ncontrols = ARRAY_SIZE(ac5_mpp_controls); + soc->gpioranges = ac5_mpp_gpio_ranges; + soc->ngpioranges = ARRAY_SIZE(ac5_mpp_gpio_ranges); + soc->modes = ac5_mpp_modes; + soc->nmodes = ac5_mpp_controls[0].npins; + + pdev->dev.platform_data = soc; + + return mvebu_pinctrl_simple_regmap_probe(pdev, pdev->dev.parent, 0); +} + +static struct platform_driver ac5_pinctrl_driver = { + .driver = { + .name = "ac5-pinctrl", + .of_match_table = of_match_ptr(ac5_pinctrl_of_match), + }, + .probe = ac5_pinctrl_probe, +}; + +builtin_platform_driver(ac5_pinctrl_driver); From patchwork Mon Mar 14 21:31:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org 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From: Chris Packham To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org, davem@davemloft.net, kuba@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, adrian.hunter@intel.com, thomas.petazzoni@bootlin.com, kostap@marvell.com, robert.marko@sartura.hr Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 5/8] net: mvneta: Add support for 98DX2530 Ethernet port Date: Tue, 15 Mar 2022 10:31:40 +1300 Message-Id: <20220314213143.2404162-6-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> References: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=LxpfyEy1a6e1ozZBTSYA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The 98DX2530 SoC is similar to the Armada 3700 except it needs a different MBUS window configuration. Add a new compatible string to identify this device and the required MBUS window configuration. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- Notes: Changes in v2: - New drivers/net/ethernet/marvell/mvneta.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 83c8908f0cc7..000929794266 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -76,6 +76,8 @@ #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) #define MVNETA_BASE_ADDR_ENABLE 0x2290 +#define MVNETA_AC5_CNM_DDR_TARGET 0x2 +#define MVNETA_AC5_CNM_DDR_ATTR 0xb #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 #define MVNETA_PORT_CONFIG 0x2400 #define MVNETA_UNI_PROMISC_MODE BIT(0) @@ -544,6 +546,7 @@ struct mvneta_port { /* Flags for special SoC configurations */ bool neta_armada3700; + bool neta_ac5; u16 rx_offset_correction; const struct mbus_dram_target_info *dram_target_info; }; @@ -5272,6 +5275,10 @@ static void mvneta_conf_mbus_windows(struct mvneta_port *pp, win_protect |= 3 << (2 * i); } } else { + if (pp->neta_ac5) + mvreg_write(pp, MVNETA_WIN_BASE(0), + (MVNETA_AC5_CNM_DDR_ATTR << 8) | + MVNETA_AC5_CNM_DDR_TARGET); /* For Armada3700 open default 4GB Mbus window, leaving * arbitration of target/attribute to a different layer * of configuration. @@ -5397,6 +5404,11 @@ static int mvneta_probe(struct platform_device *pdev) /* Get special SoC configurations */ if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) pp->neta_armada3700 = true; + if (of_device_is_compatible(dn, "marvell,armada-ac5-neta")) { + pp->neta_armada3700 = true; + pp->neta_ac5 = true; + } + pp->clk = devm_clk_get(&pdev->dev, "core"); if (IS_ERR(pp->clk)) @@ -5720,6 +5732,7 @@ static const struct of_device_id mvneta_match[] = { { .compatible = "marvell,armada-370-neta" }, { .compatible = "marvell,armada-xp-neta" }, { .compatible = "marvell,armada-3700-neta" }, + { .compatible = "marvell,armada-ac5-neta" }, { } }; MODULE_DEVICE_TABLE(of, mvneta_match); From patchwork Mon Mar 14 21:31:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD6CEC433FE for ; Mon, 14 Mar 2022 21:32:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245364AbiCNVd6 (ORCPT ); Mon, 14 Mar 2022 17:33:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245311AbiCNVd2 (ORCPT ); Mon, 14 Mar 2022 17:33:28 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82DE433E23 for ; Mon, 14 Mar 2022 14:32:16 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 2B4702C0C56; Mon, 14 Mar 2022 21:32:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647293528; bh=r53xBPP6Mh8fbb8zLoRBgxJf+LBKckfcKs/6WIKmI5A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GfVydy+OGGWpxxtgdGBOJOvBgOccqaPNxQRRoRhJxoTBO6FM9ec16PomdZG/NgMTV PNeoOjPTWW/cpBXXd/ihwao+Pc86mjEz5Ia7OzOGwaedEEqWIcK9se6lqaPxtysJPJ 9AZuVXiRihtwt17bjtkQC4jVgZpcEU7vRfvgYJBPIrC44YjImIko8xR6bHhRwrQZyw 3LsD8cBmeR2cQHFsFP3SG8ZBjWfUJN6ulB1EKXnP2vAtysXdhBpOLWO7ffJvX8fCQJ XGGk4DAL2ZlpFP/tO55i+QQQO/Qz9I/1q6fFzNCwcw8Rf3+P3WRqNtnN9lwiURNhZn P7VZEuyiAe8wA== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 15 Mar 2022 10:32:07 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 1733313EEAD; Tue, 15 Mar 2022 10:32:07 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id F21682A2678; Tue, 15 Mar 2022 10:32:03 +1300 (NZDT) From: Chris Packham To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org, davem@davemloft.net, kuba@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, adrian.hunter@intel.com, thomas.petazzoni@bootlin.com, kostap@marvell.com, robert.marko@sartura.hr Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 6/8] mmc: xenon: add AC5 compatible string Date: Tue, 15 Mar 2022 10:31:41 +1300 Message-Id: <20220314213143.2404162-7-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> References: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=UvibhkeALEyMK9IFLgoA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add marvell,ac5-sdhci to the list of compatible strings for the Xenon SDHCI controller. Currently this is functionally no different to the ap806 but having the compatible string will allow handling any differences that arise from the controller being integrated in the 98DX2530 switch chips. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- Notes: Changes in v2: - New drivers/mmc/host/sdhci-xenon.c | 1 + drivers/mmc/host/sdhci-xenon.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c index 666cee4c7f7c..ac95d16809c5 100644 --- a/drivers/mmc/host/sdhci-xenon.c +++ b/drivers/mmc/host/sdhci-xenon.c @@ -692,6 +692,7 @@ static const struct of_device_id sdhci_xenon_dt_ids[] = { { .compatible = "marvell,armada-ap807-sdhci", .data = (void *)XENON_AP807}, { .compatible = "marvell,armada-cp110-sdhci", .data = (void *)XENON_CP110}, { .compatible = "marvell,armada-3700-sdhci", .data = (void *)XENON_A3700}, + { .compatible = "marvell,ac5-sdhci", .data = (void *)XENON_AC5}, {} }; MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids); diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h index 3e9c6c908a79..451b41dd3447 100644 --- a/drivers/mmc/host/sdhci-xenon.h +++ b/drivers/mmc/host/sdhci-xenon.h @@ -57,7 +57,8 @@ enum xenon_variant { XENON_A3700, XENON_AP806, XENON_AP807, - XENON_CP110 + XENON_CP110, + XENON_AC5, }; struct xenon_priv { From patchwork Mon Mar 14 21:31:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1324C433EF for ; Mon, 14 Mar 2022 21:32:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245387AbiCNVeA (ORCPT ); Mon, 14 Mar 2022 17:34:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245352AbiCNVd6 (ORCPT ); Mon, 14 Mar 2022 17:33:58 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE7EF33E33 for ; Mon, 14 Mar 2022 14:32:16 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 34FF72C0C59; Mon, 14 Mar 2022 21:32:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647293528; bh=HMSC7+viBhpiZH0ubKqMcCUMFi+bu1zmSMjwuNE05Oc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o8VoBqSsTdh5zDX0cOW/F4rs6O3McBr6/cY1Nk8jnt56gV8+HkLD89AhS5YqX16ch Y1UEdPXCZqT29vj/X7+0KeyGucwGgQ54QEBN1j84pMIaXQ4CTHJXvCIZpmMgCCh+UM fkRVNAo8eTJP1WSqlAWBpWjl0Jke0UFmyxf9zfTVDjEkzVq0XqLgG0It7Gy/jxcgBI NCqsCzpnRWXZ+O3WJ5eTfyZqpWF987LQ2GjbShciF1uM2UWJ7Ay203rFq2bqPYiC9o AjbiMkXjQyxWb0eHA/Th871J9Vqf1sa2wridj/ET6q1IE8SBWHc+m2ypIenTLu/oV9 9hfyY0MqKtQUw== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 15 Mar 2022 10:32:07 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 1A50D13EEAE; Tue, 15 Mar 2022 10:32:07 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 012B02A2678; Tue, 15 Mar 2022 10:32:03 +1300 (NZDT) From: Chris Packham To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org, davem@davemloft.net, kuba@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, adrian.hunter@intel.com, thomas.petazzoni@bootlin.com, kostap@marvell.com, robert.marko@sartura.hr Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 7/8] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Date: Tue, 15 Mar 2022 10:31:42 +1300 Message-Id: <20220314213143.2404162-8-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> References: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=sHAJOpqgVnCWuCwbjzwA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The 98DX2530 SoC is the Control and Management CPU integrated into the Marvell 98DX25xx and 98DX35xx series of switch chip (internally referred to as AlleyCat5 and AlleyCat5X). These files have been taken from the Marvell SDK and lightly cleaned up with the License and copyright retained. Signed-off-by: Chris Packham --- Notes: The Marvell SDK has a number of new compatible strings. I've brought through some of the drivers or where possible used an in-tree alternative (e.g. there is SDK code for a ac5-gpio but the existing marvell,armada-8k-gpio seems to cover what is needed if you use an appropriate binding). I expect that there will a new series of patches when I get some different hardware (or additions to this series depending on if/when it lands). Changes in v2: - Make pinctrl a child node of a syscon node - Use marvell,armada-8k-gpio instead of orion-gpio - Remove nand peripheral. The Marvell SDK does have some changes for the ac5-nand-controller but I currently lack hardware with NAND fitted so I can't test it right now. I've therefore chosen to omit the node and not attempted to bring in the driver or binding. - Remove pcie peripheral. Again there are changes in the SDK and I have no way of testing them. - Remove prestera node. - Remove "marvell,ac5-ehci" compatible from USB node as "marvell,orion-ehci" is sufficient - Remove watchdog node. There is a buggy driver for the ac5 watchdog in the SDK but it needs some work so I've dropped the node for now. arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-98dx2530.dtsi | 343 ++++++++++++++++++ arch/arm64/boot/dts/marvell/rd-ac5x.dts | 62 ++++ 3 files changed, 406 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi create mode 100644 arch/arm64/boot/dts/marvell/rd-ac5x.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 1c794cdcb8e6..3905dee558b4 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb +dtb-$(CONFIG_ARCH_MVEBU) += rd-ac5x.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi new file mode 100644 index 000000000000..ebe464b9ebd2 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5. + * + * Copyright (C) 2021 Marvell + * + */ + +/dts-v1/; + +#include +#include + +/ { + model = "Marvell AC5 SoC"; + compatible = "marvell,ac5", "marvell,armada3700"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + spiflash0 = &spiflash0; + gpio0 = &gpio0; + gpio1 = &gpio1; + ethernet0 = ð0; + ethernet1 = ð1; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <25000000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + internal-regs@7f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + /* 16M internal register @ 0x7f00_0000 */ + ranges = <0x0 0x0 0x7f000000 0x1000000>; + dma-coherent; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clock-frequency = <328000000>; + status = "okay"; + }; + + mdio: mdio@20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x22004 0x4>; + clocks = <&core_clock>; + }; + + i2c0: i2c@11000{ + compatible = "marvell,mv78230-i2c"; + reg = <0x11000 0x20>; + + clocks = <&core_clock>; + clock-names = "core"; + interrupts = ; + clock-frequency=<100000>; + status="okay"; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio>; + scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; + }; + + i2c1: i2c@11100{ + compatible = "marvell,mv78230-i2c"; + reg = <0x11100 0x20>; + + clocks = <&core_clock>; + clock-names = "core"; + interrupts = ; + clock-frequency=<100000>; + status="okay"; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_gpio>; + scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; + sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; + + system-controller@18000 { + compatible = "syscon", "simple-mfd"; + reg = <0x18000 0x200>; + + gpio0: gpio@100 { + compatible = "marvell,armada-8k-gpio"; + offset = <0x100>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl0 0 0 32>; + #pwm-cells = <2>; + }; + + gpio1: gpio@140 { + compatible = "marvell,armada-8k-gpio"; + offset = <0x140>; + ngpios = <14>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl0 0 32 14>; + #pwm-cells = <2>; + }; + }; + }; + + mmc_dma: mmc-dma-peripherals@80500000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + dma-coherent; + + sdhci0: sdhci@805c0000 { + compatible = "marvell,ac5-sdhci", + "marvell,armada-ap806-sdhci"; + reg = <0x0 0x805c0000 0x0 0x300>; + reg-names = "ctrl", "decoder"; + interrupts = ; + clocks = <&core_clock>; + clock-names = "core"; + status = "okay"; + bus-width = <8>; + /*marvell,xenon-phy-slow-mode;*/ + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + }; + + /* + * Dedicated section for devices behind 32bit controllers so we + * can configure specific DMA mapping for them + */ + behind-32bit-controller@7f000000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; + /* Host phy ram starts at 0x200M */ + dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>; + dma-coherent; + + eth0: ethernet@20000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x20000 0x0 0x4000>; + interrupts = ; + clocks = <&core_clock>; + status = "disabled"; + phy-mode = "sgmii"; + }; + + eth1: ethernet@24000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x24000 0x0 0x4000>; + interrupts = ; + clocks = <&core_clock>; + status = "disabled"; + phy-mode = "sgmii"; + }; + + /* A dummy entry used for chipidea phy init */ + usb1phy: usbphy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + /* USB0 is a host USB */ + usb0: usb@80000 { + compatible = "marvell,orion-ehci"; + reg = <0x0 0x80000 0x0 0x500>; + interrupts = ; + status = "okay"; + }; + + /* USB1 is a peripheral USB */ + usb1: usb@a0000 { + reg = <0x0 0xa0000 0x0 0x500>; + interrupts = ; + status = "okay"; + }; + }; + + system-controller@80020100 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x80020100 0 0x20>; + + pinctrl0: pinctrl@80020100 { + compatible = "marvell,ac5-pinctrl"; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c0"; + }; + + i2c0_gpio: i2c0-gpio-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + + i2c1_pins: i2c1-pins { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "i2c1"; + }; + + i2c1_gpio: i2c1-gpio-pins { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "i2c1"; + }; + }; + }; + + core_clock: core_clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + + axi_clock: axi_clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <325000000>; + }; + + spi_clock: spi_clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + spi0: spi@805a0000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a0000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = ; + num-cs = <1>; + status = "disabled"; + }; + + spi@805a8000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a8000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = ; + num-cs = <1>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@80600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + /*#redistributor-regions = <1>;*/ + redistributor-stride = <0x0 0x20000>; // 128kB stride + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ + <0x0 0x80660000 0x0 0x40000>; /* GICR */ + interrupts = ; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x2 0x00000000 0x0 0x40000000>; + // linux,usable-memory = <0x2 0x00000000 0x0 0x80000000>; + }; + +}; diff --git a/arch/arm64/boot/dts/marvell/rd-ac5x.dts b/arch/arm64/boot/dts/marvell/rd-ac5x.dts new file mode 100644 index 000000000000..013cf7bd913a --- /dev/null +++ b/arch/arm64/boot/dts/marvell/rd-ac5x.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5X. + * + * Copyright (C) 2021 Marvell + * + */ +/* + * Device Tree file for Marvell Alleycat 5X development board + * This board file supports the B configuration of the board + */ + +#include "armada-98dx2530.dtsi" + +&mdio { + phy0: ethernet-phy@0 { + reg = <0 0>; + }; +}; + +ð0 { + status = "okay"; + phy = <&phy0>; +}; + +&spi0 { + status = "okay"; + + spiflash0: spi-flash@0 { + compatible = "spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "spi_flash_part0"; + reg = <0x0 0x800000>; + }; + + parition@1 { + label = "spi_flash_part1"; + reg = <0x800000 0x700000>; + }; + + parition@2 { + label = "spi_flash_part2"; + reg = <0xF00000 0x100000>; + }; + }; +}; + +&usb1 { + compatible = "chipidea,usb2"; + phys = <&usb1phy>; + phy-names = "usb-phy"; + dr_mode = "peripheral"; +}; + From patchwork Mon Mar 14 21:31:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96A54C433EF for ; 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d=alliedtelesis.co.nz; s=mail181024; t=1647293528; bh=CCslJI4Upt9ti4sTFV0dF2UZUVjFxXqK24Ghz+BqxaM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KG9fXNXlKNU+snjweKpKj3+rkFkFLy5sEzLpwJKppiUh9KDfKiQ9BWNXy+7c8798A pbbSgP6ErCgJ/U4HzZtVi5oFmFdXrBggmuYeqbedgtzjnxpOqin8pBYR3cJ5d+7zpR gEqXuhDJBMek7iQRpvbo3v2/dXrTr48FQLpFePVO/KCLS7+vZoHBm2NranximxGMiV nPpVgoxTUyiXUyygU0H+tH2zcLXpFFwcyQ8Ktt2sTAOwakCMJwZXIYfxdLqAmFiRRY H1otMOk4Ox1s6XRWJnWEYQfCOjGS38xfQWRunvGqTWNSg9ROlTxlmY8ZllG70auv3J 7QzYDPiu/7u2w== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 15 Mar 2022 10:32:07 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 1DA3313EE36; Tue, 15 Mar 2022 10:32:07 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 0458E2A2678; Tue, 15 Mar 2022 10:32:04 +1300 (NZDT) From: Chris Packham To: huziji@marvell.com, ulf.hansson@linaro.org, robh+dt@kernel.org, davem@davemloft.net, kuba@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, adrian.hunter@intel.com, thomas.petazzoni@bootlin.com, kostap@marvell.com, robert.marko@sartura.hr Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 8/8] arm64: marvell: enable the 98DX2530 pinctrl driver Date: Tue, 15 Mar 2022 10:31:43 +1300 Message-Id: <20220314213143.2404162-9-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> References: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=XQcNo-tEeLJW46c85tUA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This commit makes sure the drivers for the 98DX2530 pin controller is enabled. Signed-off-by: Chris Packham --- Notes: Changes in v2: - None arch/arm64/Kconfig.platforms | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 21697449d762..6bbb56901794 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -183,11 +183,13 @@ config ARCH_MVEBU select PINCTRL_ARMADA_37XX select PINCTRL_ARMADA_AP806 select PINCTRL_ARMADA_CP110 + select PINCTRL_AC5 help This enables support for Marvell EBU familly, including: - Armada 3700 SoC Family - Armada 7K SoC Family - Armada 8K SoC Family + - 98DX2530 SoC Family config ARCH_MXC bool "ARMv8 based NXP i.MX SoC family"