From patchwork Wed Mar 16 06:07:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 551933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E2B9C433FE for ; Wed, 16 Mar 2022 06:07:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353819AbiCPGJI (ORCPT ); Wed, 16 Mar 2022 02:09:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353781AbiCPGI6 (ORCPT ); Wed, 16 Mar 2022 02:08:58 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D4AC60AAC; Tue, 15 Mar 2022 23:07:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647410866; x=1678946866; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=cZrDloP/7lXSlRe8nV2apCerDfz4MdbPHsS6uRLzOPo=; b=eDFdGPR1fJfC+ZVDvA1T3PCiIBMRcBJdf7+S6fntVslqbd/3OlXblbws sw2e4wLPr1G1L5HLpuueMPsDjkuJHhWH9/amA22iLuWjHbgOk8kUTDPQP uc9uCq4WLbS8ofHvDkE7C+LgwTj2JpO159kIXE5PuoDobl4pMZyze7Uq6 0=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 15 Mar 2022 23:07:45 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Mar 2022 23:07:43 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:37:22 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 12D654794; Wed, 16 Mar 2022 11:37:21 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, linus.walleij@linaro.org, robh+dt@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, rnayak@codeaurora.org, collinsd@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 2/6] regulator: qcom-rpmh: Add support for SDX65 Date: Wed, 16 Mar 2022 11:37:13 +0530 Message-Id: <1647410837-22537-3-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647410837-22537-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647410837-22537-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support from RPMH regulators found in SDX65 platform. Signed-off-by: Rohit Agarwal --- drivers/regulator/qcom-rpmh-regulator.c | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/regulator/qcom-rpmh-regulator.c b/drivers/regulator/qcom-rpmh-regulator.c index a3bc0eb..561de6b 100644 --- a/drivers/regulator/qcom-rpmh-regulator.c +++ b/drivers/regulator/qcom-rpmh-regulator.c @@ -1121,6 +1121,39 @@ static const struct rpmh_vreg_init_data pmx55_vreg_data[] = { {} }; +static const struct rpmh_vreg_init_data pmx65_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps510, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_hfsmps510, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"), + RPMH_VREG("smps7", "smp%s7", &pmic5_hfsmps510, "vdd-s7"), + RPMH_VREG("smps8", "smp%s8", &pmic5_hfsmps510, "vdd-s8"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2-l18"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"), + RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4"), + RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6-l16"), + RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6-l16"), + RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo, "vdd-l7"), + RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l8-l9"), + RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l8-l9"), + RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l10"), + RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l11-l13"), + RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo, "vdd-l12"), + RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l11-l13"), + RPMH_VREG("ldo14", "ldo%s14", &pmic5_nldo, "vdd-l14"), + RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo, "vdd-l15"), + RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l6-l16"), + RPMH_VREG("ldo17", "ldo%s17", &pmic5_nldo, "vdd-l17"), + /* ldo18 not configured */ + RPMH_VREG("ldo19", "ldo%s19", &pmic5_nldo, "vdd-l19"), + RPMH_VREG("ldo20", "ldo%s20", &pmic5_nldo, "vdd-l20"), + RPMH_VREG("ldo21", "ldo%s21", &pmic5_nldo, "vdd-l21"), + {} +}; + static const struct rpmh_vreg_init_data pm7325_vreg_data[] = { RPMH_VREG("smps1", "smp%s1", &pmic5_hfsmps510, "vdd-s1"), RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps520, "vdd-s2"), @@ -1277,6 +1310,10 @@ static const struct of_device_id __maybe_unused rpmh_regulator_match_table[] = { .data = pmx55_vreg_data, }, { + .compatible = "qcom,pmx65-rpmh-regulators", + .data = pmx65_vreg_data, + }, + { .compatible = "qcom,pm7325-rpmh-regulators", .data = pm7325_vreg_data, }, From patchwork Wed Mar 16 06:17:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 551930 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22B64C4321E for ; Wed, 16 Mar 2022 06:18:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353909AbiCPGTS (ORCPT ); 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15 Mar 2022 23:17:50 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:47:36 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 9A6B34791; Wed, 16 Mar 2022 11:47:35 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 3/6] ARM: dts: qcom: sdx65-mtp: Add pmx65 pmic Date: Wed, 16 Mar 2022 11:47:24 +0530 Message-Id: <1647411447-25249-4-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SDX65-mtp features PMX65 pmic, so include the dts as well. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 9fa251a..408d30e 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -7,6 +7,7 @@ #include "qcom-sdx65.dtsi" #include #include +#include "qcom-pmx65.dtsi" / { model = "Qualcomm Technologies, Inc. SDX65 MTP"; From patchwork Wed Mar 16 06:17:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 551931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86BF8C433EF for ; Wed, 16 Mar 2022 06:18:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353891AbiCPGTP (ORCPT ); Wed, 16 Mar 2022 02:19:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353871AbiCPGTH (ORCPT ); Wed, 16 Mar 2022 02:19:07 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC2A6E97; Tue, 15 Mar 2022 23:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647411470; x=1678947470; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=GUK4JIE654NZxV1pFo5SaB16H7zXCfmo7RTrkPYh/S0=; b=dP1FW+AlJ3T0n9Q7JUc8gnMYGyZC9v58iKFX6dFSbdOqj1PZD45qFfdx CqfEnJuEdKZ4KaObjcDbElRIeTRQqNUV74VwEqKKkM6GiHEIaidZJHBOy LygJiGRf1XB1ooSL4yGc4rRy8IWYfkpNuyEOAPYhEx7t+0j6Morfu8ZzR M=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 15 Mar 2022 23:17:50 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Mar 2022 23:17:48 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 16 Mar 2022 11:47:37 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 8CB5F478E; Wed, 16 Mar 2022 11:47:36 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 5/6] ARM: dts: qcom: Add PMIC pmx65 dts Date: Wed, 16 Mar 2022 11:47:26 +0530 Message-Id: <1647411447-25249-6-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> References: <1647411447-25249-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DTS for PMIC PMX65 found in Qualcomm platforms. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-pmx65.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-pmx65.dtsi diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi new file mode 100644 index 0000000..5411b83 --- /dev/null +++ b/arch/arm/boot/dts/qcom-pmx65.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + pmic@1 { + compatible = "qcom,pmx65", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmx65_temp: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmx65_gpios: pinctrl@8800 { + compatible = "qcom,pmx65-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +};