From patchwork Wed Mar 16 15:13:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 552818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30893C4332F for ; Wed, 16 Mar 2022 15:13:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353905AbiCPPPF (ORCPT ); Wed, 16 Mar 2022 11:15:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357125AbiCPPOt (ORCPT ); Wed, 16 Mar 2022 11:14:49 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65751403FA; Wed, 16 Mar 2022 08:13:34 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 2445C1F44671 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647443613; bh=VWVdyhf+kOwqwxWog/5n8WYiI9hoA0DQJolpHjf/k6A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KmJJGQDgz8NfiPUmBh5lnKP2WxK8Xyx1GwbYIoCQx1XE/AQbHUsygFjoDMh8HJcJX VHO84PlMXXMG7KJLaBoTpRDCKbzoVd5GLX25qqPvgwQUP/vc+vvweQToeHfqQgalJZ QwWtMSyB/YuWGIha3161V0JVVZRStw/cW3tTq+6J12z7XFTR1otcxhrZXZXcP60p2I AykDLBVcD9hTxEKL4mZGJ53xqsCvVz3vMC8wPcUTXIP6k7AJd4aKFmTUHrmqiPegrR qBgVfOD8c5f23jSSmBJD0u/a9dyyJ5JExkuVgakgOPwu2DjBaRI1Hk2uayHPA1Ov8x d0qH0ZLrR6OSQ== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 01/10] arm64: dts: mediatek: Introduce MT8192-based Asurada board family Date: Wed, 16 Mar 2022 11:13:18 -0400 Message-Id: <20220316151327.564214-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316151327.564214-1-nfraprado@collabora.com> References: <20220316151327.564214-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce the MT8192 Asurada Chromebook platform, including the Asurada Spherion and Asurada Hayato boards. This is enough configuration to get serial output working on Spherion and Hayato. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 2 ++ .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 11 ++++++++ .../mediatek/mt8192-asurada-spherion-r0.dts | 13 ++++++++++ .../boot/dts/mediatek/mt8192-asurada.dtsi | 26 +++++++++++++++++++ 4 files changed, 52 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 8c1e18032f9f..034cba17276b 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -37,5 +37,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts new file mode 100644 index 000000000000..e18e14b13d61 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Google LLC + */ +/dts-v1/; +#include "mt8192-asurada.dtsi" + +/ { + model = "MediaTek Hayato rev1"; + compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts new file mode 100644 index 000000000000..b5372ce6bd95 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ +/dts-v1/; +#include "mt8192-asurada.dtsi" + +/ { + model = "MediaTek Spherion (rev0 - 3)"; + compatible = "google,spherion-rev3", "google,spherion-rev2", + "google,spherion-rev1", "google,spherion-rev0", + "google,spherion", "mediatek,mt8192"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi new file mode 100644 index 000000000000..277bd38943fe --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang + */ +/dts-v1/; +#include "mt8192.dtsi" + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; From patchwork Wed Mar 16 15:13:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 551956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67F07C433FE for ; Wed, 16 Mar 2022 15:13:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240466AbiCPPPE (ORCPT ); Wed, 16 Mar 2022 11:15:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357096AbiCPPOx (ORCPT ); Wed, 16 Mar 2022 11:14:53 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A90831511; Wed, 16 Mar 2022 08:13:35 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 742F01F4466C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647443614; bh=73T++O+sVkacU4ezH/NiQ+RPX96Kc4UTdJpge0w1oUc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K8xv51AkPzaaqrsLUi79gX/sGO8573lhhu6mIJPPvjiT0ZAJ+fBFL3Mauc4GXINpn KCyQwKopdWRJn2oONF4qwg9RuYMrFs7ijIBwk0GM6xMuTKn1dSwHfWIobPzZ65ByH4 7dRUECr4C2vCvrGlnKLD+cx2EOlkumftlehbWBhGsenz0JVflcB35QkN3YnVyaG+hC KI9mvVxP7KEAjR1sDHpi4vWHW6ThcYJqCQklJWRcIX3T9AD+QUmQWfLQ/uGoDCau4N 9GACDa8tzWsrNsyEiWBqKjkV11e2WxN5ZSBXou0+kLFhMVItfivtQpihCiLC9I5Lbg QtAwriJ2WEkGg== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 02/10] arm64: dts: mediatek: asurada: Document GPIO names Date: Wed, 16 Mar 2022 11:13:19 -0400 Message-Id: <20220316151327.564214-3-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316151327.564214-1-nfraprado@collabora.com> References: <20220316151327.564214-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the gpio-line-names property to gpio-controller in order to document the usage of GPIOs on the Asurada platform. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 228 ++++++++++++++++++ 1 file changed, 228 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 277bd38943fe..e10636298639 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -21,6 +21,234 @@ memory@40000000 { }; }; +&pio { + /* 220 lines */ + gpio-line-names = "I2S_DP_LRCK", + "IS_DP_BCLK", + "I2S_DP_MCLK", + "I2S_DP_DATAOUT", + "SAR0_INT_ODL", + "EC_AP_INT_ODL", + "EDPBRDG_INT_ODL", + "DPBRDG_INT_ODL", + "DPBRDG_PWREN", + "DPBRDG_RST_ODL", + "I2S_HP_MCLK", + "I2S_HP_BCK", + "I2S_HP_LRCK", + "I2S_HP_DATAIN", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it AP_FLASH_WP_ODL. + */ + "AP_FLASH_WP_L", + "TRACKPAD_INT_ODL", + "EC_AP_HPD_OD", + "SD_CD_ODL", + "HP_INT_ODL_ALC", + "EN_PP1000_DPBRDG", + "AP_GPIO20", + "TOUCH_INT_L_1V8", + "UART_BT_WAKE_ODL", + "AP_GPIO23", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_CLK", + "EN_PP3300_DPBRDG_DX", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_MISO", + "I2S_HP_DATAOUT", + "AP_GPIO30", + "I2S_SPKR_MCLK", + "I2S_SPKR_BCLK", + "I2S_SPKR_LRCK", + "I2S_SPKR_DATAIN", + "I2S_SPKR_DATAOUT", + "AP_SPI_H1_TPM_CLK", + "AP_SPI_H1_TPM_CS_L", + "AP_SPI_H1_TPM_MISO", + "AP_SPI_H1_TPM_MOSI", + "BL_PWM", + "EDPBRDG_PWREN", + "EDPBRDG_RST_ODL", + "EN_PP3300_HUB", + "HUB_RST_L", + "", + "", + "", + "", + "", + "", + "SD_CLK", + "SD_CMD", + "SD_DATA3", + "SD_DATA0", + "SD_DATA2", + "SD_DATA1", + "", + "", + "", + "", + "", + "", + "PCIE_WAKE_ODL", + "PCIE_RST_L", + "PCIE_CLKREQ_ODL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SPMI_SCL", + "SPMI_SDA", + "AP_GOOD", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "UART_AP_TX_BT_RX", + "UART_BT_TX_AP_RX", + "MIPI_DPI_D0_R", + "MIPI_DPI_D1_R", + "MIPI_DPI_D2_R", + "MIPI_DPI_D3_R", + "MIPI_DPI_D4_R", + "MIPI_DPI_D5_R", + "MIPI_DPI_D6_R", + "MIPI_DPI_D7_R", + "MIPI_DPI_D8_R", + "MIPI_DPI_D9_R", + "MIPI_DPI_D10_R", + "", + "", + "MIPI_DPI_DE_R", + "MIPI_DPI_D11_R", + "MIPI_DPI_VSYNC_R", + "MIPI_DPI_CLK_R", + "MIPI_DPI_HSYNC_R", + "PCM_BT_DATAIN", + "PCM_BT_SYNC", + "PCM_BT_DATAOUT", + "PCM_BT_CLK", + "AP_I2C_AUDIO_SCL", + "AP_I2C_AUDIO_SDA", + "SCP_I2C_SCL", + "SCP_I2C_SDA", + "AP_I2C_WLAN_SCL", + "AP_I2C_WLAN_SDA", + "AP_I2C_DPBRDG_SCL", + "AP_I2C_DPBRDG_SDA", + "EN_PP1800_DPBRDG_DX", + "EN_PP3300_EDP_DX", + "EN_PP1800_EDPBRDG_DX", + "EN_PP1000_EDPBRDG", + "SCP_JTAG0_TDO", + "SCP_JTAG0_TDI", + "SCP_JTAG0_TMS", + "SCP_JTAG0_TCK", + "SCP_JTAG0_TRSTN", + "EN_PP3000_VMC_PMU", + "EN_PP3300_DISPLAY_DX", + "TOUCH_RST_L_1V8", + "TOUCH_REPORT_DISABLE", + "", + "", + "AP_I2C_TRACKPAD_SCL_1V8", + "AP_I2C_TRACKPAD_SDA_1V8", + "EN_PP3300_WLAN", + "BT_KILL_L", + "WIFI_KILL_L", + "SET_VMC_VOLT_AT_1V8", + "EN_SPK", + "AP_WARM_RST_REQ", + "", + "", + "EN_PP3000_SD_S3", + "AP_EDP_BKLTEN", + "", + "", + "", + "AP_SPI_EC_CLK", + "AP_SPI_EC_CS_L", + "AP_SPI_EC_MISO", + "AP_SPI_EC_MOSI", + "AP_I2C_EDPBRDG_SCL", + "AP_I2C_EDPBRDG_SDA", + "MT6315_PROC_INT", + "MT6315_GPU_INT", + "UART_SERVO_TX_SCP_RX", + "UART_SCP_TX_SERVO_RX", + "BT_RTS_AP_CTS", + "AP_RTS_BT_CTS", + "UART_AP_WAKE_BT_ODL", + "WLAN_ALERT_ODL", + "EC_IN_RW_ODL", + "H1_AP_INT_ODL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MSDC0_CMD", + "MSDC0_DAT0", + "MSDC0_DAT2", + "MSDC0_DAT4", + "MSDC0_DAT6", + "MSDC0_DAT1", + "MSDC0_DAT5", + "MSDC0_DAT7", + "MSDC0_DSL", + "MSDC0_CLK", + "MSDC0_DAT3", + "MSDC0_RST_L", + "SCP_VREQ_VAO", + "AUD_DAT_MOSI2", + "AUD_NLE_MOSI1", + "AUD_NLE_MOSI0", + "AUD_DAT_MISO2", + "AP_I2C_SAR_SDA", + "AP_I2C_SAR_SCL", + "AP_I2C_PWR_SCL", + "AP_I2C_PWR_SDA", + "AP_I2C_TS_SCL_1V8", + "AP_I2C_TS_SDA_1V8", + "SRCLKENA0", + "SRCLKENA1", + "AP_EC_WATCHDOG_L", + "PWRAP_SPI0_MI", + "PWRAP_SPI0_CSN", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_CK", + "AP_RTC_CLK32K", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1"; +}; + &uart0 { status = "okay"; }; From patchwork Wed Mar 16 15:13:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 551955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93B31C433EF for ; Wed, 16 Mar 2022 15:14:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357157AbiCPPPL (ORCPT ); Wed, 16 Mar 2022 11:15:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240433AbiCPPPB (ORCPT ); Wed, 16 Mar 2022 11:15:01 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B69D44771; Wed, 16 Mar 2022 08:13:37 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id C5F061F44681 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647443615; bh=6XdHparrNynql5aI5JDISRsUDYEhB7brv5rqIJfGbOk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LQdSkPXBBpWphzqB2vlbw3lyC7guiYbHqG7S+Fkajzu0NGPBLZnROInbMF1zm/ef3 dD0jPE2IiFpeSOlvQD0Q/AnMe317I8a60t2IUMUfsPRa3m8huuwnoNqyVeVPwW+3IW LuGwM3bfzuuSFAFa6VY/q5jcmHnp93iZiSrS1xAzf2lupNXzVhOkXNL6ilgQ0tNFg/ QdGHdQq03NAkQEfMOJK3pxQbMWBZdpHsEymAi0hoaF8V/S/bm18a46K36l6CL4T+3z 3QVxnJ8OIQ8s5TpKudfVdlQdvvkLJW4xOikvxLq2qEG2wBDXhqpVY7PWMcWtJBCQo7 omarGcoGldLiA== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 03/10] arm64: dts: mediatek: asurada: Add system-wide power supplies Date: Wed, 16 Mar 2022 11:13:20 -0400 Message-Id: <20220316151327.564214-4-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316151327.564214-1-nfraprado@collabora.com> References: <20220316151327.564214-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add system-wide power supplies present on all of the boards in the Asurada family. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index e10636298639..5cb7580a13cf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -19,6 +19,70 @@ memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x80000000>; }; + + /* system wide LDO 1.8V power rail */ + pp1800_ldo_g: pp1800-ldo-g { + compatible = "regulator-fixed"; + regulator-name = "pp1800_ldo_g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pp3300_g>; + }; + + /* system wide switching 3.3V power rail */ + pp3300_g: pp3300-g { + compatible = "regulator-fixed"; + regulator-name = "pp3300_g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide LDO 3.3V power rail */ + pp3300_ldo_z: pp3300-ldo-z { + compatible = "regulator-fixed"; + regulator-name = "pp3300_ldo_z"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* separately switched 3.3V power rail */ + pp3300_u: pp3300-u { + compatible = "regulator-fixed"; + regulator-name = "pp3300_u"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* enable pin wired to GPIO controlled by EC */ + vin-supply = <&pp3300_g>; + }; + + /* system wide switching 5.0V power rail */ + pp5000_a: pp5000-a { + compatible = "regulator-fixed"; + regulator-name = "pp5000_a"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: ppvar-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; }; &pio { From patchwork Wed Mar 16 15:13:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 552817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04731C433EF for ; Wed, 16 Mar 2022 15:14:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237009AbiCPPPP (ORCPT ); Wed, 16 Mar 2022 11:15:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357159AbiCPPPC (ORCPT ); Wed, 16 Mar 2022 11:15:02 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1076845792; Wed, 16 Mar 2022 08:13:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 298211F4467E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647443617; bh=t5bAb94VXfBDVM8bnyfOVDys57n3UV6MaXzdmkwM90Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RynSvKpHpCH/C9/GmIJFRLeCD+h1B58erwCcKUaBI73V7AdzKqYo9Fc6IH6tJAuXm K8vwVs1T3lgiiRe6vl06lF6sWt5G0TNZfVRaI8HNhj00mH5KZZWis4WPXuv4Lqi7Dg 1YmAu8XI4fBnrDO6rMkIUEax//HIMKeDWWX3GoPOY9HIbvsumQxXDTkb6HONA7p71Y 1HQph4mPPUN1bPtz2kIOeKqcLoZba6TgediAI5/LFek38xMhPr3zRwoUX5vqB/j0VZ xqgJG+N1MiHZ4574DAToifvHMvOQwA2gV5Rpg1V1FVD/AlpIA2s0ASc7twa2l1d8bV sSK1K93d39NAw== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 04/10] arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses Date: Wed, 16 Mar 2022 11:13:21 -0400 Message-Id: <20220316151327.564214-5-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316151327.564214-1-nfraprado@collabora.com> References: <20220316151327.564214-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Asurada platform has five I2C controllers and two SPI controllers that are used. In preparation for enabling the devices connected to these controllers, enable and configure their busses. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 130 ++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 5cb7580a13cf..3c5b1e475cf6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -85,6 +85,47 @@ ppvar_sys: ppvar-sys { }; }; +&i2c0 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <400000>; + clock-stretch-ns = <12600>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&i2c7 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; +}; + &pio { /* 220 lines */ gpio-line-names = "I2S_DP_LRCK", @@ -311,6 +352,95 @@ &pio { "AUD_DAT_MOSI1", "AUD_DAT_MISO0", "AUD_DAT_MISO1"; + + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux = , + ; + bias-pull-up; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux = , + ; + bias-pull-up; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = , + ; + bias-pull-up; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <0>; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <7>; + }; + }; + + spi1_pins: spi1-default-pins { + pins-cs-mosi-clk { + pinmux = , + , + ; + bias-disable; + }; + + pins-miso { + pinmux = ; + bias-pull-down; + }; + }; + + spi5_pins: spi5-default-pins { + pins-bus { + pinmux = , + , + , + ; + bias-disable; + }; + }; +}; + +&spi1 { + status = "okay"; + + mediatek,pad-select = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&spi5 { + status = "okay"; + + cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; + mediatek,pad-select = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_pins>; }; &uart0 { From patchwork Wed Mar 16 15:13:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 552816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB09BC433EF for ; Wed, 16 Mar 2022 15:14:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238324AbiCPPPX (ORCPT ); Wed, 16 Mar 2022 11:15:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357199AbiCPPPK (ORCPT ); Wed, 16 Mar 2022 11:15:10 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0400E51E7D; Wed, 16 Mar 2022 08:13:39 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 94BFB1F4467B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647443618; bh=enIv65xIz/LQWh/DPBxtnq0kzu+DCLgUdEOM/boND/Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UaGSSGHTUXuSIBvDX1tYy0LMYkYn1J6J2aMsJpf3WeNfdNaELQZ/ni0qsdps+6FAI 7SlYw9+46MqGlHWG4NZF5Ym3Aw4HL4npAlnDwkzeVlwbZJprasBs4OnLAEs7GlvyRv jpcdB5iCcAGcO6GJQn0c0d2O79uywW15olDNAywL3kU3bOJs+0XHtQVRE/GQR0OFUG JRq8O8HiJnbtIDUXdeLhghnAuzGaG4zWDgx2taSgSKlynk1m4GZl2zmnPUdFJXzPUY YEctQcKVNUWHZILp8FYbLPQ12o5E0miMJNR4G0NIA3qWzUl4Xtymh1iAIuIQ9s/u60 t2AgUoUQM0jfg== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 05/10] arm64: dts: mediatek: asurada: Add ChromeOS EC Date: Wed, 16 Mar 2022 11:13:22 -0400 Message-Id: <20220316151327.564214-6-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316151327.564214-1-nfraprado@collabora.com> References: <20220316151327.564214-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the ChromeOS Embedded Controller present on the Asurada platform. It is connected through the SPI1 bus and offers several functionalities: base detection, PWM controller, I2C tunneling, regulators, Type-C connector management, keyboard and Smart Battery Metrics (SBS). Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 3c5b1e475cf6..bd2730ab6266 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -353,6 +353,14 @@ &pio { "AUD_DAT_MISO0", "AUD_DAT_MISO1"; + cros_ec_int: cros-ec-irq-default-pins { + pins-ec-ap-int-odl { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux = , @@ -432,6 +440,74 @@ &spi1 { mediatek,pad-select = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&cros_ec_int>; + + #address-cells = <1>; + #size-cells = <0>; + + base_detection: cbas { + compatible = "google,cros-cbas"; + }; + + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + + status = "disabled"; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mt6360_ldo3_reg: regulator@0 { + compatible = "google,cros-ec-regulator"; + reg = <0>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + mt6360_ldo5_reg: regulator@1 { + compatible = "google,cros-ec-regulator"; + reg = <1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; }; &spi5 { @@ -446,3 +522,6 @@ &spi5 { &uart0 { status = "okay"; }; + +#include +#include From patchwork Wed Mar 16 15:13:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 551954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75069C433EF for ; Wed, 16 Mar 2022 15:14:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357184AbiCPPPW (ORCPT ); Wed, 16 Mar 2022 11:15:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357186AbiCPPPJ (ORCPT ); Wed, 16 Mar 2022 11:15:09 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1893D554AC; Wed, 16 Mar 2022 08:13:41 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id E11001F44697 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647443619; bh=2p0nXwmN6GNvSmOE+eHbcWmtXYYvQUQ67PxW87FfnP0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OnTFA0NyRINzLPsGHHJRLupwUDQrXTFXZAL1gYHKMD2Nk0UlqXvWXI2HomyMvWsAB ibVz1qaT34Bqixs06vC5y1SaLe/M2OTaB9oOU9s7Aber7hh9E/9LQ8NdMZ/bEn3bJl qugzWEf5u+/4q8u4dg7Do4ZWYPWBPCTkJaFPpJWE/VU8gLyZB9d7AmhA4blWeFLt1f 7XSP4Zb/GAN12W4T5JibJLoV9obppFNE2HY+tCywtidbP9N2Q1Vc2wL8y74ZFe0v0h zoXSLelwiLaNE/KrkwfLddJriyMsnPYHV2Lr+E0jqOHKguaioDKiJrZStLN8sDKHZX RQRfr2272m1mQ== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 06/10] arm64: dts: mediatek: asurada: Add keyboard mapping for the top row Date: Wed, 16 Mar 2022 11:13:23 -0400 Message-Id: <20220316151327.564214-7-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316151327.564214-1-nfraprado@collabora.com> References: <20220316151327.564214-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Chromebooks' embedded keyboards differ from standard layouts for the top row in that they have shortcuts in place of the standard function keys. Map these keys to achieve the functionality that is pictured on the printouts. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index bd2730ab6266..1d1a4b9a989a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -525,3 +525,32 @@ &uart0 { #include #include + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; From patchwork Wed Mar 16 15:13:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 551953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58A22C433F5 for ; Wed, 16 Mar 2022 15:14:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357110AbiCPPP3 (ORCPT ); Wed, 16 Mar 2022 11:15:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357131AbiCPPPK (ORCPT ); Wed, 16 Mar 2022 11:15:10 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1BF95A08F; Wed, 16 Mar 2022 08:13:42 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 3F30E1F4468D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647443621; bh=iWCKuQcSEhS1E0/lZPLekaNrYJWzHrIOHJ2/Yty469k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b6CEDyUVZ1jFrCdInFhpSC/7sqMyVyW4jVS8wNwJ1Ct6DfM7lptPfpO0GQvWJ/9IJ BvjLh0q/NBU/hyqyoUyxT+z1yBKIGti+Tkis0sDlnu+TJZDwzvnsPjGGrZG4RnVmeX 8x1JQJo3vgASiaDuOmwu9MZ6tWdtLjJ77RRkYUXHhoO1T1CY3MYQ01mOBi/KmRfQwN qyGzgPAb0QnsQyBvG/zEcvp+YWT8XIIXlwOSKmSVJZKLPnnmaCgxK9i3AZoYYkx/VJ PrS2UwpSuO5Or//sM3gqxjKyJqpRNzw3Br1lGb25LvuK/pQoJBnvpaYic3uhorLdsT hvsjlQO0L83cA== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 07/10] arm64: dts: mediatek: asurada: Add Cr50 TPM Date: Wed, 16 Mar 2022 11:13:24 -0400 Message-Id: <20220316151327.564214-8-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316151327.564214-1-nfraprado@collabora.com> References: <20220316151327.564214-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Asurada platform has a Google Security Chip connected to the SPI5 bus. It runs the cr50 firmware and provides TPM functionality. Add support for it. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 1d1a4b9a989a..3b4c74d5d5c3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; #include "mt8192.dtsi" +#include / { aliases { @@ -353,6 +354,13 @@ &pio { "AUD_DAT_MISO0", "AUD_DAT_MISO1"; + cr50_int: cr50-irq-default-pins { + pins-gsc-ap-int-odl { + pinmux = ; + input-enable; + }; + }; + cros_ec_int: cros-ec-irq-default-pins { pins-ec-ap-int-odl { pinmux = ; @@ -517,6 +525,15 @@ &spi5 { mediatek,pad-select = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi5_pins>; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&cr50_int>; + }; }; &uart0 { From patchwork Wed Mar 16 15:13:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 552815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79EDBC433EF for ; Wed, 16 Mar 2022 15:14:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357223AbiCPPPj (ORCPT ); Wed, 16 Mar 2022 11:15:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357221AbiCPPPL (ORCPT ); Wed, 16 Mar 2022 11:15:11 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D36E05C852; Wed, 16 Mar 2022 08:13:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 8E8691F44699 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647443622; bh=/bhUnlYrfsDoQs+TNn3x9vAxRBVThPY75bVuGDqvUHc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Xev6M37ThJ7B5XZLX6Q+n2iHghpH/+e9tfo2nYJOl6J1bwh4RKsp35BngBcse0qMN g6MTwYFglWVkWDvI+DxEts7TYamFkFi7SuJB6aHFgIRiecAz/YrfesTduJcz2BRTiB 7wxHq3rZ1uzTVqoj+RRtrWfr4KtynQ/nYco66bb+Z+rnNMDOHqMoqme7iER0k8qGFR tbtkks7BsKP8/1qRDAeTvJElH2TTEnNGtBGBwvjNqOjEY9TrmvIh2NPeunixYXqMFR ywIDgjQbsu7YA20oJ8ssPysp1NROFRRQdA1FKRKsOgZ6gPgmi33fG/i1qBn9TsivqZ i3N54e9f2TUEg== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 08/10] arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad Date: Wed, 16 Mar 2022 11:13:25 -0400 Message-Id: <20220316151327.564214-9-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316151327.564214-1-nfraprado@collabora.com> References: <20220316151327.564214-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the Elan eKTH3000 i2c trackpad present on Asurada. It is connected to the I2C2 bus and has address 0x15. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 3b4c74d5d5c3..b911f4fc3038 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -109,6 +109,16 @@ &i2c2 { clock-stretch-ns = <12600>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + vcc-supply = <&pp3300_u>; + wakeup-source; + }; }; &i2c3 { @@ -440,6 +450,14 @@ pins-bus { bias-disable; }; }; + + trackpad_pins: trackpad-default-pins { + pins-int-n { + pinmux = ; + input-enable; + mediatek,pull-up-adv = <3>; + }; + }; }; &spi1 { From patchwork Wed Mar 16 15:13:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 551952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7FF3C433FE for ; Wed, 16 Mar 2022 15:14:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355281AbiCPPPk (ORCPT ); Wed, 16 Mar 2022 11:15:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357224AbiCPPPM (ORCPT ); Wed, 16 Mar 2022 11:15:12 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3876449F3D; Wed, 16 Mar 2022 08:13:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id DF5CA1F446A4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647443623; bh=W2MR9JRQeWd3Gd2gjq9LLXv6OCGWn1HG5Yfu70CzhFo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z8EbRb6+7S3l8ZQ9BS1lCOzIh2eKSg06Y+KAhfn6SXeoJZWKOqdlVwZIVTgOHJwUn OSMsikWLNyZjbrphJYBKnt4OWn40JDFptSEx1n9gD6n9VyBzwLrHcgol2QN1wuJX9F OwtBWun4Sv6A7M+KdLybc1nrq+2QhqOKLAQCTcMSkllJa9Bk/1RSyy6d4ljRX3eUNW O6r8pZuprjZLvr6pIW7ijgPxcZxNlY6tj3xNoj20VovwBYygz/qnPPPhQIEm7KjSat e7vutsa/t0HlPFr9xR3OsMj7tf0SNmFI5tbq486WGzjlc24HTxmlC+vGOJH5xU8LQ+ SudJPEp4spa8g== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 09/10] arm64: dts: mediatek: asurada: Add I2C touchscreen Date: Wed, 16 Mar 2022 11:13:26 -0400 Message-Id: <20220316151327.564214-10-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316151327.564214-1-nfraprado@collabora.com> References: <20220316151327.564214-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org All machines of the Asurada platform have a touchscreen at address 0x10 in the I2C0 bus, but the devices vary: Spherion has the Elan eKTH3500 touchscreen, while Hayato has a generic HID-over-i2c touchscreen. Add common support for the touchscreens on the platform and the specifics in each board file. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 7 ++++++ .../mediatek/mt8192-asurada-spherion-r0.dts | 4 +++ .../boot/dts/mediatek/mt8192-asurada.dtsi | 25 +++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts index e18e14b13d61..22d187df1428 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -9,3 +9,10 @@ / { model = "MediaTek Hayato rev1"; compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; }; + +&touchscreen { + compatible = "hid-over-i2c"; + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_u>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index b5372ce6bd95..20ae4a869c63 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -11,3 +11,7 @@ / { "google,spherion-rev1", "google,spherion-rev0", "google,spherion", "mediatek,mt8192"; }; + +&touchscreen { + compatible = "elan,ekth3500"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index b911f4fc3038..6e5c2f8fd591 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -92,6 +92,13 @@ &i2c0 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; + + touchscreen: touchscreen@10 { + reg = <0x10>; + interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + }; }; &i2c1 { @@ -458,6 +465,24 @@ pins-int-n { mediatek,pull-up-adv = <3>; }; }; + + touchscreen_pins: touchscreen-default-pins { + pins-irq { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-reset { + pinmux = ; + output-high; + }; + + pins-report-sw { + pinmux = ; + output-low; + }; + }; }; &spi1 { From patchwork Wed Mar 16 15:13:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 552814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B52AC433FE for ; Wed, 16 Mar 2022 15:14:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357292AbiCPPPq (ORCPT ); Wed, 16 Mar 2022 11:15:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357230AbiCPPPM (ORCPT ); Wed, 16 Mar 2022 11:15:12 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88BAA5EDC6; Wed, 16 Mar 2022 08:13:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 400CC1F44713 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647443625; bh=Y+lkLt3+XMMhoecgGOVlam/wNyWF4vFjgKdH60o7wRY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nC8i0iJlO1gOtgwmNN1OQxY9rC9ayCBImNW2RAkJfnnRQvjhBpVlUTN6YIYCn/ep6 PPDO7r57s47zCGcIWxzRTzE/t25MbCWYJOwTteQL5yWYaDleIdM1pZRkvxabiZ8JYr xVo36OwcPqIm1Au6t8GcTxhU3ZNOuhouM+7S2uWq/+AR9T5v6tIbyVclCcmPyypfBj 1i2e6Uav28IgiHDJulQJCS1mpB1QJ+pYye9tjz4oBtP9qUMmPxReJYBVqfmZst/k0d 5bsvOCyFFcy4h+/nzPGZB8cXP/MyQiL3/iS1naRjL0nI0mWj+j0+5o/Xnm1IacOw/V k7GQzWhuHIyhA== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 10/10] arm64: dts: mediatek: spherion: Add keyboard backlight Date: Wed, 16 Mar 2022 11:13:27 -0400 Message-Id: <20220316151327.564214-11-nfraprado@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316151327.564214-1-nfraprado@collabora.com> References: <20220316151327.564214-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Spherion board has keyboard backlight controlled by the PWM signal generated by the ChromeOS EC. Enable PWM output for ChromeOS EC and add a PWM controlled LED node for the keyboard backlight. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8192-asurada-spherion-r0.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index 20ae4a869c63..b9dd5fd2e964 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -4,12 +4,28 @@ */ /dts-v1/; #include "mt8192-asurada.dtsi" +#include / { model = "MediaTek Spherion (rev0 - 3)"; compatible = "google,spherion-rev3", "google,spherion-rev2", "google,spherion-rev1", "google,spherion-rev0", "google,spherion", "mediatek,mt8192"; + + pwmleds { + compatible = "pwm-leds"; + + led { + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +&cros_ec_pwm { + status = "okay"; }; &touchscreen {