From patchwork Wed Mar 16 06:00:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Axe Yang X-Patchwork-Id: 552088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3932CC433FE for ; Wed, 16 Mar 2022 06:00:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353710AbiCPGBq (ORCPT ); Wed, 16 Mar 2022 02:01:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236350AbiCPGBn (ORCPT ); Wed, 16 Mar 2022 02:01:43 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19E6D60064; Tue, 15 Mar 2022 23:00:28 -0700 (PDT) X-UUID: 225d4fb96f9047898fb5dd0881689368-20220316 X-UUID: 225d4fb96f9047898fb5dd0881689368-20220316 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1302056127; Wed, 16 Mar 2022 14:00:22 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Mar 2022 14:00:21 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Mar 2022 14:00:19 +0800 From: Axe Yang To: Ulf Hansson , Rob Herring , Chaotian Jing , Matthias Brugger , Adrian Hunter CC: Yoshihiro Shimoda , Satya Tangirala , Andy Shevchenko , Wolfram Sang , Axe Yang , Lucas Stach , Eric Biggers , Andrew Jeffery , Stephen Boyd , Kiwoong Kim , Yue Hu , Tian Tao , , , , , , Subject: [PATCH v6 1/3] dt-bindings: mmc: mtk-sd: extend interrupts and pinctrls properties Date: Wed, 16 Mar 2022 14:00:12 +0800 Message-ID: <20220316060014.12732-2-axe.yang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220316060014.12732-1-axe.yang@mediatek.com> References: <20220316060014.12732-1-axe.yang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Extend interrupts and pinctrls for SDIO wakeup interrupt feature. This feature allow SDIO devices alarm asynchronous interrupt to host even when host stop providing clock to SDIO card. An extra wakeup interrupt and pinctrl states for SDIO DAT1 pin state switching are required in this scenario. Signed-off-by: Axe Yang --- .../devicetree/bindings/mmc/mtk-sd.yaml | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 297ada03e3de..fb66b042c32f 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -69,12 +69,24 @@ properties: - const: ahb_cg interrupts: - maxItems: 1 + description: + Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended + interrupt is required and be configured as wakeup source irq. + minItems: 1 + maxItems: 2 pinctrl-names: + description: + Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin + will be switched between GPIO mode and SDIO DAT1 mode, state_eint and state_dat1 are + mandatory in this scenarios. + minItems: 2 + maxItems: 4 items: - const: default - const: state_uhs + - const: state_eint + - const: state_dat1 pinctrl-0: description: @@ -86,6 +98,16 @@ properties: should contain uhs mode pin ctrl. maxItems: 1 + pinctrl-2: + description: + should switch dat1 pin to GPIO mode. + maxItems: 1 + + pinctrl-3: + description: + should switch SDIO dat1 pin from GPIO mode back to SDIO mode. + maxItems: 1 + assigned-clocks: description: PLL of the source clock. From patchwork Wed Mar 16 06:00:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Axe Yang X-Patchwork-Id: 552087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEF44C433F5 for ; Wed, 16 Mar 2022 06:00:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353724AbiCPGBx (ORCPT ); Wed, 16 Mar 2022 02:01:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353715AbiCPGBt (ORCPT ); Wed, 16 Mar 2022 02:01:49 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9F0060064; Tue, 15 Mar 2022 23:00:34 -0700 (PDT) X-UUID: 1a4f80253f744e09b2b271ebdd8c3688-20220316 X-UUID: 1a4f80253f744e09b2b271ebdd8c3688-20220316 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1694223216; Wed, 16 Mar 2022 14:00:25 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Mar 2022 14:00:25 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Mar 2022 14:00:24 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Mar 2022 14:00:22 +0800 From: Axe Yang To: Ulf Hansson , Rob Herring , Chaotian Jing , Matthias Brugger , Adrian Hunter CC: Yoshihiro Shimoda , Satya Tangirala , Andy Shevchenko , Wolfram Sang , Axe Yang , Lucas Stach , Eric Biggers , Andrew Jeffery , Stephen Boyd , Kiwoong Kim , Yue Hu , Tian Tao , , , , , , , Yong Mao Subject: [PATCH v6 3/3] mmc: mediatek: add support for SDIO eint wakup IRQ Date: Wed, 16 Mar 2022 14:00:14 +0800 Message-ID: <20220316060014.12732-4-axe.yang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220316060014.12732-1-axe.yang@mediatek.com> References: <20220316060014.12732-1-axe.yang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add support for eint IRQ when MSDC is used as an SDIO host. This feature requires SDIO device support async IRQ function. With this feature, SDIO host can be awakened by SDIO card in suspend state, without additional pin. MSDC driver will time-share the SDIO DAT1 pin. During suspend, MSDC turn off clock and switch SDIO DAT1 pin to GPIO mode. And during resume, switch GPIO function back to DAT1 mode then turn on clock. Some device tree property should be added or modified in MSDC node to support SDIO eint IRQ. Pinctrls named "state_dat1" and "state_eint" are mandatory. Since this feature depends on asynchronous interrupts, "wakeup-source", "keep-power-in-suspend" and "cap-sdio-irq" flags are necessary, and the interrupts list should be extended: &mmcX { ... interrupts-extended = <...>, <&pio xxx IRQ_TYPE_LEVEL_LOW>; ... pinctrl-names = "default", "state_uhs", "state_eint", "state_dat1"; ... pinctrl-2 = <&mmc2_pins_eint>; pinctrl-3 = <&mmc2_pins_dat1>; ... cap-sdio-irq; keep-power-in-suspend; wakeup-source; ... }; Co-developed-by: Yong Mao Signed-off-by: Yong Mao Signed-off-by: Axe Yang --- drivers/mmc/host/mtk-sd.c | 99 +++++++++++++++++++++++++++++++++++---- 1 file changed, 91 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 65037e1d7723..5ff95f32bd45 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2015 MediaTek Inc. + * Copyright (c) 2014-2015, 2022 MediaTek Inc. * Author: Chaotian.Jing */ @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -440,8 +441,12 @@ struct msdc_host { struct pinctrl *pinctrl; struct pinctrl_state *pins_default; struct pinctrl_state *pins_uhs; + struct pinctrl_state *pins_eint; + struct pinctrl_state *pins_dat1; struct delayed_work req_timeout; int irq; /* host interrupt */ + int eint_irq; /* interrupt from sdio device for waking up system */ + int sdio_wake_irq_depth; struct reset_control *reset; struct clk *src_clk; /* msdc source clock */ @@ -465,6 +470,7 @@ struct msdc_host { bool hs400_tuning; /* hs400 mode online tuning */ bool internal_cd; /* Use internal card-detect logic */ bool cqhci; /* support eMMC hw cmdq */ + bool sdio_eint_ready; /* Ready to support SDIO eint interrupt */ struct msdc_save_para save_para; /* used when gate HCLK */ struct msdc_tune_para def_tune_para; /* default tune setting */ struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ @@ -1527,10 +1533,12 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) __msdc_enable_sdio_irq(host, enb); spin_unlock_irqrestore(&host->lock, flags); - if (enb) - pm_runtime_get_noresume(host->dev); - else - pm_runtime_put_noidle(host->dev); + if (mmc->card && !mmc_card_enable_async_irq(mmc->card)) { + if (enb) + pm_runtime_get_noresume(host->dev); + else + pm_runtime_put_noidle(host->dev); + } } static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) @@ -2631,6 +2639,23 @@ static int msdc_drv_probe(struct platform_device *pdev) goto host_free; } + /* Support for SDIO eint irq ? */ + if (mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) { + host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); + if (IS_ERR(host->pins_eint)) { + dev_dbg(&pdev->dev, "Cannot find pinctrl eint!\n"); + } else { + host->pins_dat1 = pinctrl_lookup_state(host->pinctrl, "state_dat1"); + if (IS_ERR(host->pins_dat1)) { + ret = dev_err_probe(&pdev->dev, PTR_ERR(host->pins_dat1), + "Cannot find pinctrl dat1!\n"); + goto host_free; + } + + host->sdio_eint_ready = true; + } + } + msdc_of_property_parse(pdev, host); host->dev = &pdev->dev; @@ -2722,6 +2747,20 @@ static int msdc_drv_probe(struct platform_device *pdev) if (ret) goto release; + if (host->sdio_eint_ready) { + host->eint_irq = irq_of_parse_and_map(host->dev->of_node, 1); + ret = host->eint_irq ? dev_pm_set_dedicated_wake_irq(host->dev, host->eint_irq) : + -ENODEV; + + if (ret) { + dev_err(host->dev, "Failed to register data1 eint irq!\n"); + goto release; + } + + dev_pm_disable_wake_irq(host->dev); + pinctrl_select_state(host->pinctrl, host->pins_dat1); + } + pm_runtime_set_active(host->dev); pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); pm_runtime_use_autosuspend(host->dev); @@ -2734,6 +2773,7 @@ static int msdc_drv_probe(struct platform_device *pdev) return 0; end: pm_runtime_disable(host->dev); + dev_pm_clear_wake_irq(host->dev); release: platform_set_drvdata(pdev, NULL); msdc_deinit_hw(host); @@ -2845,6 +2885,16 @@ static int __maybe_unused msdc_runtime_suspend(struct device *dev) struct msdc_host *host = mmc_priv(mmc); msdc_save_reg(host); + + if (host->sdio_eint_ready) { + disable_irq(host->irq); + pinctrl_select_state(host->pinctrl, host->pins_eint); + if (host->sdio_wake_irq_depth == 0) { + dev_pm_enable_wake_irq(dev); + host->sdio_wake_irq_depth++; + } + sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); + } msdc_gate_clock(host); return 0; } @@ -2860,12 +2910,25 @@ static int __maybe_unused msdc_runtime_resume(struct device *dev) return ret; msdc_restore_reg(host); + + if (host->sdio_eint_ready) { + if (host->sdio_wake_irq_depth > 0) { + dev_pm_disable_wake_irq(dev); + host->sdio_wake_irq_depth--; + sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); + } else { + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); + } + pinctrl_select_state(host->pinctrl, host->pins_uhs); + enable_irq(host->irq); + } return 0; } -static int __maybe_unused msdc_suspend(struct device *dev) +static int __maybe_unused msdc_suspend_noirq(struct device *dev) { struct mmc_host *mmc = dev_get_drvdata(dev); + struct msdc_host *host = mmc_priv(mmc); int ret; if (mmc->caps2 & MMC_CAP2_CQE) { @@ -2874,16 +2937,36 @@ static int __maybe_unused msdc_suspend(struct device *dev) return ret; } + if (host->sdio_eint_ready) + enable_irq_wake(host->eint_irq); + return pm_runtime_force_suspend(dev); } -static int __maybe_unused msdc_resume(struct device *dev) +static int __maybe_unused msdc_resume_noirq(struct device *dev) { + struct mmc_host *mmc = dev_get_drvdata(dev); + struct msdc_host *host = mmc_priv(mmc); + + if (host->sdio_eint_ready) { + disable_irq_wake(host->eint_irq); + + /* + * In noirq resume stage, msdc_runtime_resume() + * won't be called, so disalbe wake irq here + * to block dedicated wake irq handler callback. + */ + if (likely(host->sdio_wake_irq_depth > 0)) { + dev_pm_disable_wake_irq(dev); + host->sdio_wake_irq_depth--; + } + } + return pm_runtime_force_resume(dev); } static const struct dev_pm_ops msdc_dev_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(msdc_suspend_noirq, msdc_resume_noirq) SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) };