From patchwork Thu Mar 17 00:28:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 552803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69F62C433F5 for ; Thu, 17 Mar 2022 00:28:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347650AbiCQA3n (ORCPT ); Wed, 16 Mar 2022 20:29:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244189AbiCQA3m (ORCPT ); Wed, 16 Mar 2022 20:29:42 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68D281C930 for ; Wed, 16 Mar 2022 17:28:27 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id t22so3184898plo.0 for ; Wed, 16 Mar 2022 17:28:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=s7sITGOccSSxXbU5IqO/h2LY98v91UmNuWsJwF4ndG0=; b=WDLX8RusToDhguFb9R+rCWHeuiQ9xj1U0FmX3/jNDcQHvip5vREM6uhQ0SlzUIIT2j Ph2NU9QMfsX+77WZ2mKP8w46ikhcXVC7eVnPTkNSJ+82v4hh+/sAEertJqaOCgn6qI4U oIuPVUAvZacjdffC/1xVdem7LqSICRDZe+ltE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=s7sITGOccSSxXbU5IqO/h2LY98v91UmNuWsJwF4ndG0=; b=ESlJt+XgozxQ96+FXxDn4Mzu901ZMr6coc7CGhQB/Toeqoj9nTrNWcUbPDGTkCn/ws J0j9C8m294YCsQKKatpX5zhX7komnE8BZ4W2yH6FCIwsuFzhzsD84z68Lxc7o9rr/NQi MCA9FZqdBG5nz8Bsp2ZZQmgIjIXOfome34LXX44mOlz2DB9r7hJB7MIMlNDOer1Qd23r JKcQqAj2uwoDPvSc06iNxOfMGXAit2IlTlkmAKGLOavsYxzbFin2BPzMaGWKGrnNQES0 rimAJ8iQcKirqssvWN7gtaRy60y9qUmhVE6UZAqcIAePvVlJNSJJsOsfVeIZ4n0VRmpl X1Uw== X-Gm-Message-State: AOAM530urzm5Kbyx/TaIt7CBsJZ8K6QG2RO/Q07C41Dg++Ix7ct0eE6/ ellAIPoTnmqGpvTICdjrdB01hA== X-Google-Smtp-Source: ABdhPJxoDEonzZLvxbRJfDVLNOwBp6GF5KVNLA9ru3wOYbA5CpXQ2CMarPevTUmhXDQpypumPPymGA== X-Received: by 2002:a17:903:32c3:b0:152:c1b:e840 with SMTP id i3-20020a17090332c300b001520c1be840mr2494389plr.40.1647476906946; Wed, 16 Mar 2022 17:28:26 -0700 (PDT) Received: from localhost ([2620:15c:202:201:3314:2f99:65d0:5a73]) by smtp.gmail.com with UTF8SMTPSA id x16-20020a637c10000000b00380b351aaacsm3396764pgc.16.2022.03.16.17.28.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Mar 2022 17:28:26 -0700 (PDT) From: Matthias Kaehlcke To: Andy Gross , Bjorn Andersson , Rob Herring Cc: Stephen Boyd , devicetree@vger.kernel.org, Douglas Anderson , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH v1 1/4] arm64: dts: qcom: sc7280: Rename crd to crd-r3 Date: Wed, 16 Mar 2022 17:28:17 -0700 Message-Id: <20220316172814.v1.1.I2deda8f2cd6adfbb525a97d8fee008a8477b7b0e@changeid> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are multiple revisions of CRD boards. The current sc7280-crd.dts describes revision 3 and 4 (aka CRD 1.0 and 2.0). Support for a newer version will be added by another patch. Add the revision number to distinguish it from the versionn. Also add the revision numbers to the compatible string. Signed-off-by: Matthias Kaehlcke --- arch/arm64/boot/dts/qcom/Makefile | 2 +- .../arm64/boot/dts/qcom/{sc7280-crd.dts => sc7280-crd-r3.dts} | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) rename arch/arm64/boot/dts/qcom/{sc7280-crd.dts => sc7280-crd-r3.dts} (91%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f9e6343acd03..38d41b1d70ad 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -87,7 +87,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts similarity index 91% rename from arch/arm64/boot/dts/qcom/sc7280-crd.dts rename to arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index e2efbdde53a3..7a028b9248c3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -11,8 +11,8 @@ #include "sc7280-idp-ec-h1.dtsi" / { - model = "Qualcomm Technologies, Inc. sc7280 CRD platform"; - compatible = "qcom,sc7280-crd", "google,hoglin", "qcom,sc7280"; + model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)"; + compatible = "qcom,sc7280-crd", "google,hoglin-rev3", "google,hoglin-rev4", "qcom,sc7280"; aliases { serial0 = &uart5; From patchwork Thu Mar 17 00:28:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 552381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15176C4332F for ; Thu, 17 Mar 2022 00:28:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350626AbiCQA3p (ORCPT ); Wed, 16 Mar 2022 20:29:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349930AbiCQA3o (ORCPT ); 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The hoglin entries are kept to make sure the board keeps booting with older bootloader versions. The compatible string 'google,piglin' (without revision information) is still used by the IDP2 board, which is not expected to evolve further. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index 7a028b9248c3..344338ad8a01 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -12,7 +12,10 @@ / { model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)"; - compatible = "qcom,sc7280-crd", "google,hoglin-rev3", "google,hoglin-rev4", "qcom,sc7280"; + compatible = "qcom,sc7280-crd", + "google,hoglin-rev3", "google,hoglin-rev4", + "google,piglin-rev3", "google,piglin-rev4", + "qcom,sc7280"; aliases { serial0 = &uart5; From patchwork Thu Mar 17 00:28:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 552802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0E5FC433EF for ; Thu, 17 Mar 2022 00:28:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351987AbiCQA3s (ORCPT ); Wed, 16 Mar 2022 20:29:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350808AbiCQA3q (ORCPT ); Wed, 16 Mar 2022 20:29:46 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8E581C932 for ; Wed, 16 Mar 2022 17:28:30 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id f8so5490324pfj.5 for ; Wed, 16 Mar 2022 17:28:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ACtZLOUsEKL3RZmcnEkTB+sHZpJYYlU30MhaK0PAGw0=; b=P9pO/F33FUDOqGxMjS34mKrRhzcGWETsme09k+0RobF1mfoPgq5TAkICcVZels4aLC 5Av4+UZAHAlBE+G8IL61Iv5DthHwXx5b9D/rfLXhYOLkfFZsLG1EAB3shf2IFBRBDktd KPvkqRk2YRyiZuv0ipRkSnMXNOzRSmWk8bX5Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ACtZLOUsEKL3RZmcnEkTB+sHZpJYYlU30MhaK0PAGw0=; b=Aklrda/EITN8JduzoWHs593g8Hk3fTnnm2MnNnjmCcMKNnE51WhkiMqu/PGjJexY1+ vFiTxI7F9MtcC0nM5Qq68xONig3pwHPjJR2wCu+senDhNIztDKmCFsSlg1iUSEdUoNBR 4+uqP/RaMMLbAJRXUeo8RZPIas2dcONVPSIJ+AQTNYsxx0SxhpySb6sxBhX7zV9y6zrH Y8m7ZT2N4kj5htsme1N1Y5v7MYxcPwNGIQG5IJfANMiRe4cTWeOFDESMNTnHqDzV2bbS XLxEz+P8++A4VVWHFtztYpuVgba1SznMWw//DTkY5WeM6nQFmCNmkRBgwqlOnUbns8fL FzeA== X-Gm-Message-State: AOAM532U+MzEO+zuQvvkR09lF12iQ/COceNhZJFv5XwM1m2q5MeoMBR9 noxbq07EsZ0UMnvv7vo6An9www== X-Google-Smtp-Source: ABdhPJwCPte94KNgJ+auSrzd8vBjXMVP+z2KrTWz+4FAbpEukJ6wXFwWyGNfvKo8XQ5xgt6kWNe+Mw== X-Received: by 2002:aa7:8211:0:b0:4f7:8b7:239b with SMTP id k17-20020aa78211000000b004f708b7239bmr1827222pfi.64.1647476910416; Wed, 16 Mar 2022 17:28:30 -0700 (PDT) Received: from localhost ([2620:15c:202:201:3314:2f99:65d0:5a73]) by smtp.gmail.com with UTF8SMTPSA id pi10-20020a17090b1e4a00b001bf9749b95bsm8073837pjb.50.2022.03.16.17.28.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Mar 2022 17:28:30 -0700 (PDT) From: Matthias Kaehlcke To: Andy Gross , Bjorn Andersson , Rob Herring Cc: Stephen Boyd , devicetree@vger.kernel.org, Douglas Anderson , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH v1 3/4] arm64: dts: qcom: sc7280: herobrine: disable some regulators by default Date: Wed, 16 Mar 2022 17:28:19 -0700 Message-Id: <20220316172814.v1.3.Iad21bd53f3ac14956b8dbbf3825fc7ab29abdf97@changeid> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220316172814.v1.1.I2deda8f2cd6adfbb525a97d8fee008a8477b7b0e@changeid> References: <20220316172814.v1.1.I2deda8f2cd6adfbb525a97d8fee008a8477b7b0e@changeid> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Not all herobrine boards have a world facing camera or a fingerprint sensor, disable the regulators that feed these devices by default and only enable them for the boards that use them. Similarly the audio configuration can vary between boards, not all boards have the regulator pp3300_codec, disable it by default. Signed-off-by: Matthias Kaehlcke --- .../qcom/sc7280-herobrine-herobrine-r1.dts | 30 +++++++++++++++++++ .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 ++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index f95273052da0..29c4ca095294 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -14,6 +14,36 @@ / { compatible = "google,herobrine", "qcom,sc7280"; }; +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_codec { + status = "okay"; +}; + +&pp3300_fp_mcu { + status = "okay"; +}; + +&pp2850_vcm_wf_cam { + status = "okay"; +}; + +&pp2850_wf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp1200_wf_cam { + status = "okay"; +}; + /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ &ap_spi_fp { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index dc17f2079695..40cca69b1414 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -92,6 +92,7 @@ pp3300_codec: pp3300-codec-regulator { pinctrl-0 = <&en_pp3300_codec>; vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp3300_left_in_mlb: pp3300-left-in-mlb-regulator { @@ -132,6 +133,7 @@ pp3300_fp_mcu: pp3300-fp-regulator { pinctrl-0 = <&en_fp_rails>; vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp3300_hub: pp3300-hub-regulator { @@ -194,6 +196,7 @@ pp2850_vcm_wf_cam: pp2850-vcm-wf-cam-regulator { pinctrl-0 = <&wf_cam_en>; vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp2850_wf_cam: pp2850-wf-cam-regulator { @@ -214,6 +217,7 @@ pp2850_wf_cam: pp2850-wf-cam-regulator { */ vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp1800_fp: pp1800-fp-regulator { @@ -258,6 +262,7 @@ pp1800_wf_cam: pp1800-wf-cam-regulator { */ vin-supply = <&vreg_l19b_s0>; + status = "disabled"; }; pp1200_wf_cam: pp1200-wf-cam-regulator { @@ -278,6 +283,7 @@ pp1200_wf_cam: pp1200-wf-cam-regulator { */ vin-supply = <&pp3300_z1>; + status = "disabled"; }; /* BOARD-SPECIFIC TOP LEVEL NODES */ From patchwork Thu Mar 17 00:28:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 552380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB9DCC43219 for ; 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Wed, 16 Mar 2022 17:28:31 -0700 (PDT) From: Matthias Kaehlcke To: Andy Gross , Bjorn Andersson , Rob Herring Cc: Stephen Boyd , devicetree@vger.kernel.org, Douglas Anderson , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH v1 4/4] arm64: dts: qcom: sc7280: Add CRD rev5 Date: Wed, 16 Mar 2022 17:28:20 -0700 Message-Id: <20220316172814.v1.4.I37bdb77fdd06fb4143056366d7ec35b929528002@changeid> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220316172814.v1.1.I2deda8f2cd6adfbb525a97d8fee008a8477b7b0e@changeid> References: <20220316172814.v1.1.I2deda8f2cd6adfbb525a97d8fee008a8477b7b0e@changeid> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Qualcomm's SC7280 CRD rev5 (aka CRD 3.0/3.1). Signed-off-by: Matthias Kaehlcke --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sc7280-herobrine-crd.dts | 313 ++++++++++++++++++ 2 files changed, 314 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 38d41b1d70ad..396a6a6a82d8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts new file mode 100644 index 000000000000..fd6eadc8581a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sc7280 CRD 3+ board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; + compatible = "google,hoglin", "qcom,sc7280"; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +&apps_rsc { + pmg1110-regulators { + compatible = "qcom,pmg1110-rpmh-regulators"; + qcom,pmic-id = "k"; + + vreg_s1k_1p0: smps1 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + }; +}; + +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +ap_ts_pen_1v8: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5c { + compatible = "hid-over-i2c"; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <500>; + hid-descr-addr = <0x0000>; + + vdd-supply = <&pp3300_left_in_mlb>; + }; +}; + +/* For nvme */ +&pcie1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1_phy { + status = "okay"; +}; + +/* For eMMC */ +&sdhc_1 { + status = "okay"; +}; + +/* For SD Card */ +&sdhc_2 { + status = "okay"; +}; + +/* PINCTRL - BOARD-SPECIFIC */ + +/* + * Methodology for gpio-line-names: + * - If a pin goes to CRD board and is named it gets that name. + * - If a pin goes to CRD board and is not named, it gets no name. + * - If a pin is totally internal to Qcard then it gets Qcard name. + * - If a pin is not hooked up on Qcard, it gets no name. + */ + +&pm8350c_gpios { + gpio-line-names = "FLASH_STROBE_1", /* 1 */ + "AP_SUSPEND", + "PM8008_1_RST_N", + "", + "", + "EDP_BL_REG_EN", + "PMIC_EDP_BL_EN", + "PMIC_EDP_BL_PWM", + ""; +}; + +&tlmm { + gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ + "AP_TP_I2C_SCL", + "PCIE1_RESET_N", + "PCIE1_WAKE_N", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "", + "TPAD_INT_N", + "", + "", + + "GNSS_L1_EN", /* 10 */ + "GNSS_L5_EN", + "QSPI_DATA_0", + "QSPI_DATA_1", + "QSPI_CLK", + "QSPI_CS_N_1", + /* + * AP_FLASH_WP is crossystem ABI. Schematics call it + * BIOS_FLASH_WP_L (the '_L' suffix is misleading, the + * signal is active high). + */ + "AP_FLASH_WP", + "", + "AP_EC_INT_N", + "", + + "CAM0_RST_N", /* 20 */ + "CAM1_RST_N", + "SM_DBG_UART_TX", + "SM_DBG_UART_RX", + "", + "PM8008_IRQ_1", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "MOS_BT_UART_CTS", + "MOS_BT_UART_RFR", + + "MOS_BT_UART_TX", /* 30 */ + "MOS_BT_UART_RX", + "", + "HUB_RST", + "", + "", + "", + "", + "", + "", + + "EC_SPI_MISO_GPIO40", /* 40 */ + "EC_SPI_MOSI_GPIO41", + "EC_SPI_CLK_GPIO42", + "EC_SPI_CS_GPIO43", + "", + "EARLY_EUD_EN", + "", + "DP_HOT_PLUG_DETECT", + "AP_BRD_ID_0", + "AP_BRD_ID_1", + + "AP_BRD_ID_2", /* 50 */ + "NVME_PWR_REG_EN", + "TS_I2C_SDA_CONN", + "TS_I2C_CLK_CONN", + "TS_RST_CONN", + "TS_INT_CONN", + "AP_I2C_TPM_SDA", + "AP_I2C_TPM_SCL", + "", + "", + + "EDP_HOT_PLUG_DET_N", /* 60 */ + "", + "", + "AMP_EN", + "CAM0_MCLK_GPIO_64", + "CAM1_MCLK_GPIO_65", + "", + "", + "", + "CCI_I2C_SDA0", + + "CCI_I2C_SCL0", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "PCIE1_CLK_REQ_N", + + "EN_PP3300_DX_EDP", /* 80 */ + "US_EURO_HS_SEL", + "FORCED_USB_BOOT", + "WCD_RESET_N", + "MOS_WLAN_EN", + "MOS_BT_EN", + "MOS_SW_CTRL", + "MOS_PCIE0_RST", + "MOS_PCIE0_CLKREQ_N", + "MOS_PCIE0_WAKE_N", + + "MOS_LAA_AS_EN", /* 90 */ + "SD_CARD_DET_CONN", + "", + "", + "MOS_BT_WLAN_SLIMBUS_CLK", + "MOS_BT_WLAN_SLIMBUS_DAT0", + "", + "", + "", + "", + + "", /* 100 */ + "", + "", + "", + "H1_AP_INT_N", + "", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM1_DATA_GPIO_109", + + "UIM1_CLK_GPIO_110", /* 110 */ + "UIM1_RESET_GPIO_111", + "", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RESET", + "UIM1_PRESENT", + "SDM_RFFE0_CLK", + "SDM_RFFE0_DATA", + "", + + "SDM_RFFE1_DATA", /* 120 */ + "SC_GPIO_121", + "FASTBOOT_SEL_1", + "SC_GPIO_123", + "FASTBOOT_SEL_2", + "SM_RFFE4_CLK_GRFC_8", + "SM_RFFE4_DATA_GRFC_9", + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "", + + "", /* 130 */ + "", + "", + "SDR_QLINK_REQ", + "SDR_QLINK_EN", + "QLINK0_WMSS_RESET_N", + "SMR526_QLINK1_REQ", + "SMR526_QLINK1_EN", + "SMR526_QLINK1_WMSS_RESET_N", + "", + + "SAR1_INT_N", /* 140 */ + "SAR0_INT_N", + "", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + + "DMIC01_CLK", /* 150 */ + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "", + "", + "EC_IN_RW_N", + "EN_PP3300_HUB", + "WCD_SWR_TX_DATA2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "MOS_BLE_UART_TX", + "MOS_BLE_UART_RX", + "", + "", + ""; +};