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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id j1sm1634664otl.43.2018.12.07.09.09.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 09:09:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 11:09:51 -0600 Message-Id: <20181207170951.7307-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH] target/i386: Generate #UD when applying LOCK to a register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This covers inc, dec, and the bit test instructions. I believe we've finally covered all of the cases for which we have an atomic path that would use the cpu_A0 temp, which is only initialized for address sources. Fixes: https://bugs.launchpad.net/qemu/+bug/1803160/comments/4 Signed-off-by: Richard Henderson --- target/i386/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.17.2 Reported-by: Alberto Ortega Reported-by: Alberto Ortega Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/i386/translate.c b/target/i386/translate.c index 0dd5fbe45c..eb52322a47 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -1398,6 +1398,11 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) { if (s1->prefix & PREFIX_LOCK) { + if (d != OR_TMP0) { + /* Lock prefix when destination is not memory. */ + gen_illegal_opcode(s1); + return; + } tcg_gen_movi_tl(s1->T0, c > 0 ? 1 : -1); tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0, s1->mem_index, ot | MO_LE); @@ -6764,6 +6769,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_op_ld_v(s, ot, s->T0, s->A0); } } else { + if (s->prefix & PREFIX_LOCK) { + goto illegal_op; + } gen_op_mov_v_reg(s, ot, s->T0, rm); } /* load shift */ @@ -6803,6 +6811,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_op_ld_v(s, ot, s->T0, s->A0); } } else { + if (s->prefix & PREFIX_LOCK) { + goto illegal_op; + } gen_op_mov_v_reg(s, ot, s->T0, rm); } bt_op: