From patchwork Tue Mar 22 10:41:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 553477 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:1248:0:0:0:0 with SMTP id z8csp2319355mag; Tue, 22 Mar 2022 04:24:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz7iP0FjYjSu0rjIbDmkAF+/IheEvFhGnpZeyPxUN7GpokXCiKNMOORR2FD8Y7zOmXobK39 X-Received: by 2002:a05:6402:5186:b0:419:49af:428f with SMTP id q6-20020a056402518600b0041949af428fmr7773104edd.177.1647948276839; Tue, 22 Mar 2022 04:24:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647948276; cv=none; d=google.com; s=arc-20160816; b=tpi5tAIfok5tC5B85v8lckd8xFQxHxYkmwBQ4+x/Tf3COAk70m9M/Qns3m51Bzzr2J 7lWw+uiKO006SQ3xd8Hc0BS3qI4vyZa81pFBCt0GG5qkRsC9ZSQSPy6dkwriNnGyrE5H lH+hC93sLuEZy1wqjHDVbey5yPVutEdtnd0JRiOXhsVPpJuETmGcFvRZtq+SXoUljTKl twwcvukDhipkChP/WwGXIGehYlUuYGcubdD7vVd47Vff5bkkc8xgCH5P7T3LGHRRBiW5 t0MvDz2y57RuBmbM8Tu+AmOjjcs4Ejkt6ATmPHvMloTS+tdE3sfPxqI+BaXfJ9QeQoQ7 +6GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NoM6EHi0XjCyQN28bkas2AtBgiZ28cEHh+DbqDTl1os=; b=fm6J3tPf44pFtujsOdlChqNYvr47aAMYVAXk+bHg2qj40gNF+GtYBpSL6ougpqEcm+ 3o8K+y9c0msIeHJZF6fCAx3kl8VgyEVrEsyH6dQPJ1n7cNL2Aw6fqiXpBC0p+GA8KWTx AmFszDDwBFtjYQkybSd0UFmOeKzGvinYtmX27daGt40nQRF2Ix3cUUv87Q3AVxI0HOQf LMfbbsq+hul2w8sO4hrxDUqKJIJ1xg1LZYzOsHHw+8QER9jGNUzLg3Ey9dqT4SIruefp fkiD8XvThTKTZKwwhKp6Q6091PMFOnnOcnl7m+EgwOQKwL6l5USsakNun54uJv1kKI6O tpXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pKrVqS2o; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id k17-20020a50ce51000000b00418c2b5be28si12583814edj.266.2022.03.22.04.24.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Mar 2022 04:24:36 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pKrVqS2o; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6E94E83B48; Tue, 22 Mar 2022 12:23:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="pKrVqS2o"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9CEF3839D3; Tue, 22 Mar 2022 11:41:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B92D2838D5 for ; Tue, 22 Mar 2022 11:41:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rui.silva@linaro.org Received: by mail-ej1-x62d.google.com with SMTP id qa43so35148406ejc.12 for ; Tue, 22 Mar 2022 03:41:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NoM6EHi0XjCyQN28bkas2AtBgiZ28cEHh+DbqDTl1os=; b=pKrVqS2o+vLDZWQ4nZP5bzr7jPA0HcI0eK5EehwbQ/UHhn70Q7uqLRtcN48xnkMweR BOH+H3LTm9Bly58N2GpxExjAexbqRiwupy/0cTg6oVKa6sMo72lgHVpYnedjgKzIyw6Q ZWxG5Gr7NgJMsNmLveRNEi0Ik7AQXSGN6MZ4h0RtM6Ag5y4j2EQBdlrO28t46pHBw56q FAbnFUTUOsTE0tcxBzTWC3RhNIZNKpTXoQ49gMUeFwAiluzT/J5qi8jS7IPJvC2zWWXN glqwjfW52Xo0Dc6L1McxjpU10pnDQq7FhElT/WOXa64VBMyUu+ea1FS3U9qqJN7t4KIs 3J6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NoM6EHi0XjCyQN28bkas2AtBgiZ28cEHh+DbqDTl1os=; b=TVcXHWGJv7FVqyyK20xKTfs99dZzDM8g04WJ+F2VwZhqlwGZ2ULeQnUgjAxAMOAn7r Dofc/uVKHTNSgorwiLevx3iat6kO/dddElS84v/tTfIRQfY2f5lFXrJKdMo3JxNkC4vT 9PP4DG8stuAbAd+AVkgS2Qcov5G/XeHXJM20Jyah8L1nNRxknglbteYVJSoUX5wAxXOh 8iLVW09ApLhOTHbrc+Dql7u4BRVFQ6lhGzrgb+3LITi9NwN77g4ZeoqwFUTooO/PeKdJ vBJaH2FiGpc4uGF/UyvUeveXBU7B9i2uBwdISmDQD9fmaWjpc9pMosLYDy6oeMZLmVFT fkwQ== X-Gm-Message-State: AOAM533tKv6GQmteOR6oZweC7so5dHEj0uoo89jzZWTsR2411FExJQly 8fY/HNLec1mKXLCdPdgRCJeSIikE8dDNlQ== X-Received: by 2002:a17:907:2cc4:b0:6df:a036:a025 with SMTP id hg4-20020a1709072cc400b006dfa036a025mr23515207ejc.554.1647945703142; Tue, 22 Mar 2022 03:41:43 -0700 (PDT) Received: from arch-thunder.local (a109-49-33-111.cpe.netcabo.pt. [109.49.33.111]) by smtp.gmail.com with ESMTPSA id l2-20020aa7cac2000000b003f9b3ac68d6sm9359641edt.15.2022.03.22.03.41.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Mar 2022 03:41:42 -0700 (PDT) From: Rui Miguel Silva To: u-boot@lists.denx.de Cc: Rui Miguel Silva Subject: [PATCH 1/2] cmd: load: add load command for memory mapped Date: Tue, 22 Mar 2022 10:41:17 +0000 Message-Id: <20220322104118.573537-2-rui.silva@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220322104118.573537-1-rui.silva@linaro.org> References: <20220322104118.573537-1-rui.silva@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 22 Mar 2022 12:23:15 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean cp.b is used a lot as a way to load binaries to memory and execute them, however we may need to integrate this with the efi subsystem to set it up as a bootdev. So, introduce a loadm command that will be consistent with the other loadX commands and will call the efi API's. ex: loadm $kernel_addr $kernel_addr_r $kernel_size with this a kernel with CONFIG_EFI_STUB enabled will be loaded and then subsequently booted with bootefi command. Signed-off-by: Rui Miguel Silva --- README | 1 + cmd/Kconfig | 6 ++++ cmd/bootefi.c | 12 ++++++++ cmd/load.c | 48 ++++++++++++++++++++++++++++++++ include/efi_loader.h | 2 ++ lib/efi_loader/efi_device_path.c | 9 ++++++ 6 files changed, 78 insertions(+) diff --git a/README b/README index fe3ba01865e6..2932734b3edc 100644 --- a/README +++ b/README @@ -2693,6 +2693,7 @@ rarpboot- boot image via network using RARP/TFTP protocol diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd' loads - load S-Record file over serial line loadb - load binary file over serial line (kermit mode) +loadm - load binary blob from source address to destination address md - memory display mm - memory modify (auto-incrementing) nm - memory modify (constant address) diff --git a/cmd/Kconfig b/cmd/Kconfig index 564daa7bbc8d..d70e8398a558 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1076,6 +1076,12 @@ config CMD_LOADB help Load a binary file over serial line. +config CMD_LOADM + bool "loadm" + default y + help + Load a binary over memory mapped. + config CMD_LOADS bool "loads" default y diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 46eebd5ee225..64fe170bc3d6 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -34,6 +34,18 @@ static struct efi_device_path *bootefi_device_path; static void *image_addr; static size_t image_size; +/** + * efi_get_image_parameters() - return image parameters + * + * @img_addr: address of loaded image in memory + * @img_size: size of loaded image + */ +void efi_get_image_parameters(void **img_addr, size_t *img_size) +{ + *img_addr = image_addr; + *img_size = image_size; +} + /** * efi_clear_bootdev() - clear boot device */ diff --git a/cmd/load.c b/cmd/load.c index 7e4a552d90ef..1224a7f85bb3 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -1063,6 +1063,44 @@ static ulong load_serial_ymodem(ulong offset, int mode) #endif +#if defined(CONFIG_CMD_LOADM) +static int do_load_memory_bin(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr, dest, size; + void *src, *dst; + + if (argc != 4) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + + dest = simple_strtoul(argv[2], NULL, 16); + + size = simple_strtoul(argv[3], NULL, 16); + + if (!size) { + printf("loadm: can not load zero bytes\n"); + return 1; + } + + src = map_sysmem(addr, size); + dst = map_sysmem(dest, size); + + memcpy(dst, src, size); + + unmap_sysmem(src); + unmap_sysmem(dst); + + if (IS_ENABLED(CONFIG_CMD_BOOTEFI)) + efi_set_bootdev("Mem", "", "", map_sysmem(dest, 0), size); + + printf("loaded bin to memory: size: %lu\n", size); + + return 0; +} +#endif + /* -------------------------------------------------------------------- */ #if defined(CONFIG_CMD_LOADS) @@ -1137,3 +1175,13 @@ U_BOOT_CMD( ); #endif /* CONFIG_CMD_LOADB */ + +#if defined(CONFIG_CMD_LOADM) +U_BOOT_CMD( + loadm, 4, 0, do_load_memory_bin, + "load binary blob from source address to destination address", + "[src_addr] [dst_addr] [size]\n" + " - load a binary blob from one memory location to other" + " from src_addr to dst_addr by size bytes" +); +#endif /* CONFIG_CMD_LOADM */ diff --git a/include/efi_loader.h b/include/efi_loader.h index 110d8ae79cca..8d199db18ff2 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -585,6 +585,8 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, void efi_save_gd(void); /* Call this to relocate the runtime section to an address space */ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map); +/* Call this to get image parameters */ +void efi_get_image_parameters(void **img_addr, size_t *img_size); /* Add a new object to the object list. */ void efi_add_handle(efi_handle_t obj); /* Create handle */ diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index dc787b4d3dde..707d5e043d3d 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -1112,6 +1112,8 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr, { struct blk_desc *desc = NULL; struct disk_partition fs_partition; + size_t image_size; + void *image_addr; int part = 0; char *filename; char *s; @@ -1127,6 +1129,13 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr, } else if (!strcmp(dev, "Uart")) { if (device) *device = efi_dp_from_uart(); + } else if (!strcmp(dev, "Mem")) { + efi_get_image_parameters(&image_addr, &image_size); + + if (device) + *device = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, + (uintptr_t)image_addr, + image_size); } else { part = blk_get_device_part_str(dev, devnr, &desc, &fs_partition, 1); From patchwork Tue Mar 22 10:41:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 553478 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:1248:0:0:0:0 with SMTP id z8csp2319466mag; Tue, 22 Mar 2022 04:24:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz9y0xQ5252I5CaQnMuzAfMSdU+uB+mmgUD32e6pHelYRXcYAJk8PHkVhtPWFgxHYeXWsIu X-Received: by 2002:a05:6402:2789:b0:419:5317:7d39 with SMTP id b9-20020a056402278900b0041953177d39mr4636339ede.53.1647948286645; Tue, 22 Mar 2022 04:24:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647948286; cv=none; d=google.com; s=arc-20160816; b=FhqduL0jrBZDEhH1o+lQVAeYjnXA3azpXw7obysDTzBlIOjY8FH3M0wkU58dMyLutP 1KkjTLCo1sJDIeb1hDED17h7I33k5oB0xdogqSD1CXKh0o4utT1C4+a2n+ZxpZaZbozj vofU4Iwiw7b7213AdrPlEpJs3jaSAW+3bc54z9H/tOGeGdJZFeS9UEJ56b6+R8699tOr X+cLHVZ8Zk6vC0ycTsEXfFbniGe7afyaDcYdxM/M6py0wOX4fz6MuHD+9qhMwBREJpDA 4CMbO0H00LmVmfTHMugYzXyqtfMFxVpRUeYPX5RgYvRNKHe8zYUEBlwXM17nYCG58CZG kK0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UqgkkNf8DLWWEGORRn4BR7kKk1RMfKBLJOdYwmnILfI=; b=muffcJSvhTckWhnBS/CI2AZKmp7wd9Ho7d/ChVM0vmsdVWoh+Lsv742mkZYJayrr7P 0MdP16Kwu8MsSrikBg8ZKW1EacHSHvxtns3SwKgMgPa4d0Ix/SRbwt+Z/JqZYRzZp6B5 HH+3KnIggD3KvXngyQ9x3+71NtW2VvdW1M94OwxWiGqqGCqmbwJgofqvYabE2DeLADco UICWhs59AMQwrExftUYuk1ddVg70EXsMEDb8VYrJIQPmICuFEofzDHudOVsHKC78E9Xj kPRwwcheVcY8qdoB4ZUMqHx9oxWrSRT2MF+Q3SkwWlg4+ipZxlf39A91SksyIDyZn28n uTuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S4AbLSKO; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id z1-20020a50e681000000b00418c2b5bdefsi12510221edm.209.2022.03.22.04.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Mar 2022 04:24:46 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S4AbLSKO; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3AE4583B44; Tue, 22 Mar 2022 12:23:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="S4AbLSKO"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DAC86838D5; Tue, 22 Mar 2022 11:41:52 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1AED38395F for ; Tue, 22 Mar 2022 11:41:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rui.silva@linaro.org Received: by mail-ej1-x631.google.com with SMTP id qa43so35148748ejc.12 for ; Tue, 22 Mar 2022 03:41:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UqgkkNf8DLWWEGORRn4BR7kKk1RMfKBLJOdYwmnILfI=; b=S4AbLSKOkRnCc/m6zyRbk8zRD/2i9ZxcskBWqnUMgppMw2aFQmuBvqMzEqF0EQXJPZ QOsQ0m2cOzv1zNjj7bTbxisvyFEs2KntcbUWz1qKssdqy6kR6FNWh6nvdT7BKMlw+77F 50bVLNVP19cMfbjT6Zp5DzbbcFX/FtGuV4iAi5LMIXHzvjXn0LouJopqszBk97rA10xy WN5qc4f/OdX5WhguxtSC99+v2rlNt6hfEf5SVQ/QQGq5zDjzhBjHyi6k0I3vuouZC/4V zgRa40V56a1k1q2cCtMLSnKiArndBR6gXjohUXDiovDCtqXHPl2zn56zWpw4G1VFBd/e qWkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UqgkkNf8DLWWEGORRn4BR7kKk1RMfKBLJOdYwmnILfI=; b=3pJFG0OMUFOaKmuFKgCJ2nc1pE82fQ9k9sJ1r3wV+tcLc9wKcOu9TrUlJmCbLAXiI1 dcKoqxpll36BzFYqHy7yltP3fHQ9L2NlWmJIDtxwBkaIscG5M9FUM56PT71aJKLONCP5 XsKv5x6Rp8Jce0ZaLUWsvQbbws4+tEgac6ui7m9T5a3UCUgbE8aC5+4g78gI91XZTmOc vwIveTFVk3FQ8rUS2qkLIm3/h9BvxJ82l3MXl+9m1pf9HC0sP+LQxrJMNQ34taIiTofJ tesgBnzE5kXnudzCpl52DsscDbxelCUaJ69QO+1MwNSxNS7HoQZxbrJIH3y8hk7LEqzr hYsw== X-Gm-Message-State: AOAM531yzmFl6rWaxNxnH+6ZV/4jsyKuoyA/huW28bujPu6Tgr2DmNut UR/yQeNgCFGd2/VV5aLDdXzsFrt+OeFGJw== X-Received: by 2002:a17:906:2bc5:b0:6cd:e676:3624 with SMTP id n5-20020a1709062bc500b006cde6763624mr25114277ejg.277.1647945706233; Tue, 22 Mar 2022 03:41:46 -0700 (PDT) Received: from arch-thunder.local (a109-49-33-111.cpe.netcabo.pt. [109.49.33.111]) by smtp.gmail.com with ESMTPSA id l2-20020aa7cac2000000b003f9b3ac68d6sm9359641edt.15.2022.03.22.03.41.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Mar 2022 03:41:45 -0700 (PDT) From: Rui Miguel Silva To: u-boot@lists.denx.de Cc: Rui Miguel Silva , Abdellatif El Khlifi Subject: [PATCH 2/2] arm: add support to corstone1000 platform Date: Tue, 22 Mar 2022 10:41:18 +0000 Message-Id: <20220322104118.573537-3-rui.silva@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220322104118.573537-1-rui.silva@linaro.org> References: <20220322104118.573537-1-rui.silva@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 22 Mar 2022 12:23:15 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. This code adds the support for the Cortex-A35 implementation at host side, it contains also the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the FPGA MPS3 board implementation of this platform. [2] 0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf Signed-off-by: Abdellatif El Khlifi Signed-off-by: Rui Miguel Silva --- arch/arm/Kconfig | 8 ++ arch/arm/dts/Makefile | 3 + arch/arm/dts/corstone1000-fvp.dts | 33 +++++ arch/arm/dts/corstone1000-mps3.dts | 41 ++++++ arch/arm/dts/corstone1000.dtsi | 167 +++++++++++++++++++++++ board/armltd/corstone1000/Kconfig | 12 ++ board/armltd/corstone1000/MAINTAINERS | 7 + board/armltd/corstone1000/Makefile | 7 + board/armltd/corstone1000/corstone1000.c | 120 ++++++++++++++++ configs/corstone1000_defconfig | 80 +++++++++++ include/configs/corstone1000.h | 85 ++++++++++++ 11 files changed, 563 insertions(+) create mode 100644 arch/arm/dts/corstone1000-fvp.dts create mode 100644 arch/arm/dts/corstone1000-mps3.dts create mode 100644 arch/arm/dts/corstone1000.dtsi create mode 100644 board/armltd/corstone1000/Kconfig create mode 100644 board/armltd/corstone1000/MAINTAINERS create mode 100644 board/armltd/corstone1000/Makefile create mode 100644 board/armltd/corstone1000/corstone1000.c create mode 100644 configs/corstone1000_defconfig create mode 100644 include/configs/corstone1000.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 474ce4a555e4..68206e51f7db 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1279,6 +1279,12 @@ config TARGET_VEXPRESS64_JUNO select USB imply OF_HAS_PRIOR_STAGE +config TARGET_CORSTONE1000 + bool "Support Corstone1000 Platform" + select ARM64 + select PL01X_SERIAL + select DM + config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" select ARM64 @@ -2230,6 +2236,8 @@ source "arch/arm/mach-nexell/Kconfig" source "board/armltd/total_compute/Kconfig" +source "board/armltd/corstone1000/Kconfig" + source "board/bosch/shc/Kconfig" source "board/bosch/guardian/Kconfig" source "board/Marvell/octeontx/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 770a51955ea3..c850c040a36f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1219,6 +1219,9 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb +dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ + corstone1000-fvp.dtb + include $(srctree)/scripts/Makefile.dts targets += $(dtb-y) diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts new file mode 100644 index 000000000000..2c5ea307d532 --- /dev/null +++ b/arch/arm/dts/corstone1000-fvp.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "corstone1000-fvp"; + + ethernet: eth@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gic>; + interrupts = ; + reg-io-width = <2>; + smsc,irq-push-pull; + }; + +}; + +&refclk { + clock-frequency = <50000000>; +}; + +&arm_ffa { + status = "okay"; +}; diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts new file mode 100644 index 000000000000..99a51d2f5148 --- /dev/null +++ b/arch/arm/dts/corstone1000-mps3.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "corstone1000-mps3"; + + ethernet: eth@4010000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gic>; + interrupts = ; + reg-io-width = <2>; + smsc,irq-push-pull; + }; + + usb: usb@40200000 { + compatible = "nxp,usb-isp1763"; + reg = <0x40200000 0x100000>; + interrupts-parent = <&gic>; + interrupts = ; + bus-width = <16>; + dr_mode = "host"; + }; +}; + +&refclk { + clock-frequency = <50000000>; +}; + +&arm_ffa { + status = "okay"; +}; diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi new file mode 100644 index 000000000000..4d9dc3eeb6f5 --- /dev/null +++ b/arch/arm/dts/corstone1000.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +#include + +/ { + compatible = "arm,corstone1000"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + stdout-path = "/uart@1a510000:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0>; + next-level-cache = <&L2_0>; + }; + }; + + memory@88200000 { + device_type = "memory"; + reg = <0x88200000 0x77e00000>; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; + interrupts = <1 9 0xf08>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + + refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: refclk24mhzx2 { + /* Reference 24MHz clock x 2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + uartclk: uartclk { + /* UART clock - 50MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "uartclk"; + }; + + serial0: uart@1a510000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a510000 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + refclk: refclk@1a220000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x1a220000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@1a230000 { + frame-number = <0>; + interrupts = ; + reg = <0x1a230000 0x1000>; + }; + }; + + mbox_es0mhu0: mhu@1b000000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b000000 0x1000>, + <0x1b010000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-es0-mhu0"; + }; + + mbox_es0mhu1: mhu@1b020000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b020000 0x1000>, + <0x1b030000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-es0-mhu1"; + }; + + mbox_semhu1: mhu@1b820000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b820000 0x1000>, + <0x1b830000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-se-mhu1"; + }; + + client { + compatible = "arm,client"; + mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>; + mbox-names = "es0mhu0", "es0mhu1", "semhu1"; + }; + + extsys0: extsys@1A010310 { + compatible = "arm,extsys_ctrl"; + reg = <0x1A010310 0x4>, + <0x1A010314 0x4>; + reg-names = "rstreg", "streg"; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + arm_ffa: arm_ffa { + compatible = "arm,ffa"; + method = "smc"; + status = "disabled"; + }; + +}; diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig new file mode 100644 index 000000000000..709674d4cf7d --- /dev/null +++ b/board/armltd/corstone1000/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CORSTONE1000 + +config SYS_BOARD + default "corstone1000" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "corstone1000" + +endif diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS new file mode 100644 index 000000000000..8c905686de76 --- /dev/null +++ b/board/armltd/corstone1000/MAINTAINERS @@ -0,0 +1,7 @@ +CORSTONE1000 BOARD +M: Rui Miguel Silva +M: Vishnu Banavath +S: Maintained +F: board/armltd/corstone1000/ +F: include/configs/corstone1000.h +F: configs/corstone1000_defconfig diff --git a/board/armltd/corstone1000/Makefile b/board/armltd/corstone1000/Makefile new file mode 100644 index 000000000000..77a82c28929b --- /dev/null +++ b/board/armltd/corstone1000/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Arm Limited +# (C) Copyright 2022 Linaro +# Rui Miguel Silva + +obj-y := corstone1000.o diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c new file mode 100644 index 000000000000..8ac1d0a90fc9 --- /dev/null +++ b/board/armltd/corstone1000/corstone1000.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 ARM Limited + * (C) Copyright 2022 Linaro + * Rui Miguel Silva + */ + +#include +#include +#include +#include +#include + +static const struct pl01x_serial_plat serial_plat = { + .base = V2M_UART0, + .type = TYPE_PL011, + .clock = CONFIG_PL011_CLOCK, +}; + +U_BOOT_DRVINFO(corstone1000_serials) = { + .name = "serial_pl01x", + .plat = &serial_plat, +}; + +static struct mm_region corstone1000_mem_map[] = { + { + /* CVM */ + .virt = 0x02000000UL, + .phys = 0x02000000UL, + .size = 0x02000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* QSPI */ + .virt = 0x08000000UL, + .phys = 0x08000000UL, + .size = 0x08000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Host Peripherals */ + .virt = 0x1A000000UL, + .phys = 0x1A000000UL, + .size = 0x26000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* USB */ + .virt = 0x40200000UL, + .phys = 0x40200000UL, + .size = 0x00100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* ethernet */ + .virt = 0x40100000UL, + .phys = 0x40100000UL, + .size = 0x00100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OCVM */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = corstone1000_mem_map; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +/* + * Board specific ethernet initialization routine. + */ +int board_eth_init(struct bd_info *bis) +{ + int rc = 0; + +#ifndef CONFIG_DM_ETH +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif +#endif + + return rc; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig new file mode 100644 index 000000000000..02f931b0d469 --- /dev/null +++ b/configs/corstone1000_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_TARGET_CORSTONE1000=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x82100000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_IDENT_STRING=" corstone1000 aarch64 " +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk" +CONFIG_LOGLEVEL=7 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="corstone1000# " +# CONFIG_CMD_CONSOLE is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_BOOTM=y +CONFIG_CMD_LOADM=y +CONFIG_CMD_BOOTEFI=y +CONFIG_EFI_LOADER=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y +CONFIG_CMD_BOOTEFI_HELLO=y +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_ENV_EXISTS is not set +CONFIG_CMD_NVEDIT_EFI=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_USB=y +CONFIG_CMD_ITEST=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +# CONFIG_MMC is not set +CONFIG_DM_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_EFI_MM_COMM_TEE=y +# CONFIG_OPTEE is not set +# CONFIG_GENERATE_SMBIOS_TABLE is not set +# CONFIG_HEXDUMP is not set +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +# CONFIG_EFI_CAPSULE_ON_DISK_EARLY is not set +# CONFIG_EFI_CAPSULE_AUTHENTICATE is not set +CONFIG_EFI_HAVE_CAPSULE_SUPPORT=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y +CONFIG_DM_RTC=y +CONFIG_CMD_RTC=y +CONFIG_EFI_GET_TIME=y +CONFIG_EFI_SET_TIME=y +CONFIG_RTC_EMULATION=y +CONFIG_PSCI_RESET=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_CMD_DHCP=y +CONFIG_SMC911X=y +CONFIG_SMC911X_BASE=0x40100000 +CONFIG_DM_ETH=y +CONFIG_PHY_SMSC=y +CONFIG_CMD_BOOTEFI_SELFTEST=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_PHYLIB=y +CONFIG_PHY=y +CONFIG_RAM=y +CONFIG_ERRNO_STR=y +CONFIG_CMD_EDITENV=y +CONFIG_MISC=y diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h new file mode 100644 index 000000000000..dd7b12475081 --- /dev/null +++ b/include/configs/corstone1000.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 ARM Limited + * (C) Copyright 2022 Linaro + * Rui Miguel Silva + * Abdellatif El Khlifi + * + * Configuration for Corstone1000. Parts were derived from other ARM + * configurations. + */ + +#ifndef __CORSTONE1000_H +#define __CORSTONE1000_H + +#include + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_HZ 1000 + +#define V2M_SRAM0 0x02000000 +#define V2M_QSPI 0x08000000 + +#define V2M_DEBUG 0x10000000 +#define V2M_BASE_PERIPH 0x1A000000 + +#define V2M_BASE 0x80000000 + +#define V2M_PERIPH_OFFSET(x) ((x) << 16) + +#define V2M_SYSID (V2M_BASE_PERIPH) +#define V2M_SYSCTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1)) + +#define V2M_COUNTER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32)) +#define V2M_COUNTER_READ (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33)) + +#define V2M_TIMER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34)) +#define V2M_TIMER_BASE0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35)) + +#define V2M_UART0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(81)) +#define V2M_UART1 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(82)) + +#define CONFIG_PL011_CLOCK 50000000 + +/* Physical Memory Map */ +#define PHYS_SDRAM_1 (V2M_BASE) +#define PHYS_SDRAM_1_SIZE 0x80000000 + +#define CONFIG_ENV_SECT_SIZE SZ_64K + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "usb_pgood_delay=250\0" \ + "boot_bank_flag=0x08002000\0" \ + "kernel_addr_bank_0=0x083EE000\0" \ + "kernel_addr_bank_1=0x0936E000\0" \ + "retrieve_kernel_load_addr=" \ + "if itest.l *${boot_bank_flag} == 0; then " \ + "setenv kernel_addr $kernel_addr_bank_0;" \ + "else " \ + "setenv kernel_addr $kernel_addr_bank_1;" \ + "fi;" \ + "\0" \ + "kernel_addr_r=0x88200000\0" + +/* + * config_distro_bootcmd define the boot command to distro_bootcmd, but we here + * want to first try to load a kernel if exists, override that config then + */ +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_BOOTCOMMAND \ + "run retrieve_kernel_load_addr;" \ + "echo Loading kernel from $kernel_addr to memory ... ;" \ + "loadm $kernel_addr $kernel_addr_r 0xc00000;" \ + "usb start; usb reset;" \ + "run distro_bootcmd;" \ + "bootefi $kernel_addr_r $fdtcontroladdr;" +#endif