From patchwork Mon Dec 10 15:04:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153270 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3661434ljp; Mon, 10 Dec 2018 07:06:51 -0800 (PST) X-Google-Smtp-Source: AFSGD/Udbzg/YGzp3XsvVN1qEG/diITXyUyl7mfH0Txvp/in6GTgHgTVZ36irR6yqQ+RX6khaiAy X-Received: by 2002:aed:2844:: with SMTP id r62mr12534413qtd.112.1544454411149; Mon, 10 Dec 2018 07:06:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544454411; cv=none; d=google.com; s=arc-20160816; b=EOKfS62cUjBfcHTzEY+3AEEu510oP2xkqDiEuGSyyi3LRuZMx5sDSJqJhns2rLVA1E lrSs6S6oSGjRNg60t8SJssf8SghvvXSp5F0ATwGVjfSoU/lIDUgAMEtYaEsWjLvq+Y0+ GBzHFxiCYyGVsB+7ZYOEWyo5KqM57kjceayLmU4R2dkVVKE9uSKRg/6E7LoehLdbyPu2 jBcf1L1G2UFpDeVzve28/YxEz7nXO2zfa9RrISDTsItrvdOCsf49+/5BKSfDymYHBUXw f5+cCpj1y/fOstfqN4sammV7U3yj5Fx+rpZ7EBN3G5v0l1V4oxq1JUCydzI7z7nh3jK4 TQFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=K8GVSsip77S76T34m6Ri7M6L4RUXGxE+dcqnBXP+41E=; b=MhxBshDBQIoKNEb2C5cTUDbMsiVKyJdGxjJfSLOtc6hYkM4bq1lUzBrs/C2UGw/QW/ GvutMpAp4R5arwOEh0p7hWORO8Pa74KCCSh/YLheuyBVZkUJRAiYGSLGQni91SZQ5TZP w11UMCqN1n0eoJchuSWKNZm6Cvgdzxm9jdfVB/u9um3qHFFRvim4zA18ELmu8aKFTJ4m apUTDWGgLlOS+GRnnSC2TYMCXJZpeKrewBU98EbuxcUiKHWrrJ9Qh5XhUPp1kxiGMGgQ zX5K1FnKH2vn5mbXmB3mt+81qjfWMYnSlSOl+ymenvdgCYKriz3XYauqG8Y6DNJu6Vi5 n7nQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=S9Cpn6Ka; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 53si799865qtq.250.2018.12.10.07.06.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 10 Dec 2018 07:06:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=S9Cpn6Ka; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33217 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWN90-0003bt-Gt for patch@linaro.org; Mon, 10 Dec 2018 10:06:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34464) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWN7N-0002gD-6w for qemu-devel@nongnu.org; Mon, 10 Dec 2018 10:05:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gWN7L-0003j4-DL for qemu-devel@nongnu.org; Mon, 10 Dec 2018 10:05:09 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:46530) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gWN7L-0003iQ-6B for qemu-devel@nongnu.org; Mon, 10 Dec 2018 10:05:07 -0500 Received: by mail-ot1-x341.google.com with SMTP id w25so10617224otm.13 for ; Mon, 10 Dec 2018 07:05:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K8GVSsip77S76T34m6Ri7M6L4RUXGxE+dcqnBXP+41E=; b=S9Cpn6KaMET7fu6fCqV7jQ6HOzFmvpjWJqOAnOcvuoFgodV95eNoH6lA/f+LW4n5vT 6Ni+4BdIFSvUihwcs4+uQxtAhnLMA7ewMedeuWk0Seekoqmk0zFF50qSE81hNeRQkBzu u/vLyqtN8cakxWomi3cGXeqR2lNT6PDiwLdCM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K8GVSsip77S76T34m6Ri7M6L4RUXGxE+dcqnBXP+41E=; b=CjJ8yI/GwdFv+kdaJvOE/8Xnv1+syfpGoNKIFum80Qaty9zxFDwKRrxIaqa41WFw1G EamOJJmcJTYqQgGTSPUYj10zDx1bwC8aP2z80dXHDGUyspPFbVxcKdGf3UuNTVpeueQM IDK4TO06l87z9y0fPCzN5Qo/2JMyMaK9YcwtLAmWBlJN+IUzlLMeKsjg+vVc7e7rK/vO 0EpanFWC8iD91+ArNtrp/FpZ10/sCANDP8LGfnQ4uU2Q5Ym7XShZttwhjvJrk4Hi3CK1 oIJI0F09xy1GCLTJngQpReLg0qYoHx+CVFA+ba4wifQN5+IHxS24vSbydHk4vTYpLw+X wHig== X-Gm-Message-State: AA+aEWaC0I+wMakKMsZ6v83/rzamqHlHNScxWKxwGTDLhiMtMe2rHh3V /QPvjTBmSpjQnT37xDqm2mvdw/b1MxVbPg== X-Received: by 2002:a9d:58cb:: with SMTP id s11mr8575018oth.161.1544454305599; Mon, 10 Dec 2018 07:05:05 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id b18sm5694734oii.51.2018.12.10.07.05.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Dec 2018 07:05:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 10 Dec 2018 09:04:59 -0600 Message-Id: <20181210150501.7990-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181210150501.7990-1-richard.henderson@linaro.org> References: <20181210150501.7990-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v4 1/3] target/arm: Introduce arm_hcr_el2_eff X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replace arm_hcr_el2_{fmo,imo,amo} with a more general routine that also takes SCR_EL3.NS (aka arm_is_secure_below_el3) into account, as documented for the plethora of bits in HCR_EL2. Signed-off-by: Richard Henderson ---- v3: Fix set of bits affected by just TGE. Reorder the bits to ascending order. Zap VF,VI,VSE when !TGE and ![FIA]MO. v4: Revert VF,VI,VSE change. --- target/arm/cpu.h | 67 +++++++++------------------------------ hw/intc/arm_gicv3_cpuif.c | 21 ++++++------ target/arm/helper.c | 66 ++++++++++++++++++++++++++++++++------ 3 files changed, 83 insertions(+), 71 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 11ec2cce76..05ac883b6b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1729,6 +1729,14 @@ static inline bool arm_is_secure(CPUARMState *env) } #endif +/** + * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. + * E.g. when in secure state, fields in HCR_EL2 are suppressed, + * "for all purposes other than a direct read or write access of HCR_EL2." + * Not included here is HCR_RW. + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env); + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { @@ -2414,54 +2422,6 @@ bool write_cpustate_to_list(ARMCPU *cpu); # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif -/** - * arm_hcr_el2_imo(): Return the effective value of HCR_EL2.IMO. - * Depending on the values of HCR_EL2.E2H and TGE, this may be - * "behaves as 1 for all purposes other than direct read/write" or - * "behaves as 0 for all purposes other than direct read/write" - */ -static inline bool arm_hcr_el2_imo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_IMO; - } -} - -/** - * arm_hcr_el2_fmo(): Return the effective value of HCR_EL2.FMO. - */ -static inline bool arm_hcr_el2_fmo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_FMO; - } -} - -/** - * arm_hcr_el2_amo(): Return the effective value of HCR_EL2.AMO. - */ -static inline bool arm_hcr_el2_amo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_AMO; - } -} - static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el) { @@ -2470,6 +2430,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, bool secure = arm_is_secure(env); bool pstate_unmasked; int8_t unmasked = 0; + uint64_t hcr_el2; /* Don't take exceptions if they target a lower EL. * This check should catch any exceptions that would not be taken but left @@ -2479,6 +2440,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, return false; } + hcr_el2 = arm_hcr_el2_eff(env); + switch (excp_idx) { case EXCP_FIQ: pstate_unmasked = !(env->daif & PSTATE_F); @@ -2489,13 +2452,13 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, break; case EXCP_VFIQ: - if (secure || !arm_hcr_el2_fmo(env) || (env->cp15.hcr_el2 & HCR_TGE)) { + if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { /* VFIQs are only taken when hypervized and non-secure. */ return false; } return !(env->daif & PSTATE_F); case EXCP_VIRQ: - if (secure || !arm_hcr_el2_imo(env) || (env->cp15.hcr_el2 & HCR_TGE)) { + if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { /* VIRQs are only taken when hypervized and non-secure. */ return false; } @@ -2534,7 +2497,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * to the CPSR.F setting otherwise we further assess the state * below. */ - hcr = arm_hcr_el2_fmo(env); + hcr = hcr_el2 & HCR_FMO; scr = (env->cp15.scr_el3 & SCR_FIQ); /* When EL3 is 32-bit, the SCR.FW bit controls whether the @@ -2551,7 +2514,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * when setting the target EL, so it does not have a further * affect here. */ - hcr = arm_hcr_el2_imo(env); + hcr = hcr_el2 & HCR_IMO; scr = false; break; default: diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 068a8e8e9b..cbad6037f1 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -85,8 +85,8 @@ static bool icv_access(CPUARMState *env, int hcr_flags) * * access if NS EL1 and either IMO or FMO == 1: * CTLR, DIR, PMR, RPR */ - bool flagmatch = ((hcr_flags & HCR_IMO) && arm_hcr_el2_imo(env)) || - ((hcr_flags & HCR_FMO) && arm_hcr_el2_fmo(env)); + uint64_t hcr_el2 = arm_hcr_el2_eff(env); + bool flagmatch = hcr_el2 & hcr_flags & (HCR_IMO | HCR_FMO); return flagmatch && arm_current_el(env) == 1 && !arm_is_secure_below_el3(env); @@ -1552,8 +1552,9 @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, /* No need to include !IsSecure in route_*_to_el2 as it's only * tested in cases where we know !IsSecure is true. */ - route_fiq_to_el2 = arm_hcr_el2_fmo(env); - route_irq_to_el2 = arm_hcr_el2_imo(env); + uint64_t hcr_el2 = arm_hcr_el2_eff(env); + route_fiq_to_el2 = hcr_el2 & HCR_FMO; + route_irq_to_el2 = hcr_el2 & HCR_IMO; switch (arm_current_el(env)) { case 3: @@ -1895,8 +1896,8 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env, if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || - (arm_hcr_el2_imo(env) == 0 && arm_hcr_el2_fmo(env) == 0)) { + /* Note that arm_hcr_el2_eff takes secure state into account. */ + if ((arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) == 0) { r = CP_ACCESS_TRAP_EL3; } break; @@ -1936,8 +1937,8 @@ static CPAccessResult gicv3_dir_access(CPUARMState *env, static CPAccessResult gicv3_sgi_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - if ((arm_hcr_el2_imo(env) || arm_hcr_el2_fmo(env)) && - arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) { + if (arm_current_el(env) == 1 && + (arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) != 0) { /* Takes priority over a possible EL3 trap */ return CP_ACCESS_TRAP_EL2; } @@ -1961,7 +1962,7 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env, if (env->cp15.scr_el3 & SCR_FIQ) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || !arm_hcr_el2_fmo(env)) { + if ((arm_hcr_el2_eff(env) & HCR_FMO) == 0) { r = CP_ACCESS_TRAP_EL3; } break; @@ -2000,7 +2001,7 @@ static CPAccessResult gicv3_irq_access(CPUARMState *env, if (env->cp15.scr_el3 & SCR_IRQ) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || !arm_hcr_el2_imo(env)) { + if ((arm_hcr_el2_eff(env) & HCR_IMO) == 0) { r = CP_ACCESS_TRAP_EL3; } break; diff --git a/target/arm/helper.c b/target/arm/helper.c index 037cece133..95d59e07fb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1331,9 +1331,10 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) { CPUState *cs = ENV_GET_CPU(env); + uint64_t hcr_el2 = arm_hcr_el2_eff(env); uint64_t ret = 0; - if (arm_hcr_el2_imo(env)) { + if (hcr_el2 & HCR_IMO) { if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |= CPSR_I; } @@ -1343,7 +1344,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) } } - if (arm_hcr_el2_fmo(env)) { + if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |= CPSR_F; } @@ -4008,6 +4009,51 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, hcr_write(env, NULL, value); } +/* + * Return the effective value of HCR_EL2. + * Bits that are not included here: + * RW (read from SCR_EL3.RW as needed) + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env) +{ + uint64_t ret = env->cp15.hcr_el2; + + if (arm_is_secure_below_el3(env)) { + /* + * "This register has no effect if EL2 is not enabled in the + * current Security state". This is ARMv8.4-SecEL2 speak for + * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). + * + * Prior to that, the language was "In an implementation that + * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves + * as if this field is 0 for all purposes other than a direct + * read or write access of HCR_EL2". With lots of enumeration + * on a per-field basis. In current QEMU, this is condition + * is arm_is_secure_below_el3. + * + * Since the v8.4 language applies to the entire register, and + * appears to be backward compatible, use that. + */ + ret = 0; + } else if (ret & HCR_TGE) { + /* These bits are up-to-date as of ARMv8.4. */ + if (ret & HCR_E2H) { + ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | + HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | + HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | + HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE); + } else { + ret |= HCR_FMO | HCR_IMO | HCR_AMO; + } + ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | + HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | + HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | + HCR_TLOR); + } + + return ret; +} + static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO, @@ -6526,12 +6572,13 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure) { CPUARMState *env = cs->env_ptr; - int rw; - int scr; - int hcr; + bool rw; + bool scr; + bool hcr; int target_el; /* Is the highest EL AArch64? */ - int is64 = arm_feature(env, ARM_FEATURE_AARCH64); + bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); + uint64_t hcr_el2; if (arm_feature(env, ARM_FEATURE_EL3)) { rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); @@ -6543,18 +6590,19 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, rw = is64; } + hcr_el2 = arm_hcr_el2_eff(env); switch (excp_idx) { case EXCP_IRQ: scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); - hcr = arm_hcr_el2_imo(env); + hcr = hcr_el2 & HCR_IMO; break; case EXCP_FIQ: scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); - hcr = arm_hcr_el2_fmo(env); + hcr = hcr_el2 & HCR_FMO; break; default: scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); - hcr = arm_hcr_el2_amo(env); + hcr = hcr_el2 & HCR_AMO; break; }; From patchwork Mon Dec 10 15:05:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153272 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3662511ljp; Mon, 10 Dec 2018 07:07:43 -0800 (PST) X-Google-Smtp-Source: AFSGD/UwIdVhMYaFKGFNu1ux0XMqKSnpkfdhk2e6u9BY68DrlHF4eF5gnBCIcM0eudQPRM103hHM X-Received: by 2002:ac8:4818:: with SMTP id g24mr12104843qtq.66.1544454463528; Mon, 10 Dec 2018 07:07:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544454463; cv=none; d=google.com; s=arc-20160816; b=lRiQ7ZRLPuvbSY9j0m6WYtcy76XrN5RKDlssaf6WTQGngotJuhc6w8YcNY7UVahZcl 9md/yR3XFG21PAXvO6yco5yiu0TWUK7jrMaGJH8MV8z0bmfvOV6aUNg5v8XG6xCbndxU 4/Clx1z1qdpOtzn+SYCaSbNstZ6p1Oa5g07du+8H+5zUPiwK4jliJ4PH5bt8k2RQX1Rd tbIMISgPEdUSZmUdLdzTfrOAtDDocsHfjqjTS0d09D2j79o+08E+Pn7VNf8mMCp4rZ9Q I2oJT1MwrnxUi3MviC/3HFJSkyuiSGuJzGKpPW5sMQrg5AlCx6hJCPKI8icIirtl934w ga5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=CkPc61eIpCVWmyDPgstZ8J1bd1SqGM9XNiDjV1wFZ/Q=; b=jbpWMyLBLgvBqQpgzw6CpL4grIGrXSvcWJ9gTJJkgvL72LWUuVSGYPodtq1I1M4pGg VSlDStNK/QoPGZmHpmQmMblain2OVXK+9Y5VU10p+375VtrrJko6dNAD8tvhxECb5jXc 6+upwFLc2FhsfEkQIV0d5Lz5B93U/wJRDa0Uc4S8ZjZoxEqeJqnU2eyDTj9YFMZxDqVN P3wGOt9WYG1AHZ+AjGdssnQLNlKvEuazVr6pcH5RAWF5abfszjYx0eR+u6GKSlj89ZYQ nJMcnBKJaQdiX9moBXX2WRsLna6hOTmniWBfg7N9sO0NAmp9OZb/1Bqo7ch8U4rjbqSl XvRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RFh4+Zys; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 21si1846854qki.9.2018.12.10.07.07.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 10 Dec 2018 07:07:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RFh4+Zys; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33216 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWN9q-0003aj-Lr for patch@linaro.org; Mon, 10 Dec 2018 10:07:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWN7N-0002gS-Lc for qemu-devel@nongnu.org; Mon, 10 Dec 2018 10:05:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gWN7M-0003jb-8h for qemu-devel@nongnu.org; Mon, 10 Dec 2018 10:05:09 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:46252) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gWN7M-0003jL-3E for qemu-devel@nongnu.org; Mon, 10 Dec 2018 10:05:08 -0500 Received: by mail-oi1-x242.google.com with SMTP id x202so9156102oif.13 for ; Mon, 10 Dec 2018 07:05:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CkPc61eIpCVWmyDPgstZ8J1bd1SqGM9XNiDjV1wFZ/Q=; b=RFh4+ZysfxLkhz2WOLTcLpaadSic8XXIzPGSZjRKWMpw3fn6jOjxHdf33++ZkYSdTJ CYUE+HbXLhCy/PEXkgJE9QPgXjB3Z9I6221RQFFp424d1QOzFHro8O/XoVbnSQ3HLYFn XMbTcoupyJTitHDB1tqFShBdDiRCdNy44ZnjY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CkPc61eIpCVWmyDPgstZ8J1bd1SqGM9XNiDjV1wFZ/Q=; b=f4S4jG3WlFav5FYlJBSQTUkYGXhekjggYBFOt3B9X9FGTitbp7KOLo3vWRTqAGH809 3p0oCZEyN3eHsgyT4CTSArI2C4Bmx+cO0lhukhQ2LOtmgOLg45KIqOWJP8M4fRJryquK JgGOsBNwDo3UZjOPjoXUGu7D+AWOZPeSA5hq71yaCMLcDFNfhesvOXEmb/Y9+sR51yej bAa22JOlBHdd4zbVB2jeKOK6/rxWUpFDnmIwS7nvT6hNC8bGYTzsmD5uz5dtqtjvJ96T m9oLkcn3YEuA28VMeAAGp7oKxVrAS6M8Nr5WcSH16/ZGFvWa/NCF7vfz2qK9TLZPGqFe MAhg== X-Gm-Message-State: AA+aEWaY7yt96czoZOEqDg2noW8dPZLqolxiLuiGSPWN/Y8cg5P2nS4b Mxd1eg2f7YrpLZIv7WSpo1a5AssEMtBeSA== X-Received: by 2002:aca:bf06:: with SMTP id p6mr7139085oif.269.1544454306818; Mon, 10 Dec 2018 07:05:06 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id b18sm5694734oii.51.2018.12.10.07.05.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Dec 2018 07:05:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 10 Dec 2018 09:05:00 -0600 Message-Id: <20181210150501.7990-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181210150501.7990-1-richard.henderson@linaro.org> References: <20181210150501.7990-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v4 2/3] target/arm: Use arm_hcr_el2_eff more places X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since arm_hcr_el2_eff includes a check against arm_is_secure_below_el3, we can often remove a nearby check against secure state. In some cases, sort the call to arm_hcr_el2_eff to the end of a short-circuit logical sequence. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Do not change regime_translation_disabled. --- target/arm/helper.c | 12 +++++------- target/arm/op_helper.c | 14 ++++++-------- 2 files changed, 11 insertions(+), 15 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 95d59e07fb..d6f8be9f4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -448,7 +448,7 @@ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, int el = arm_current_el(env); bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -468,7 +468,7 @@ static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, int el = arm_current_el(env); bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -488,7 +488,7 @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, int el = arm_current_el(env); bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -4566,8 +4566,7 @@ int sve_exception_el(CPUARMState *env, int el) if (disabled) { /* route_to_el2 */ return (arm_feature(env, ARM_FEATURE_EL2) - && !arm_is_secure(env) - && (env->cp15.hcr_el2 & HCR_TGE) ? 2 : 1); + && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); } /* Check CPACR.FPEN. */ @@ -6216,9 +6215,8 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) * and CPS are treated as illegal mode changes. */ if (write_type == CPSRWriteByInstr && - (env->cp15.hcr_el2 & HCR_TGE) && (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && - !arm_is_secure_below_el3(env)) { + (arm_hcr_el2_eff(env) & HCR_TGE)) { return 1; } return 0; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0d6e89e474..ef72361a36 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -33,8 +33,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, { CPUState *cs = CPU(arm_env_get_cpu(env)); - if ((env->cp15.hcr_el2 & HCR_TGE) && - target_el == 1 && !arm_is_secure(env)) { + if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* * Redirect NS EL1 exceptions to NS EL2. These are reported with * their original syndrome register value, with the exception of @@ -428,9 +427,9 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the * bits will be zero indicating no trap. */ - if (cur_el < 2 && !arm_is_secure(env)) { - mask = (is_wfe) ? HCR_TWE : HCR_TWI; - if (env->cp15.hcr_el2 & mask) { + if (cur_el < 2) { + mask = is_wfe ? HCR_TWE : HCR_TWI; + if (arm_hcr_el2_eff(env) & mask) { return 2; } } @@ -995,7 +994,7 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) exception_target_el(env)); } - if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) { + if (cur_el == 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) { /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. * We also want an EL2 guest to be able to forbid its EL1 from * making PSCI calls into QEMU's "firmware" via HCR.TSC. @@ -1098,8 +1097,7 @@ void HELPER(exception_return)(CPUARMState *env) goto illegal_return; } - if (new_el == 1 && (env->cp15.hcr_el2 & HCR_TGE) - && !arm_is_secure_below_el3(env)) { + if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; } From patchwork Mon Dec 10 15:05:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153273 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3662683ljp; Mon, 10 Dec 2018 07:07:51 -0800 (PST) X-Google-Smtp-Source: AFSGD/X7mPgpEeGxIVw+ECD+i8Yq1d99i73VL8KGkcEU1R4bt3t7YFf06Y5I0UODMCk30CzylmQt X-Received: by 2002:a0c:e5c1:: with SMTP id u1mr11929674qvm.113.1544454471273; Mon, 10 Dec 2018 07:07:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544454471; cv=none; d=google.com; s=arc-20160816; b=w0djHzyCcxbjsXYVrZa/beefVMkmxNWjVqERmBN3mte0llj3IqA2ItrK2hyMhoYneS 8ilFM3XnlKQyuxgWKzPs5PAQ+DXvNiJr6B0QaMOwvDoguLDxNBBgl45c86nAUwjQ+gRc 8ArJ8yAmDO70SSWj+/cukL2JDN85/o5EGXIJj+hGHyp+4OecQFJiT6uhRQ3hd5Y6s820 QOSCa5fP2daKD2GKItSdcn2PhKeISquiuIWT+dMyhgxWJMLyVdyRv+StHAjpA+4lEgG0 1enbA2CGynUJZwye1UhKDQvEoeOlCSU+v0Zig45GIvg7me4J+p9tEff1H9o/c0ifVmSp mJ9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=xir+xQnKUxj9WKRQcojx3q0A4djL7id8IxY2T1i5d/U=; b=AZJewzPhs12LwVqzIHX8UkN5ReQzE6/K1+X+cS5E/3dli39gxJBSMFuSFXZzvXGj3X tYNWcdWyLTdVALmXjKx0S1BeEVkPEP9e7pcdXlh23H0yAbqXoe6RLBOgkDsJY1ZAPiqm +QT5k0WI2JQC6k5BVG2K+Ni7cn7w+4VecSEymQhFRcHPsBVIADaI9AiBbcKW5YumrrZD SYM5AnPShjlzMDC93pXV9Vm4nq+zmD/DoXl1v+UTrzUYtyj13pjutW66zrcUQ/yDgpKe WsZP9rRjey+0AREyt4qLMEZ3t44P8YkGSsnCYqOD4H8GjGxNp2E/XSEVAJTwxR2f6Niy 1Khg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a1vosRGX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r18si1360100qtc.338.2018.12.10.07.07.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 10 Dec 2018 07:07:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a1vosRGX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33219 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWN9y-0003j4-D8 for patch@linaro.org; Mon, 10 Dec 2018 10:07:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34513) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWN7T-0002jk-WE for qemu-devel@nongnu.org; Mon, 10 Dec 2018 10:05:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gWN7N-0003kk-G9 for qemu-devel@nongnu.org; Mon, 10 Dec 2018 10:05:15 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:41805) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gWN7N-0003k7-7o for qemu-devel@nongnu.org; Mon, 10 Dec 2018 10:05:09 -0500 Received: by mail-ot1-x344.google.com with SMTP id u16so10643099otk.8 for ; Mon, 10 Dec 2018 07:05:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xir+xQnKUxj9WKRQcojx3q0A4djL7id8IxY2T1i5d/U=; b=a1vosRGXg8v4nKClFgGvsMBzGocPd4klBY/QNNzVauslswF8ItAKW/IRpz+BnQlHp3 bPAhEQU5Q7icQrKxGcRG0I/wSdKdQ7aThMAP8sQLtGAdhJvDHdTcMoblr6BmRK1eDhDM rpYwBY1TOsz25xOd33K+yAbEKeP4+d4hUBgmE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xir+xQnKUxj9WKRQcojx3q0A4djL7id8IxY2T1i5d/U=; b=bxf1EprtZfMoij+BU/t8MZPJOU4GbdnvV1sDExvgT1E2M6scdYrbcvrQ8ZBrxVqJln CteGwnE4Mzi3uFrJluo05y2A1u8QvEXHFKmI/FCaaMjVCTSy+E/Xu4kz2SEAFdh+kJDL UAM/TKyG+10OWb+di+VgztR26A8bSa+5gDWRAoYXdJVKWCLQaos37mvLIXsJZHDJ0e32 zwVQzoiblheoCxoAwPSZfhdCzAaKH+ZqSolkP0M1dXOWZvYnFFR8pNQW8W6xgdJpyQnb SGzxE7qWfKRfUN/6wSRz0+ik1LFwydH+0Kcmjrdh1OsQUDOON4q/UGhcoazZS6tHWCKJ 6SZA== X-Gm-Message-State: AA+aEWa6+jdzIenSPwlKkLsqsd1b6LbeyGMWw+56jSU5U7KwItHadvWq t8wTCK77+m9HMjqlUCinmejTq6Hxhh7zdw== X-Received: by 2002:a05:6830:1584:: with SMTP id i4mr8189486otr.116.1544454308242; Mon, 10 Dec 2018 07:05:08 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id b18sm5694734oii.51.2018.12.10.07.05.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Dec 2018 07:05:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 10 Dec 2018 09:05:01 -0600 Message-Id: <20181210150501.7990-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181210150501.7990-1-richard.henderson@linaro.org> References: <20181210150501.7990-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v4 3/3] target/arm: Implement the ARMv8.1-LOR extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Provide a trivial implementation with zero limited ordering regions, which causes the LDLAR and STLLR instructions to devolve into the LDAR and STLR instructions from the base ARMv8.0 instruction set. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Mark LORID_EL1 read-only. Add TLOR access checks. Conditionally unmask TLOR in hcr/scr_write. v3: Fix isar_feature_aa64_lor. Split out access_lor_ns. Defer all {E2H,TGE} vs TLOR testing to arm_hcr_el2_eff. --- target/arm/cpu.h | 5 +++ target/arm/cpu64.c | 1 + target/arm/helper.c | 75 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 12 ++++++ 4 files changed, 93 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05ac883b6b..c943f35dd9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3340,6 +3340,11 @@ static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; } +static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1a4289c9dd..1d57be0c91 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -326,6 +326,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64mmfr1; t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ + t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); cpu->isar.id_aa64mmfr1 = t; /* Replicate the same data to the 32-bit id registers. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d6f8be9f4e..644599b29d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1281,6 +1281,7 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Begin with base v8.0 state. */ uint32_t valid_mask = 0x3fff; + ARMCPU *cpu = arm_env_get_cpu(env); if (arm_el_is_aa64(env, 3)) { value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ @@ -1303,6 +1304,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) valid_mask &= ~SCR_SMD; } } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |= SCR_TLOR; + } /* Clear all-context RES0 bits. */ value &= valid_mask; @@ -3963,6 +3967,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) */ valid_mask &= ~HCR_TSC; } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |= HCR_TLOR; + } /* Clear RES0 bits. */ value &= valid_mask; @@ -5018,6 +5025,42 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr0; } +/* Shared logic between LORID and the rest of the LOR* registers. + * Secure state has already been delt with. + */ +static CPAccessResult access_lor_ns(CPUARMState *env) +{ + int el = arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_is_secure_below_el3(env)) { + /* Access ok in secure mode. */ + return CP_ACCESS_OK; + } + return access_lor_ns(env); +} + +static CPAccessResult access_lor_other(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + if (arm_is_secure_below_el3(env)) { + /* Access denied in secure mode. */ + return CP_ACCESS_TRAP; + } + return access_lor_ns(env); +} + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -5759,6 +5802,38 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &sctlr); } + if (cpu_isar_feature(aa64_lor, cpu)) { + /* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ + static const ARMCPRegInfo lor_reginfo[] = { + { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, + .access = PL1_R, .accessfn = access_lorid, + .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, lor_reginfo); + } + if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fd36425f1a..e1da1e4d6f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2290,6 +2290,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } return; + case 0x8: /* STLLR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* StoreLORelease is the same as Store-Release for QEMU. */ + /* fall through */ case 0x9: /* STLR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn == 31) { @@ -2301,6 +2307,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; + case 0xc: /* LDLAR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ + /* fall through */ case 0xd: /* LDAR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn == 31) {