From patchwork Mon Dec 10 17:35:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 153318 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3819451ljp; Mon, 10 Dec 2018 09:36:33 -0800 (PST) X-Google-Smtp-Source: AFSGD/VIGl8Dc1zineNuUqjr5thC7jRhvwNKLwDfwmYowOuvpv34ufa2BgAo4hbKymNxN3++2MRu X-Received: by 2002:a63:1848:: with SMTP id 8mr11478307pgy.81.1544463393435; Mon, 10 Dec 2018 09:36:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544463393; cv=none; d=google.com; s=arc-20160816; b=wJM4/cclcguHQACr6zMvy8sPGBfkJ6Rkc6vZbtzQX9vsizVlulZlz84yOuLhdp/Em0 9KZ5DAO9A7KBq7ba06OK44aYOEw+rOEUPmEK6AgWjX9L5qoQ3NAf4MF4M/tQfWM7JpCx 5UNbw7tJW8XVhqjg4iGEuRN+x/MFzS8bI9hpOc1EM991PMwx129elH4CTmtMJJUqqq2Q ilIxhe0BSud7qeHobFl5fYcxUaGAJneJRmgfI+LXuaUq2r7oZX/6iyNiDEtAp3GdcHQ7 EeS4cFCiiCLAcGu3PtUQ5XrsZdLU9LpuvhKbEHXBiZq6tG5R2SGV77QRvw5d9zHfIeCt 1C2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UfYvMyUASU0SktOneqY893l+ivwuHLJC4IjYGuuzrdU=; b=Mr0MbpRKPuvSQc8fQV7V1hQehb4aVMQ0EitjgyIkJmz54MUnKilmBcDo3kSZx+d08y aSWj2CT6LjJLLNtGbxAC2ScWI0hteBsByXx0dEQNQjbfjIvayRv/S3nNnvl5WLkUc6mq pQAkWi/f9EYGawKrzabydzKY1eVD52LECkW2Oawc7EM8nnINKzwb7kg/af75ESCuLB5c 19MllZNOqNyT4zRaSyBfGXYVIGTmwzAfMu99uEdX6CTNdRZlSt8qONnVJ/dm7mXFnowY MNMasvpoC83jvmuMslxbNJLrLjcWmnzB22akWQtukL/IhZd0Fdkys0pOJ6wCk7zJZhVx e85g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NzymLJJR; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n5si9786173pgl.485.2018.12.10.09.36.33; Mon, 10 Dec 2018 09:36:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NzymLJJR; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727974AbeLJRgc (ORCPT + 6 others); Mon, 10 Dec 2018 12:36:32 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:45547 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727595AbeLJRgc (ORCPT ); Mon, 10 Dec 2018 12:36:32 -0500 Received: by mail-pg1-f196.google.com with SMTP id y4so5265171pgc.12 for ; Mon, 10 Dec 2018 09:36:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UfYvMyUASU0SktOneqY893l+ivwuHLJC4IjYGuuzrdU=; b=NzymLJJRnKatfmJWgRKG8bAq9MZ+HEbSo4SRHnje6au6eEkc0sG2Er84QFmA408r+A SQNOyVrFo86xbbJh1AzLkGfjulDB4R5i628VHW6i9kgw+7OEg/yhiWgo5NN3pZKoEgqa MU7U04cpHLakl7+WS4tZ57/DGLoVtMd2iXAaA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UfYvMyUASU0SktOneqY893l+ivwuHLJC4IjYGuuzrdU=; b=jOWmT1PHSUfuER3GIFuGlQl6AAtiS+wpIYEtSckA94lnQlrY+upJIDSDnxradzb9H/ 2/wk3GbkA44UXtFtOgbrf9okp0fzn2UzRmJJYwVPuwX4Y42ECcZmXTQVfjRhvxGpQdUj 9rU1I0NDbOtvOvRJNyBOQ05gv37X4IkYR/ZdDcK0UgnDpQSUH8EVOoOETvDy4sgJORGn RELTMQk5P0AGG9p1PelOUVONeSK/KH+cDBke0aX710dqL2foue44BFiB56JBvNXA8drT 20VxiQfqOVjlzPluGUJe+bP5KRI/yZWunnEJdIYhSLlIizSorWuwL1irTezcxDQaCm+p /Jlg== X-Gm-Message-State: AA+aEWa7BXYzBmH1CUS0WeTSl0GndEzX9fSol3hstYKIelj0pghsq46z D8povWcCS/u8z7lZMztuOGp0 X-Received: by 2002:a65:4784:: with SMTP id e4mr11363289pgs.12.1544463391519; Mon, 10 Dec 2018 09:36:31 -0800 (PST) Received: from localhost.localdomain ([2409:4072:91e:2c01:40e1:a028:b090:9e12]) by smtp.gmail.com with ESMTPSA id q1sm15998396pfb.96.2018.12.10.09.36.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Dec 2018 09:36:30 -0800 (PST) From: Manivannan Sadhasivam To: olof@lixom.net, arnd@arndb.de, robh+dt@kernel.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, daniel.lezcano@linaro.org, gregkh@linuxfoundation.org, jslaby@suse.com Cc: linux-unisoc@lists.infradead.org, afaerber@suse.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, amit.kucheria@linaro.org, linus.walleij@linaro.org, zhao_steven@263.net, Manivannan Sadhasivam Subject: [PATCH v4 03/15] ARM: Prepare RDA8810PL SoC Date: Mon, 10 Dec 2018 23:05:38 +0530 Message-Id: <20181210173550.29643-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181210173550.29643-1-manivannan.sadhasivam@linaro.org> References: <20181210173550.29643-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Andreas Färber Introduce ARCH_RDA and mach-rda for RDA Micro SoCs. Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam --- arch/arm/Kconfig | 2 ++ arch/arm/Makefile | 1 + arch/arm/mach-rda/Kconfig | 9 +++++++++ arch/arm/mach-rda/Makefile | 1 + 4 files changed, 13 insertions(+) create mode 100644 arch/arm/mach-rda/Kconfig create mode 100644 arch/arm/mach-rda/Makefile -- 2.17.1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 91be74d8df65..084f0983e6b2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -804,6 +804,8 @@ source "arch/arm/plat-pxa/Kconfig" source "arch/arm/mach-qcom/Kconfig" +source "arch/arm/mach-rda/Kconfig" + source "arch/arm/mach-realview/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 05a91d8b89f3..10056ccdb8be 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -202,6 +202,7 @@ machine-$(CONFIG_ARCH_ORION5X) += orion5x machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_QCOM) += qcom +machine-$(CONFIG_ARCH_RDA) += rda machine-$(CONFIG_ARCH_REALVIEW) += realview machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc diff --git a/arch/arm/mach-rda/Kconfig b/arch/arm/mach-rda/Kconfig new file mode 100644 index 000000000000..1ea753f57b2d --- /dev/null +++ b/arch/arm/mach-rda/Kconfig @@ -0,0 +1,9 @@ +menuconfig ARCH_RDA + bool "RDA Micro SoCs" + depends on ARCH_MULTI_V7 + select COMMON_CLK + select GENERIC_IRQ_CHIP + select RDA_INTC + select RDA_TIMER + help + This enables support for the RDA Micro 8810PL SoC family. diff --git a/arch/arm/mach-rda/Makefile b/arch/arm/mach-rda/Makefile new file mode 100644 index 000000000000..6bea3d3a2dd7 --- /dev/null +++ b/arch/arm/mach-rda/Makefile @@ -0,0 +1 @@ +obj- += dummy.o From patchwork Mon Dec 10 17:35:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 153321 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3819848ljp; Mon, 10 Dec 2018 09:36:57 -0800 (PST) X-Google-Smtp-Source: AFSGD/X/Qqw4zmc+HVwckE4dPUswpZZxhZVfkYpmxwixOyoQgwn/osdvExYXfMpKnIIHnTa/iGfA X-Received: by 2002:a17:902:3064:: with SMTP id u91mr12651599plb.325.1544463417361; Mon, 10 Dec 2018 09:36:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544463417; cv=none; d=google.com; s=arc-20160816; b=YtceMxwsXuLAHfkJJZzuGsvGAmoAtl++ql4M5wqG4xvn/qJ818YRZXhTjpQE5Fxfj+ uvrrotYOCiZ3hORBWPJe++Q346jwIpAMepOr4SrR9ayT5GAeDNEsKUswabtppLBbvUKV f+/R1JFPJJzMKmIr0k5cMHMvJDuri9y627bnDH9HXPUAp04NtjjHz6iSI+rXkg34FXLX Qj/cHD+ByawnRkQfD4dd1Z8BtrZ1SmNfx3BlUpw4CBNYvf3JDrOAxrcP+DsfN1styD2t 1LGkhWCWBHC7laLYw5B8r4jfMIqs/zCdh5pfkcHwZpLqOqFaUkq7F4ZZ9Yx/nSguFda8 2V3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jBeXaJXIkgLTVAea7CD+4QY6FweZRNu6qTHTVAB8x/Y=; b=v3DDSAfdUjpxc+kWiWl/kQ1YIhzsV7ZUuiIL5vAIVxHT9s8p1to+FCoX23HZ2UENoF 6DkMP5a4iqjDE8KfOhRIbKxXTZzzC0+9mu4fl9xTgMm8Hpe1IoxrZ0rf97RwLV59HQ3q xTIVWb1DnEMEOi5mb2donhwW9aQ1FhKBc0bMVtFsQBrkvmOC7TT+BCy3Xq9n/gcqTbX1 lj5MfJJMQ7WBH5XDZKksEVyggSuLvqF0Ts2T5ysa4+MdcSXzZbk9WDaR3gpW09g8nNOg 2/IyWAzWYBnY1gWEjb3hwV2aQNSbqrmVtZvzdT5QyHJFJrzvD6dWuZ/Cd+BhOWOGci6i mgVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HnWTjtv6; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c1si7585182pld.194.2018.12.10.09.36.57; Mon, 10 Dec 2018 09:36:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HnWTjtv6; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728340AbeLJRg4 (ORCPT + 6 others); Mon, 10 Dec 2018 12:36:56 -0500 Received: from mail-pf1-f194.google.com ([209.85.210.194]:35579 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727283AbeLJRg4 (ORCPT ); Mon, 10 Dec 2018 12:36:56 -0500 Received: by mail-pf1-f194.google.com with SMTP id z9so5734685pfi.2 for ; Mon, 10 Dec 2018 09:36:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jBeXaJXIkgLTVAea7CD+4QY6FweZRNu6qTHTVAB8x/Y=; b=HnWTjtv6Hy7K1s4CYLo0CNcASjpB/ucXs+JDazjHumFysvFqK+VJ8QJWG1urZqaYjt Y0afPttIx8MIBlO/YhK5H0I0R0rKCJkRuKDTyP6KaboVBdzD6WwvGny6ncV5PmcmUjnz wDw+4l/6qUiEcd1nEANt24gSD+Rqcm5Y1pUQk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jBeXaJXIkgLTVAea7CD+4QY6FweZRNu6qTHTVAB8x/Y=; b=cvjwu59emi2JaiL/YleBFe0eYVo8Td5cvMUcWVUir9AxlpsM9vXiROvP28ZbEBpjcT CyI0BOLWzSc5rwYiq/AbDEviTz6PS0cHLVrGo1XA/Nn29o0IhUm2y+VHMH9gPl1X4xRx r3ZFlvP0Yu7/puz2MOPds5b7P3CQOrAY0emqVpXgHPFR3thokTyq3F+wSUUOX8jC+2Ce okDlpgSqag2dkzRPJoDGDd88p0F9GQn0zm682+GQb2rlDMe/oEEJsAxA2Gv9XWW3VNWH 6LaVenaNOJIpU5bSgp1o3A6h/r2niJFyco5yyFGcni8ZLp315+drBK3gZq88cxC57xC1 /oyg== X-Gm-Message-State: AA+aEWby53TmJLBbdeGsuJEgzpVtKNBytxmUJb7dLIY/JSyOowP1iuow UO2sXbZHI3GfqNFgy4N7AV5k X-Received: by 2002:a63:6c48:: with SMTP id h69mr11056458pgc.139.1544463415247; Mon, 10 Dec 2018 09:36:55 -0800 (PST) Received: from localhost.localdomain ([2409:4072:91e:2c01:40e1:a028:b090:9e12]) by smtp.gmail.com with ESMTPSA id q1sm15998396pfb.96.2018.12.10.09.36.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Dec 2018 09:36:54 -0800 (PST) From: Manivannan Sadhasivam To: olof@lixom.net, arnd@arndb.de, robh+dt@kernel.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, daniel.lezcano@linaro.org, gregkh@linuxfoundation.org, jslaby@suse.com Cc: linux-unisoc@lists.infradead.org, afaerber@suse.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, amit.kucheria@linaro.org, linus.walleij@linaro.org, zhao_steven@263.net, Manivannan Sadhasivam Subject: [PATCH v4 06/15] ARM: dts: Add devicetree for OrangePi 2G IoT board Date: Mon, 10 Dec 2018 23:05:41 +0530 Message-Id: <20181210173550.29643-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181210173550.29643-1-manivannan.sadhasivam@linaro.org> References: <20181210173550.29643-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial devicetree support for OrangePi 2G IoT board from Xunlong. Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/rda8810pl-orangepi-2g-iot.dts | 50 +++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts -- 2.17.1 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..a0fdad8f10dd 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -806,6 +806,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8974-sony-xperia-castor.dtb \ qcom-msm8974-sony-xperia-honami.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb +dtb-$(CONFIG_ARCH_RDA) += \ + rda8810pl-orangepi-2g-iot.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ arm-realview-pb11mp.dtb \ diff --git a/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts b/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts new file mode 100644 index 000000000000..98e34248ae80 --- /dev/null +++ b/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +/dts-v1/; + +#include "rda8810pl.dtsi" + +/ { + compatible = "xunlong,orangepi-2g-iot", "rda,8810pl"; + model = "Orange Pi 2G-IoT"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + chosen { + stdout-path = "serial2:921600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&uart1 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart2 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart3 { + status = "okay"; + clocks = <&uart_clk>; +}; From patchwork Mon Dec 10 17:35:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 153323 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3820107ljp; Mon, 10 Dec 2018 09:37:14 -0800 (PST) X-Google-Smtp-Source: AFSGD/X00k8HxCJTb/Huktaw/d6JLE2oCjm5hg5XVCBXAuRIn89+S3tKdwoLjrPmrR3Og5YOUbtV X-Received: by 2002:a62:61c3:: with SMTP id v186mr13267268pfb.55.1544463434694; Mon, 10 Dec 2018 09:37:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544463434; cv=none; d=google.com; s=arc-20160816; b=KIOyZh8DhVKjUJ3e2sVg1oEdW7k4EHaJEbKe2ntroph1zXGqtm8J5tMoX8M2ko9f+K 8+3wDEj61VGYWNaJ11KBShPeHmQGdsLOUUji5tWn0fsMB6QP9uTFPh32V25qrh7K0F1C SOwYVAr49qgnke/MqEnLHBeOoH3AZaWnWHkVsSI5h0g4YH6RSLhC/RP6sJwusNGYJHrd QG2ScxyDRZX4Sqydq9ZGap6+SMv0su3+wYJ4XAJZ9vTjYjUqkn9F0K4r4kpRxw54D97D PuWIk2y0+FG//ZgYKvivOGFnzi0Ci8VIwFA0rdodQ1q3yIqH39Qg8zuksGXbInUAJ7jP zTOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=paserLSWvruKGRH0unlQrwzFxeUOtATxgj85HiPjRLo=; b=k90MuzGkgyOCGGanjbA7lrOs8b1d7vccBkrfb9lKAjlguognCihcnJHrRTQewvRLYy KTjhKx71dRfa68NvGu8Y+Ixchue79f5IdH5Lcpqv1TCWP4QYvCESiThoiOAG2gOtWeNU ktGdYb0tArynMq89sdPIU/e1xnYpEjR85O42Xddjs4uvCsI89BrW+QZolCTThQk702VU JNL6dx98ICg/XQ5tuFagghuBFHfy9aXMDiZJcyeuEq0hZK2htAbumebIKvPPHm8u5o2k WKnh5zNGurQDgqxcEVSyL5Imek8Ue3M/OC5krCstse4d7gTX6QqLz9cGIMq/2o9GMaqJ 3FFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iZpnl14W; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 90si10721181plb.17.2018.12.10.09.37.14; Mon, 10 Dec 2018 09:37:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iZpnl14W; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728429AbeLJRhO (ORCPT + 6 others); Mon, 10 Dec 2018 12:37:14 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:40426 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727027AbeLJRhN (ORCPT ); Mon, 10 Dec 2018 12:37:13 -0500 Received: by mail-pf1-f193.google.com with SMTP id i12so5720045pfo.7 for ; Mon, 10 Dec 2018 09:37:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=paserLSWvruKGRH0unlQrwzFxeUOtATxgj85HiPjRLo=; b=iZpnl14WwP9SdRZH4erTHT7deFkt2RjnMbDpJ7WRsJGa7rMQkb+o/6r/P5nMTerDzC bIwCSSHOQ8gbZz16ld5veLJRKT/8bA5cKyHQRKt0FV8E0YtEqSw0ESufDCNPiv7sReCO Z+m5eurMsOQzdDc/+/7R/tzFThc/fhDfspPwI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=paserLSWvruKGRH0unlQrwzFxeUOtATxgj85HiPjRLo=; b=rXTOaLhHjiQXF79DprK7meMBy6A/F4so8QF+veBr1OUYnVF4+c3Mt0qC/iSfwXnw4D k77AVf23dNChKSTAYIwnJarqXIgmuxVHfleVWkPfBuH4PuVhQR4tak+xoIb3kkE+trgf znJ6/TqkMMEj1wEA3597qi6Q9iwMawKPPHgngVY1lC2wpavxe7ZMDchJhMupxhRV/T9e kZm7pw2YBEh46ZBBweSkSq1jZ8YiVFdQTgARJF+d9LW3XIGuoxSAhwYFMskoX8mTXK5y hKpb5vJMKklydb3bT2Y/CwmoC2wG4v9P47lyWh0x8MlriBQFfl3aSYwCblWxJMfwHK6n tEaQ== X-Gm-Message-State: AA+aEWZVtdu4a4nydU+yGG006DHQJS15MogSP27QU0hyuErpcz4ho+Ti WopvU8QQCKZLgA82j/3E2H1i X-Received: by 2002:a62:435a:: with SMTP id q87mr12968140pfa.109.1544463432829; Mon, 10 Dec 2018 09:37:12 -0800 (PST) Received: from localhost.localdomain ([2409:4072:91e:2c01:40e1:a028:b090:9e12]) by smtp.gmail.com with ESMTPSA id q1sm15998396pfb.96.2018.12.10.09.37.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Dec 2018 09:37:12 -0800 (PST) From: Manivannan Sadhasivam To: olof@lixom.net, arnd@arndb.de, robh+dt@kernel.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, daniel.lezcano@linaro.org, gregkh@linuxfoundation.org, jslaby@suse.com Cc: linux-unisoc@lists.infradead.org, afaerber@suse.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, amit.kucheria@linaro.org, linus.walleij@linaro.org, zhao_steven@263.net, Manivannan Sadhasivam Subject: [PATCH v4 08/15] irqchip: Add RDA8810PL interrupt driver Date: Mon, 10 Dec 2018 23:05:43 +0530 Message-Id: <20181210173550.29643-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181210173550.29643-1-manivannan.sadhasivam@linaro.org> References: <20181210173550.29643-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add interrupt driver for RDA Micro RDA8810PL SoC. Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam Reviewed-by: Marc Zyngier --- drivers/irqchip/Kconfig | 4 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-rda-intc.c | 107 +++++++++++++++++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 drivers/irqchip/irq-rda-intc.c -- 2.17.1 diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 51a5ef0e96ed..9d54645870ad 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -195,6 +195,10 @@ config JCORE_AIC help Support for the J-Core integrated AIC. +config RDA_INTC + bool + select IRQ_DOMAIN + config RENESAS_INTC_IRQPIN bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 794c13d3ac3d..417108027e40 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o +obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o diff --git a/drivers/irqchip/irq-rda-intc.c b/drivers/irqchip/irq-rda-intc.c new file mode 100644 index 000000000000..1176291fdef8 --- /dev/null +++ b/drivers/irqchip/irq-rda-intc.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RDA8810PL SoC irqchip driver + * + * Copyright RDA Microelectronics Company Limited + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define RDA_INTC_FINALSTATUS 0x00 +#define RDA_INTC_MASK_SET 0x08 +#define RDA_INTC_MASK_CLR 0x0c + +#define RDA_IRQ_MASK_ALL 0xFFFFFFFF + +#define RDA_NR_IRQS 32 + +static void __iomem *rda_intc_base; +static struct irq_domain *rda_irq_domain; + +static void rda_intc_mask_irq(struct irq_data *d) +{ + writel_relaxed(BIT(d->hwirq), rda_intc_base + RDA_INTC_MASK_CLR); +} + +static void rda_intc_unmask_irq(struct irq_data *d) +{ + writel_relaxed(BIT(d->hwirq), rda_intc_base + RDA_INTC_MASK_SET); +} + +static int rda_intc_set_type(struct irq_data *data, unsigned int flow_type) +{ + /* Hardware supports only level triggered interrupts */ + if ((flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) == flow_type) + return 0; + + return -EINVAL; +} + +static void __exception_irq_entry rda_handle_irq(struct pt_regs *regs) +{ + u32 stat = readl_relaxed(rda_intc_base + RDA_INTC_FINALSTATUS); + u32 hwirq; + + while (stat) { + hwirq = __fls(stat); + handle_domain_irq(rda_irq_domain, hwirq, regs); + stat &= ~BIT(hwirq); + } +} + +static struct irq_chip rda_irq_chip = { + .name = "rda-intc", + .irq_mask = rda_intc_mask_irq, + .irq_unmask = rda_intc_unmask_irq, + .irq_set_type = rda_intc_set_type, +}; + +static int rda_irq_map(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hw) +{ + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &rda_irq_chip, handle_level_irq); + irq_set_chip_data(virq, d->host_data); + irq_set_probe(virq); + + return 0; +} + +static const struct irq_domain_ops rda_irq_domain_ops = { + .map = rda_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int __init rda8810_intc_init(struct device_node *node, + struct device_node *parent) +{ + rda_intc_base = of_io_request_and_map(node, 0, "rda-intc"); + if (!rda_intc_base) + return -ENXIO; + + /* Mask all interrupt sources */ + writel_relaxed(RDA_IRQ_MASK_ALL, rda_intc_base + RDA_INTC_MASK_CLR); + + rda_irq_domain = irq_domain_create_linear(&node->fwnode, RDA_NR_IRQS, + &rda_irq_domain_ops, + rda_intc_base); + if (!rda_irq_domain) { + iounmap(rda_intc_base); + return -ENOMEM; + } + + set_handle_irq(rda_handle_irq); + + return 0; +} + +IRQCHIP_DECLARE(rda_intc, "rda,8810pl-intc", rda8810_intc_init); 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[209.132.180.67]) by mx.google.com with ESMTP id 194si9854774pgg.519.2018.12.10.09.37.40; Mon, 10 Dec 2018 09:37:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g5HmWjAE; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727894AbeLJRhk (ORCPT + 6 others); Mon, 10 Dec 2018 12:37:40 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:44208 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727225AbeLJRhk (ORCPT ); Mon, 10 Dec 2018 12:37:40 -0500 Received: by mail-pl1-f195.google.com with SMTP id k8so5554384pls.11 for ; Mon, 10 Dec 2018 09:37:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JCZeYyk0+yspspvMdnmBGZjX8Hgu2eUCGweRtMM/T5I=; b=g5HmWjAE8pU2W4hrzwBChYUnt5p/p+AJzKXCj59ZyA/k3Kn6Qrp3MpWW03hPL593Y5 mbgQyD2ozLhVBXfgfdK1cf0/uqandg+2DQ01bNogUQROvQFm5fGGRsd8Yh5DZKC+amCF B8YCOvszK2m4okgBqMcIfNcSOgZ3sTkb6x558= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JCZeYyk0+yspspvMdnmBGZjX8Hgu2eUCGweRtMM/T5I=; b=iv8uO/eLVNv1QBrlExTVRBkvPsxLY421p6yuYu+QvhOFOVs0dX+VDhc5ZIshZSB89R pjsoS7nGqDJf4AgpWxqPxYXKIWkDbJiK/SDd88sX+jsiAB6nol7mQFMp0qT3HhMkfFhN haX0jXhTaLLljxCZmOoacpcL7mT2wneYdMjLYgtBq96L8oLxRqSP5MoR5zYKv3pCGw59 z6PqgkXv0NZu8YciZmH7goIIPQTlKPVZmsZt1V9HLQiaQU8ORm1HtC92jobrv0wyi1aI GVqgIbmv29vDZCO/GW+lGoGcfH23La0eviy0AFoU+c2dlCVp4rVO7h/pc9UQkakYlABc 8Ntw== X-Gm-Message-State: AA+aEWYkepUQ+4IsQT+IS9fFuJpYtpVUnvavj6MBbHSqJ9W6vYuPytw9 10zGup+vB0OSh/fHk6087P/Y X-Received: by 2002:a17:902:12b:: with SMTP id 40mr12664123plb.72.1544463459097; Mon, 10 Dec 2018 09:37:39 -0800 (PST) Received: from localhost.localdomain ([2409:4072:91e:2c01:40e1:a028:b090:9e12]) by smtp.gmail.com with ESMTPSA id q1sm15998396pfb.96.2018.12.10.09.37.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Dec 2018 09:37:38 -0800 (PST) From: Manivannan Sadhasivam To: olof@lixom.net, arnd@arndb.de, robh+dt@kernel.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, daniel.lezcano@linaro.org, gregkh@linuxfoundation.org, jslaby@suse.com Cc: linux-unisoc@lists.infradead.org, afaerber@suse.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, amit.kucheria@linaro.org, linus.walleij@linaro.org, zhao_steven@263.net, Manivannan Sadhasivam Subject: [PATCH v4 11/15] clocksource: Add clock driver for RDA8810PL SoC Date: Mon, 10 Dec 2018 23:05:46 +0530 Message-Id: <20181210173550.29643-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181210173550.29643-1-manivannan.sadhasivam@linaro.org> References: <20181210173550.29643-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add clock driver for RDA Micro RDA8810PL SoC supporting OSTIMER and HWTIMER. RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER (64 bit). Each timer provides optional interrupt support. In this driver, OSTIMER is used for clockevents and HWTIMER is used for clocksource. Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam --- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-rda.c | 195 ++++++++++++++++++++++++++++++++ 3 files changed, 204 insertions(+) create mode 100644 drivers/clocksource/timer-rda.c -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 55c77e44bb2d..598b592e03d7 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -105,6 +105,14 @@ config OWL_TIMER help Enables the support for the Actions Semi Owl timer driver. +config RDA_TIMER + bool "RDA timer driver" if COMPILE_TEST + depends on GENERIC_CLOCKEVENTS + select CLKSRC_MMIO + select TIMER_OF + help + Enables the support for the RDA Micro timer driver. + config SUN4I_TIMER bool "Sun4i timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dd9138104568..150020a90707 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += timer-owl.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o +obj-$(CONFIG_RDA_TIMER) += timer-rda.o obj-$(CONFIG_ARC_TIMERS) += arc_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o diff --git a/drivers/clocksource/timer-rda.c b/drivers/clocksource/timer-rda.c new file mode 100644 index 000000000000..fd1199c189bf --- /dev/null +++ b/drivers/clocksource/timer-rda.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RDA8810PL SoC timer driver + * + * Copyright RDA Microelectronics Company Limited + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + * + * RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER (64 bit). + * Each timer provides optional interrupt support. In this driver, OSTIMER is + * used for clockevents and HWTIMER is used for clocksource. + */ + +#include +#include + +#include "timer-of.h" + +#define RDA_OSTIMER_LOADVAL_L 0x000 +#define RDA_OSTIMER_CTRL 0x004 +#define RDA_HWTIMER_LOCKVAL_L 0x024 +#define RDA_HWTIMER_LOCKVAL_H 0x028 +#define RDA_TIMER_IRQ_MASK_SET 0x02c +#define RDA_TIMER_IRQ_MASK_CLR 0x030 +#define RDA_TIMER_IRQ_CLR 0x034 + +#define RDA_OSTIMER_CTRL_ENABLE BIT(24) +#define RDA_OSTIMER_CTRL_REPEAT BIT(28) +#define RDA_OSTIMER_CTRL_LOAD BIT(30) + +#define RDA_TIMER_IRQ_MASK_OSTIMER BIT(0) + +#define RDA_TIMER_IRQ_CLR_OSTIMER BIT(0) + +static int rda_ostimer_start(void __iomem *base, bool periodic, u64 cycles) +{ + u32 ctrl, load_l; + + load_l = (u32)cycles; + ctrl = ((cycles >> 32) & 0xffffff); + ctrl |= RDA_OSTIMER_CTRL_LOAD | RDA_OSTIMER_CTRL_ENABLE; + if (periodic) + ctrl |= RDA_OSTIMER_CTRL_REPEAT; + + /* Enable ostimer interrupt first */ + writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER, + base + RDA_TIMER_IRQ_MASK_SET); + + /* Write low 32 bits first, high 24 bits are with ctrl */ + writel_relaxed(load_l, base + RDA_OSTIMER_LOADVAL_L); + writel_relaxed(ctrl, base + RDA_OSTIMER_CTRL); + + return 0; +} + +static int rda_ostimer_stop(void __iomem *base) +{ + /* Disable ostimer interrupt first */ + writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER, + base + RDA_TIMER_IRQ_MASK_CLR); + + writel_relaxed(0, base + RDA_OSTIMER_CTRL); + + return 0; +} + +static int rda_ostimer_set_state_shutdown(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + + rda_ostimer_stop(timer_of_base(to)); + + return 0; +} + +static int rda_ostimer_set_state_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + + rda_ostimer_stop(timer_of_base(to)); + + return 0; +} + +static int rda_ostimer_set_state_periodic(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + unsigned long cycles_per_jiffy; + + rda_ostimer_stop(timer_of_base(to)); + + cycles_per_jiffy = ((unsigned long long)NSEC_PER_SEC / HZ * + evt->mult) >> evt->shift; + rda_ostimer_start(timer_of_base(to), true, cycles_per_jiffy); + + return 0; +} + +static int rda_ostimer_tick_resume(struct clock_event_device *evt) +{ + return 0; +} + +static int rda_ostimer_set_next_event(unsigned long evt, + struct clock_event_device *ev) +{ + struct timer_of *to = to_timer_of(ev); + + rda_ostimer_start(timer_of_base(to), false, evt); + + return 0; +} + +static irqreturn_t rda_ostimer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + struct timer_of *to = to_timer_of(evt); + + /* clear timer int */ + writel_relaxed(RDA_TIMER_IRQ_CLR_OSTIMER, + timer_of_base(to) + RDA_TIMER_IRQ_CLR); + + if (evt->event_handler) + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct timer_of rda_ostimer_of = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE, + + .clkevt = { + .name = "rda-ostimer", + .rating = 250, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_DYNIRQ, + .set_state_shutdown = rda_ostimer_set_state_shutdown, + .set_state_oneshot = rda_ostimer_set_state_oneshot, + .set_state_periodic = rda_ostimer_set_state_periodic, + .tick_resume = rda_ostimer_tick_resume, + .set_next_event = rda_ostimer_set_next_event, + }, + + .of_base = { + .name = "rda-timer", + .index = 0, + }, + + .of_irq = { + .name = "ostimer", + .handler = rda_ostimer_interrupt, + .flags = IRQF_TIMER, + }, +}; + +static u64 rda_hwtimer_read(struct clocksource *cs) +{ + void __iomem *base = timer_of_base(&rda_ostimer_of); + u32 lo, hi; + + /* Always read low 32 bits first */ + do { + lo = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_L); + hi = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H); + } while (hi != readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H)); + + return ((u64)hi << 32) | lo; +} + +static struct clocksource rda_hwtimer_clocksource = { + .name = "rda-timer", + .rating = 400, + .read = rda_hwtimer_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init rda_timer_init(struct device_node *np) +{ + unsigned long rate = 2000000; + int ret; + + ret = timer_of_init(np, &rda_ostimer_of); + if (ret) + return ret; + + clocksource_register_hz(&rda_hwtimer_clocksource, rate); + + clockevents_config_and_register(&rda_ostimer_of.clkevt, rate, + 0x2, UINT_MAX); + + return 0; +} + +TIMER_OF_DECLARE(rda8810pl, "rda,8810pl-timer", rda_timer_init);