From patchwork Tue Mar 29 15:24:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 555094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DE91C4332F for ; Tue, 29 Mar 2022 15:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238506AbiC2P0V (ORCPT ); Tue, 29 Mar 2022 11:26:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238509AbiC2P0U (ORCPT ); Tue, 29 Mar 2022 11:26:20 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [217.70.178.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B07286832A; Tue, 29 Mar 2022 08:24:36 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 37B2F100013; Tue, 29 Mar 2022 15:24:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1648567475; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rj7Uv5KpYPfT/JU1QhG/jND0Kkn1n5NDASFhET19Mjc=; b=DstsxuiVQhW6WhNe6kZSiTzrZn91xOGjqM3lJKAE9sLvw4OH0/eNx7jqHH7wIfmMRARogE k58BC6ZlO4EQnM9oMj9wzyEiJeAx5vHeOczI27ErxFdyY0HpvILHwpCumLQhyxqUHGVbB3 n0d0ts3S1QFruHN4c4Iby9DgHO1Dp1T7aFRB1KaFVSZ/ELVSV/ouEokZc+AYVFCX6iKo+z 9FQzMGB8AdfNhL5kdpOU7RIJJYRRWSc6PnmTvbEMpdR5OuFLru2tlBhazXErAFXBdZsIyl xHMzBHdiMehh2btgM08YDG8V9bNJkLhL/4T7gcaMp5Jr5x89dFeMybSkya3BIw== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Phil Edworthy Subject: [PATCH v3 01/10] serial: 8250: dw: Move the per-device structure Date: Tue, 29 Mar 2022 17:24:21 +0200 Message-Id: <20220329152430.756947-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220329152430.756947-1-miquel.raynal@bootlin.com> References: <20220329152430.756947-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Phil Edworthy This structure needs to be reused from dwlib, so let's move it into a shared header. There is no functional change. Signed-off-by: Phil Edworthy [miquel.raynal@bootlin.com: Extracted from a bigger change] Signed-off-by: Miquel Raynal --- drivers/tty/serial/8250/8250_dw.c | 16 ---------------- drivers/tty/serial/8250/8250_dwlib.h | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 96a62e95726b..d89731d6c94c 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -42,22 +42,6 @@ #define DW_UART_QUIRK_ARMADA_38X BIT(1) #define DW_UART_QUIRK_SKIP_SET_RATE BIT(2) -struct dw8250_data { - struct dw8250_port_data data; - - u8 usr_reg; - int msr_mask_on; - int msr_mask_off; - struct clk *clk; - struct clk *pclk; - struct notifier_block clk_notifier; - struct work_struct clk_work; - struct reset_control *rst; - - unsigned int skip_autocfg:1; - unsigned int uart_16550_compatible:1; -}; - static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) { return container_of(data, struct dw8250_data, data); diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h index 83d528e5cc21..e973f804c2f4 100644 --- a/drivers/tty/serial/8250/8250_dwlib.h +++ b/drivers/tty/serial/8250/8250_dwlib.h @@ -1,10 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* Synopsys DesignWare 8250 library header file. */ +#include #include +#include #include "8250.h" +struct clk; +struct reset_control; + struct dw8250_port_data { /* Port properties */ int line; @@ -16,5 +21,21 @@ struct dw8250_port_data { u8 dlf_size; }; +struct dw8250_data { + struct dw8250_port_data data; + + u8 usr_reg; + int msr_mask_on; + int msr_mask_off; + struct clk *clk; + struct clk *pclk; + struct notifier_block clk_notifier; + struct work_struct clk_work; + struct reset_control *rst; + + unsigned int skip_autocfg:1; + unsigned int uart_16550_compatible:1; +}; + void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old); void dw8250_setup_port(struct uart_port *p); From patchwork Tue Mar 29 15:24:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 555093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10014C433EF for ; Tue, 29 Mar 2022 15:24:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238516AbiC2P0d (ORCPT ); Tue, 29 Mar 2022 11:26:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238524AbiC2P0Y (ORCPT ); Tue, 29 Mar 2022 11:26:24 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [IPv6:2001:4b98:dc4:8::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 666806949D; Tue, 29 Mar 2022 08:24:40 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 37F89100015; Tue, 29 Mar 2022 15:24:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1648567479; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yOgHMD+FKdOx4v/F+hsB7NfXbZyTvDjo+nCDRmBoyZI=; b=IpYBj8NTUEO0CYvF0EBZAJHiHRBECO1Ij3+UHVb8H2kYJ4rQF9Be4oVqxtFH0rlCASiMTW xDJf8QJLR1mmomUiFvHfZk0TJ+Ah1wgrR+OrbCfnaUXC0yfBwkl2WzD5wSJaQOkD2I7moT mIsJ4uX35gEEQhx+RbICnAvxORag/Dn0o1KkFCeV19rXY7R1no7sW67K7x17F1RvgYlR2l cxdCZ+ArEjzHV7ZLNVJR0evLBho8qa6Vj51c2AHQR9tkhJLAByi8eIO1lO4/9y6ppO2c/k bRKqd+hM4rpeU1TNsxRlnVgKxShV+aWjBRUT8ghuYzIuZtzvYyzbscfBufjJ6g== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger Subject: [PATCH v3 03/10] serial: 8250: dw: Change the quirks type to unsigned int Date: Tue, 29 Mar 2022 17:24:23 +0200 Message-Id: <20220329152430.756947-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220329152430.756947-1-miquel.raynal@bootlin.com> References: <20220329152430.756947-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Unsigned int is better than unsigned long as its size does not change between setups and we don't really need this variable to be more than a few bits wide for now. Suggested-by: Suggested-by: Andy Shevchenko Signed-off-by: Miquel Raynal --- drivers/tty/serial/8250/8250_dw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 28f0dea2ed88..20c9ca03225b 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -376,7 +376,7 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param) static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) { struct device_node *np = p->dev->of_node; - unsigned long quirks = (unsigned long)device_get_match_data(p->dev); + unsigned int quirks = (unsigned int)device_get_match_data(p->dev); if (np) { int id; From patchwork Tue Mar 29 15:24:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 555092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A89AC433FE for ; Tue, 29 Mar 2022 15:25:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238552AbiC2P0o (ORCPT ); Tue, 29 Mar 2022 11:26:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238527AbiC2P0f (ORCPT ); Tue, 29 Mar 2022 11:26:35 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [IPv6:2001:4b98:dc4:8::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C3FC69736; Tue, 29 Mar 2022 08:24:45 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 207E5100004; Tue, 29 Mar 2022 15:24:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1648567483; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bqlxbaPb3hKljw05W+FxwFvbnmrcIPn1a8uATNz0GAM=; b=SOgHMXqk/XcDhc7Kk0YAGYcqZaM2HluoVMTUawslxL8NlalVwVJVr1lwzV0hNpTldXkejb EIA2uA5ndG18glEr7Wz4wBflKdRp83UC7Y7DZk6WRkcqb5A1cbmzB9nQeHVc57Yc38P1CC b8aLTQPcs8IxuBcSTBV+QdMCdc9HVLojEUWScay1ZueTXgOxOZcEow6VdzhbmHdj/uLqIs CrMMfJlzU/niKtx9pHsXxxqt9OMlfzS+nswjDG8HVrkkK+USdJY4LhJ2Z3YRn0+tVwyEBL eBiOoCWdg2LjuYjZI+uLnR0wX3criYm4OGjTXomZwfSLFTKMB21oMJ31mL8LOQ== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Phil Edworthy Subject: [PATCH v3 05/10] serial: 8250: dw: Allow to use a fallback CPR value if not synthesized Date: Tue, 29 Mar 2022 17:24:25 +0200 Message-Id: <20220329152430.756947-6-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220329152430.756947-1-miquel.raynal@bootlin.com> References: <20220329152430.756947-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org DW UART controllers can be synthesized without the CPR register. In this case, allow to the platform information to provide a CPR value. Signed-off-by: Phil Edworthy Co-developed-by: Miquel Raynal Signed-off-by: Miquel Raynal --- drivers/tty/serial/8250/8250_dwlib.c | 9 +++++++++ drivers/tty/serial/8250/8250_dwlib.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c index 622d3b0d89e7..6c4fe1792eb5 100644 --- a/drivers/tty/serial/8250/8250_dwlib.c +++ b/drivers/tty/serial/8250/8250_dwlib.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include @@ -90,6 +91,7 @@ EXPORT_SYMBOL_GPL(dw8250_do_set_termios); void dw8250_setup_port(struct uart_port *p) { struct uart_8250_port *up = up_to_u8250p(p); + const struct dw8250_platform_data *pdata = device_get_match_data(p->dev); u32 reg; /* @@ -116,6 +118,13 @@ void dw8250_setup_port(struct uart_port *p) } reg = dw8250_readl_ext(p, DW_UART_CPR); + if (!reg) { + if (pdata) + reg = pdata->cpr; + + dev_dbg(p->dev, "CPR is not available, using %x instead\n", reg); + } + if (!reg) return; diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h index 7dfc2d6361e5..19c530b7fd1d 100644 --- a/drivers/tty/serial/8250/8250_dwlib.h +++ b/drivers/tty/serial/8250/8250_dwlib.h @@ -23,6 +23,7 @@ struct dw8250_port_data { struct dw8250_platform_data { unsigned int quirks; + u32 cpr; }; struct dw8250_data { From patchwork Tue Mar 29 15:24:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 555091 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3B18C433FE for ; Tue, 29 Mar 2022 15:25:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238526AbiC2P0t (ORCPT ); Tue, 29 Mar 2022 11:26:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238540AbiC2P0n (ORCPT ); Tue, 29 Mar 2022 11:26:43 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [IPv6:2001:4b98:dc4:8::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E85466D1AA; Tue, 29 Mar 2022 08:24:50 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id F104E100004; Tue, 29 Mar 2022 15:24:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1648567489; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=I4tsb4DvupL2PdeGqnx8nJ59NL6Tm1pUPj8EJLdCtWg=; b=MueszkSrybiB8Fz0+6gRDkYMrY+0wj+aXc0NCVq5chARymCUrdg5vhT1M3soKXrs30/FuI V/qIU4QS6ewKfCn0tUjRQi7joN2nzjr72g6DNvW5gfTT3CeI6gPYOcFHXdROZy2B4qQDSC 381duwLUasdP7o2/yDFf2cTaHjGH247y3Pq6okG1HOO+Jq6wbp/R0Jup4MUTqCtTQUMX/J YJIspZv5hXlVoI2oP70tXIwfUeicn55G1B6f1jje9wLMWgXkl3XhEzcD9qFc7mOChRuL4P A30vsb6lsZThGtJlOIO9mhReaq5ml4FqlJtWDdiyRPo82AU/AmX8YIKavwsCUw== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Phil Edworthy Subject: [PATCH v3 08/10] serial: 8250: dw: Add support for DMA flow controlling devices Date: Tue, 29 Mar 2022 17:24:28 +0200 Message-Id: <20220329152430.756947-9-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220329152430.756947-1-miquel.raynal@bootlin.com> References: <20220329152430.756947-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Phil Edworthy DW based controllers like the one on Renesas RZ/N1 must be programmed as flow controllers when using DMA. * Table 11.45 of the system manual, "Flow Control Combinations", states that using UART with DMA requires setting the DMA in the peripheral flow controller mode regardless of the direction. * Chapter 11.6.1.3 of the system manual, "Basic Interface Definitions", explains that the burst size in the above case must be configured in the peripheral's register DEST/SRC_BURST_SIZE. Experiments shown that upon Rx timeout, the DMA transaction needed to be manually cleared as well. Signed-off-by: Phil Edworthy Co-developed-by: Miquel Raynal Signed-off-by: Miquel Raynal --- drivers/tty/serial/8250/8250_dw.c | 64 +++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 1a6932d69332..af9fcc77ee76 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -34,14 +34,25 @@ /* Offsets for the DesignWare specific registers */ #define DW_UART_USR 0x1f /* UART Status Register */ +#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ +#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ +#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ /* DesignWare specific register fields */ #define DW_UART_MCR_SIRE BIT(6) +/* Renesas specific register fields */ +#define RZN1_UART_xDMACR_DMA_EN BIT(0) +#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1) +#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1) +#define RZN1_UART_xDMACR_8_WORD_BURST (3 << 1) +#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3) + /* Quirks */ #define DW_UART_QUIRK_OCTEON BIT(0) #define DW_UART_QUIRK_ARMADA_38X BIT(1) #define DW_UART_QUIRK_SKIP_SET_RATE BIT(2) +#define DW_UART_QUIRK_IS_DMA_FLOW_CONTROLLER BIT(3) static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) { @@ -225,6 +236,7 @@ static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) static int dw8250_handle_irq(struct uart_port *p) { + const struct dw8250_platform_data *pdata = device_get_match_data(p->dev); struct uart_8250_port *up = up_to_u8250p(p); struct dw8250_data *d = to_dw8250_data(p->private_data); unsigned int iir = p->serial_in(p, UART_IIR); @@ -252,6 +264,16 @@ static int dw8250_handle_irq(struct uart_port *p) spin_unlock_irqrestore(&p->lock, flags); } + /* Manually stop the Rx DMA transfer when acting as flow controller */ + if (up->dma && up->dma->rx_running && rx_timeout && pdata && + pdata->quirks & DW_UART_QUIRK_IS_DMA_FLOW_CONTROLLER) { + status = p->serial_in(p, UART_LSR); + if (status & (UART_LSR_DR | UART_LSR_BI)) { + writel(0, p->membase + RZN1_UART_RDMACR); + writel(1, p->membase + DW_UART_DMASA); + } + } + if (serial8250_handle_irq(p, iir)) return 1; @@ -375,6 +397,42 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param) return param == chan->device->dev; } +static u32 dw8250_rzn1_get_dmacr_burst(int max_burst) +{ + if (max_burst >= 8) + return RZN1_UART_xDMACR_8_WORD_BURST; + else if (max_burst >= 4) + return RZN1_UART_xDMACR_4_WORD_BURST; + else + return RZN1_UART_xDMACR_1_WORD_BURST; +} + +static void dw8250_prepare_tx_dma(struct uart_8250_port *p) +{ + struct uart_port *up = &p->port; + struct uart_8250_dma *dma = p->dma; + u32 val; + + writel(0, up->membase + RZN1_UART_TDMACR); + val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) | + RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) | + RZN1_UART_xDMACR_DMA_EN; + writel(val, up->membase + RZN1_UART_TDMACR); +} + +static void dw8250_prepare_rx_dma(struct uart_8250_port *p) +{ + struct uart_port *up = &p->port; + struct uart_8250_dma *dma = p->dma; + u32 val; + + writel(0, up->membase + RZN1_UART_RDMACR); + val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) | + RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) | + RZN1_UART_xDMACR_DMA_EN; + writel(val, up->membase + RZN1_UART_RDMACR); +} + static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) { struct device_node *np = p->dev->of_node; @@ -409,6 +467,12 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) p->serial_out = dw8250_serial_out38x; if (quirks & DW_UART_QUIRK_SKIP_SET_RATE) p->set_termios = dw8250_do_set_termios; + if (quirks & DW_UART_QUIRK_IS_DMA_FLOW_CONTROLLER) { + data->data.dma.txconf.device_fc = 1; + data->data.dma.rxconf.device_fc = 1; + data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma; + data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma; + } } else if (acpi_dev_present("APMC0D08", NULL, -1)) { p->iotype = UPIO_MEM32; From patchwork Tue Mar 29 15:24:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 555090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49112C4332F for ; Tue, 29 Mar 2022 15:25:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238561AbiC2P1A (ORCPT ); Tue, 29 Mar 2022 11:27:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238543AbiC2P0n (ORCPT ); Tue, 29 Mar 2022 11:26:43 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [217.70.178.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20CE8694BC; Tue, 29 Mar 2022 08:24:52 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id C08A010000E; Tue, 29 Mar 2022 15:24:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1648567491; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bdmrb1IRZraVgtf2kJEClbv+BN6v8+ptDaZlkUI1uL4=; b=ooz480BI8vR6MdBXw/ZMa3IDPRssejSkPYWYj8R/ZWn0yXIbwtO5GjSnIfIgwqomC18O9v fTBvo98iXrN38UGdbjFr5pRPuS6gPbKlJZ29uU8RxHhdDNWklufadZkRbKyRXxMxBPoPDJ AUuoF/8ztlZGP6C7F0wd5hZH9X984x2syzZDzL4gFEc3Lny4JnhMSoLgVVIe8oayT0/KbF +5XcbkqIg5ESHEY4jXLyc513Rv+do2u06UijYbrHiadvWMQcPENVpXfZBkjJiXpNGMQVcn M4G1ZtwxVtROVg6okw5ZrSsrKQ8qY6D8hd6DJ6sDmC0+j8Y+j9E2nmaWP5hcbg== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Phil Edworthy Subject: [PATCH v3 09/10] serial: 8250: dw: Improve RZN1 support Date: Tue, 29 Mar 2022 17:24:29 +0200 Message-Id: <20220329152430.756947-10-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220329152430.756947-1-miquel.raynal@bootlin.com> References: <20220329152430.756947-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Phil Edworthy Renesas RZ/N1 SoC features a slightly modified DW UART. On this SoC, the CPR register value is known but not synthetized in hardware. We hence need to provide a CPR value in the platform data. This version of the controller also relies on acting as flow controller when using DMA, so we need to provide the 'IS_DMA_FLOW_CONTROLLER' quirk. Signed-off-by: Phil Edworthy Co-developed-by: Miquel Raynal Signed-off-by: Miquel Raynal --- drivers/tty/serial/8250/8250_dw.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index af9fcc77ee76..efc5c686dbfa 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -758,6 +758,11 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = { .quirks = DW_UART_QUIRK_ARMADA_38X, }; +static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { + .quirks = DW_UART_QUIRK_IS_DMA_FLOW_CONTROLLER, + .cpr = 0x00012f32, +}; + static const struct dw8250_platform_data dw8250_starfive_jh7100_data = { .quirks = DW_UART_QUIRK_SKIP_SET_RATE, }; @@ -766,7 +771,7 @@ static const struct of_device_id dw8250_of_match[] = { { .compatible = "snps,dw-apb-uart" }, { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, - { .compatible = "renesas,rzn1-uart" }, + { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, { .compatible = "starfive,jh7100-hsuart", .data = &dw8250_starfive_jh7100_data }, { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data }, { /* Sentinel */ }