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[109.49.33.111]) by smtp.gmail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm11622812wmb.36.2022.03.31.08.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 08:45:49 -0700 (PDT) From: Rui Miguel Silva To: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Rui Miguel Silva Subject: [PATCH v4 1/3] dt-bindings: net: smsc,lan91c111 convert to schema Date: Thu, 31 Mar 2022 16:45:34 +0100 Message-Id: <20220331154536.1544220-2-rui.silva@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220331154536.1544220-1-rui.silva@linaro.org> References: <20220331154536.1544220-1-rui.silva@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the smsc lan91c9x and lan91c1xx controller device tree bindings documentation to json-schema. Signed-off-by: Rui Miguel Silva --- .../bindings/net/smsc,lan91c111.yaml | 61 +++++++++++++++++++ .../bindings/net/smsc-lan91c111.txt | 17 ------ 2 files changed, 61 insertions(+), 17 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml delete mode 100644 Documentation/devicetree/bindings/net/smsc-lan91c111.txt diff --git a/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml new file mode 100644 index 000000000000..1730284430bc --- /dev/null +++ b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller + +maintainers: + - Nicolas Pitre + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + const: smsc,lan91c111 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reg-shift: true + + reg-io-width: + enum: [ 1, 2, 4 ] + default: 4 + + reset-gpios: + description: GPIO connected to control RESET pin + maxItems: 1 + + power-gpios: + description: GPIO connect to control PWRDEWN pin + maxItems: 1 + + pxa-u16-align4: + description: put in place the workaround the force all u16 writes to be + 32 bits aligned + type: boolean + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + ethernet@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = ; + reg-io-width = <2>; + }; diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt deleted file mode 100644 index 309e37eb7c7c..000000000000 --- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt +++ /dev/null @@ -1,17 +0,0 @@ -SMSC LAN91c111 Ethernet mac - -Required properties: -- compatible = "smsc,lan91c111"; -- reg : physical address and size of registers -- interrupts : interrupt connection - -Optional properties: -- phy-device : see ethernet.txt file in the same directory -- reg-io-width : Mask of sizes (in bytes) of the IO accesses that - are supported on the device. Valid value for SMSC LAN91c111 are - 1, 2 or 4. If it's omitted or invalid, the size would be 2 meaning - 16-bit access only. -- power-gpios: GPIO to control the PWRDWN pin -- reset-gpios: GPIO to control the RESET pin -- pxa-u16-align4 : Boolean, put in place the workaround the force all - u16 writes to be 32 bits aligned From patchwork Thu Mar 31 15:45:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 555342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1D1BC433FE for ; Thu, 31 Mar 2022 15:47:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234604AbiCaPsu (ORCPT ); Thu, 31 Mar 2022 11:48:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239804AbiCaPs1 (ORCPT ); Thu, 31 Mar 2022 11:48:27 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC8411D2049 for ; Thu, 31 Mar 2022 08:45:55 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id u3so380489wrg.3 for ; Thu, 31 Mar 2022 08:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1lYHVUjyiwdFk8wmNedKjP0QNXZ6Wdan6kfqSqK0oHY=; b=XESaiuo2OzoyYl/x/9YLj4KLnqFihJE+s/lm96Nfi35hKN4drWBYVAVuLI/QPiriqy xlihb5k1SDaBoD4nv5d2sAZUAhDYZ3uUU4dQaaEIfX8nX1sfXIwJuZtQTzPsL/lsWfas uo88U1JyNYC+NMwGzVXqG0S7gF9gwFkNh6Wv77tuUYs/t8jiY1xpbCkJ2xBKftrCJjRv ggbZj+kczVdNPgiJPSyNl+ln2FmX9nsYbvP0Vi/bMxXmtLiSkXnM7eAwBLK23b6+lIVz b41fmkjgOCk/g+zmfQVINmDe95DBLN0Vs6kp31FPaOCcvGbaFR9jMRWUfAMl6BbUMMYw eJKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1lYHVUjyiwdFk8wmNedKjP0QNXZ6Wdan6kfqSqK0oHY=; b=v8kMjL8jaaW79bT+Z8aEK2dcZjm4btmaYoBvZK4qbiNbZvM1mg5AiTBeFvVO6/GV5P c1sDw4IsfS70aN1I3tXmKo7or6Q4LYMTJ+c8BIGutKj99lSLpAoS4tUrByJLMDxYKT1m xY6Cv0ef24s4i6+L3/aQXjI6lXsE7CTij0tLqiBemN952bAfEWgalBa50Qs+74Q7sa0J 6gxihzt6UnyajHshYLL3b9zEHb+cNP8iOVZVmiBPgsGer4+os6dz0Q+EBsvTAsnax+qs YFOoTeYSnubn2Y9qMoRSPb7hkuV27g7+dyyhDcBL3KK3W67XEKP5S7AxGksySrFN4ihB Ys8A== X-Gm-Message-State: AOAM5326qcmMtoWaI1iXcAOhbZK2wKDd3mB4J0yWY3a14CXbmNs3L1o/ 3xGafM3+wW7N39utjpAVQBxpWJGgR/fzow== X-Google-Smtp-Source: ABdhPJwlhvJ43pml0LRaK/YvcULwEreMOxHbiItEAC9yPI+O/CpAlY0UsLfM6IuvK6U+cItnZ8aDjg== X-Received: by 2002:adf:eb48:0:b0:203:f854:86cc with SMTP id u8-20020adfeb48000000b00203f85486ccmr4518117wrn.102.1648741554286; Thu, 31 Mar 2022 08:45:54 -0700 (PDT) Received: from arch-thunder.local (a109-49-33-111.cpe.netcabo.pt. [109.49.33.111]) by smtp.gmail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm11622812wmb.36.2022.03.31.08.45.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 08:45:53 -0700 (PDT) From: Rui Miguel Silva To: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Rui Miguel Silva Subject: [PATCH v4 2/3] dt-bindings: arm: add corstone1000 platform Date: Thu, 31 Mar 2022 16:45:35 +0100 Message-Id: <20220331154536.1544220-3-rui.silva@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220331154536.1544220-1-rui.silva@linaro.org> References: <20220331154536.1544220-1-rui.silva@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings to describe the FPGA in a prototyping board (MPS3) implementation and the Fixed Virtual Platform implementation of the ARM Corstone1000 platform. Signed-off-by: Rui Miguel Silva --- .../bindings/arm/arm,corstone1000.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml new file mode 100644 index 000000000000..a77f88223801 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Corstone1000 Device Tree Bindings + +maintainers: + - Vishnu Banavath + - Rui Miguel Silva + +description: |+ + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M + processors. + + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion + systems for M-Class (or other) processors for adding sensors, connectivity, + video, audio and machine learning at the edge System and security IPs to build + a secure SoC for a range of rich IoT applications, for example gateways, smart + cameras and embedded systems. + + Integrated Secure Enclave providing hardware Root of Trust and supporting + seamless integration of the optional CryptoCell™-312 cryptographic + accelerator. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA + implementation of the Corstone1000 in the MPS3 prototyping board. See + ARM document DAI0550. + items: + - const: arm,corstone1000-mps3 + - description: Corstone1000 FVP is the Fixed Virtual Platform + implementation of this system. See ARM ecosystems FVP's. + items: + - const: arm,corstone1000-fvp + +additionalProperties: true + +...