From patchwork Sat Apr 2 18:40:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 555825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39B27C43217 for ; Sat, 2 Apr 2022 18:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244957AbiDBSmO (ORCPT ); Sat, 2 Apr 2022 14:42:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245125AbiDBSmN (ORCPT ); Sat, 2 Apr 2022 14:42:13 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7FC249CAE for ; Sat, 2 Apr 2022 11:40:19 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id j12so997842wrb.5 for ; Sat, 02 Apr 2022 11:40:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pIzqrLEArTXL9YEy+XaJ/FROhoWjUa+sSmTt7exmUDk=; b=nh4Ca1Iee5A+rirbfhGt+Y4dwNTpehhABC7OArTt0hzWuUgBtCt9/jHJOhzA+ilXax 5Y79iqh/uLd5gfQbLX0PtaugLmr+wl3WPAY13ptk9C+UYtGC7k3kHeSjJgA5AcWIqXqH zswiOUMOdjcw1X2gsp3Cxe8nQJQpTedfJ2HxqgcB7gLsLTBCLX9TOzRdxwcx1Ec0QJdH wK3KsTA9anfivP2sxJJpkbz3smHYaOXQeAWIH0K2rEng0ShBOh3xnzls4NrKMfoUCNQU Qh7JXCiJiqg1tLM+c0xI/kacasw7EjtQH5kHsUNhudBCsG5mfY8EOplzXAt6+hRjXrLQ dW4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pIzqrLEArTXL9YEy+XaJ/FROhoWjUa+sSmTt7exmUDk=; b=2Z6ZbN0XFtGeaXiAtJjNyrEiSDaXLeXzCnwpgfU4aBTjIUKxSidLMTFlEEZklBFA4X /VU6Ncu1M8omrC3QqBekbxFz0+sLvBGNbW8uuFwxJh/6Udb/rPzyiLhCEozj7flCsNpP seI/Pbrn2qQ+xyxDM6v8Fsy3seCTqbRhFxLbGA5F8JoO8xqByFMrNl66Of6NdtBUhRIx VJcdH85vHcYKid3O6sGStfd2at9RPag9THZFsq7/vOTPsFJxZtB7ueT6g4r9iN468TbL XEi4o5eXU3SRrNRJCVrZ0p6LiFDnajoZo8j98W+MAVNfBj/ZKsIUiqP352ntvKbKxWux Zhiw== X-Gm-Message-State: AOAM530WO++1OMZLV64aHoL3GQn5ApFR1PROsLhtAkgiF3tNMF8ReH8B sQ9EihgtmyPKaGa/3GoGyFbSqw== X-Google-Smtp-Source: ABdhPJyJTdw6BouhQE797tO7oerVq6r0ag2oAn6kxWGfF0SWMaDv9yXd0fuK0BPj/DZDZJWure2C+Q== X-Received: by 2002:adf:eb4d:0:b0:1ed:c1f7:a951 with SMTP id u13-20020adfeb4d000000b001edc1f7a951mr11426073wrn.454.1648924817778; Sat, 02 Apr 2022 11:40:17 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id m20-20020a05600c4f5400b0038b5162260csm6760502wmq.23.2022.04.02.11.40.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 11:40:17 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Brown , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v3 1/9] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema Date: Sat, 2 Apr 2022 20:40:03 +0200 Message-Id: <20220402184011.132465-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220402184011.132465-1-krzysztof.kozlowski@linaro.org> References: <20220402184011.132465-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DT schema expects dma channels in tx-rx order. No functional change. Signed-off-by: Krzysztof Kozlowski --- Dropped Kuldeep's ack because of changes - more properties changed. --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 +++---- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 +++++++------- arch/arm64/boot/dts/qcom/msm8916.dtsi | 32 +++++++++++++-------------- arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++--------- 4 files changed, 38 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index aac56575e30d..87c28ffa44d3 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -322,8 +322,8 @@ i2c_0: i2c@78b6000 { <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -337,8 +337,8 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 17>, <&blsp_dma 16>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index d80b1cefab10..2072638006a4 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -471,8 +471,8 @@ blsp1_i2c2: i2c@78b6000 { <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; pinctrl-0 = <&i2c_0_pins>; pinctrl-names = "default"; status = "disabled"; @@ -488,8 +488,8 @@ blsp1_i2c3: i2c@78b7000 { <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <100000>; - dmas = <&blsp_dma 17>, <&blsp_dma 16>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -503,8 +503,8 @@ blsp1_i2c5: i2c@78b9000 { <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 21>, <&blsp_dma 20>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -518,8 +518,8 @@ blsp1_i2c6: i2c@78ba000 { <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <100000>; - dmas = <&blsp_dma 23>, <&blsp_dma 22>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 22>, <&blsp_dma 23>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e34963505e07..384fc8738130 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1485,8 +1485,8 @@ blsp1_uart1: serial@78af000 { interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_uart1_default>; pinctrl-1 = <&blsp1_uart1_sleep>; @@ -1499,8 +1499,8 @@ blsp1_uart2: serial@78b0000 { interrupts = ; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_uart2_default>; pinctrl-1 = <&blsp1_uart2_sleep>; @@ -1529,8 +1529,8 @@ blsp_spi1: spi@78b5000 { clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_default>; pinctrl-1 = <&spi1_sleep>; @@ -1561,8 +1561,8 @@ blsp_spi2: spi@78b6000 { clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi2_default>; pinctrl-1 = <&spi2_sleep>; @@ -1593,8 +1593,8 @@ blsp_spi3: spi@78b7000 { clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi3_default>; pinctrl-1 = <&spi3_sleep>; @@ -1625,8 +1625,8 @@ blsp_spi4: spi@78b8000 { clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi4_default>; pinctrl-1 = <&spi4_sleep>; @@ -1657,8 +1657,8 @@ blsp_spi5: spi@78b9000 { clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 13>, <&blsp_dma 12>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi5_default>; pinctrl-1 = <&spi5_sleep>; @@ -1689,8 +1689,8 @@ blsp_spi6: spi@78ba000 { clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi6_default>; pinctrl-1 = <&spi6_sleep>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 3f06f7cd3cf2..6b3a8e1006d0 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -823,8 +823,8 @@ blsp1_uart0: serial@78af000 { interrupts = ; clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart0_default>; status = "disabled"; @@ -836,8 +836,8 @@ blsp1_uart1: serial@78b0000 { interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart1_default>; status = "disabled"; @@ -849,8 +849,8 @@ blsp1_uart2: serial@78b1000 { interrupts = ; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart2_default>; status = "okay"; @@ -903,8 +903,8 @@ blsp1_uart3: serial@78b2000 { interrupts = ; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart3_default>; status = "disabled"; @@ -1067,8 +1067,8 @@ blsp2_uart0: serial@7aef000 { interrupts = ; clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_uart0_default>; status = "disabled"; From patchwork Sat Apr 2 18:40:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 555821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5899CC35276 for ; Sat, 2 Apr 2022 18:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355648AbiDBSmv (ORCPT ); Sat, 2 Apr 2022 14:42:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245058AbiDBSmP (ORCPT ); Sat, 2 Apr 2022 14:42:15 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4CEE4C43A for ; Sat, 2 Apr 2022 11:40:21 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id h4so8542514wrc.13 for ; Sat, 02 Apr 2022 11:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ijNe1gxoWsdrm+oek0ryQTviG9eFIwp156wwm7qwtvc=; b=QS57J11MUObITJ/vb9ovmNk0WG+DE1ZiMHHrwzVn0L2+b3vWZbAdRPZKPO7QLNSryu 74b2HkwUaAtJAXHQaNbyH9Fh/ShNoJlA72t3i/FbErVQW9i4Dq2UalFgTV9NweJ2iFzc RtX63MdnCFOSKl+SbJzkjE5ACUMiPdghrsg/r4rMKjuAKkNe0JzzmEM8N5o9Q2sDvEqB akXw3sqnQwcXtXAe/TxkDeZ9hZQPKzyZhasp1AL31VsrszzKzRz6dROhSVyt3Eqs6vYK MWpYs03DXewtA7kWsHMUb9i/WkZ4EW6v+KLQHE+VY870v3Lh5wnZ60KxejWuqsuOCiC5 5GWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ijNe1gxoWsdrm+oek0ryQTviG9eFIwp156wwm7qwtvc=; b=kJNnSQ6ojfZ22Q4TiVSBJ0V3jmXpXmJVJQBJfcBbDycXHPOxnix4QNkxdJl+Ukeggl pdz1NmBqgSOvxgqbLRjq64ySqVv4XtcsZkALSGhLynMEX+Z4NnsXE8D2cxAB1TYLLsmF aFQ6NAJ+1CX4vo45bc8H0KsNBkIe0g6lVQzfcNIIIAfed/GzE/UZ7XzE+Zp8FXKMPVcf 1r0edQXYeZwVKln5QFIUl/52RrbBjPeiec5o6FheZG9izUQ+82W8owc/0Tt8rO4DLfTW BVLjwacyzJjeawbQOMt6ps+MP0WVLsEp7ntAzgMPYMxa/3hx8n0juX25wrFB9d+iDunt D1sw== X-Gm-Message-State: AOAM53038WLOduoODUeqxJ9EnTGBm8wqbgVubWJZ3pQvZvInJU4HmYsA TJl7iQQui9HvJ2swF9PxpH4jcg== X-Google-Smtp-Source: ABdhPJz9FA9JH2oOZCCYSONJ4CImbDLu4orm9k5IKhU9oR6fOzWRHx/mRp4fuOLIRLmBLVfIjeMIUA== X-Received: by 2002:a5d:6b0b:0:b0:1ef:d826:723a with SMTP id v11-20020a5d6b0b000000b001efd826723amr12091241wrw.420.1648924820081; Sat, 02 Apr 2022 11:40:20 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id m20-20020a05600c4f5400b0038b5162260csm6760502wmq.23.2022.04.02.11.40.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 11:40:19 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Brown , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v3 3/9] ARM: dts: qcom: ipq4019: align dmas in SPI/UART with DT schema Date: Sat, 2 Apr 2022 20:40:05 +0200 Message-Id: <20220402184011.132465-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220402184011.132465-1-krzysztof.kozlowski@linaro.org> References: <20220402184011.132465-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DT schema expects dma channels in tx-rx order. No functional change. Signed-off-by: Krzysztof Kozlowski --- Dropped Kuldeep's ack because of changes - more properties changed. --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index a9d0566a3190..1f6c4ab7f37e 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -253,8 +253,8 @@ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -267,8 +267,8 @@ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -281,8 +281,8 @@ blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ clock-names = "iface", "core"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -295,8 +295,8 @@ blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ clock-names = "iface", "core"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -382,8 +382,8 @@ blsp1_uart1: serial@78af000 { clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; }; blsp1_uart2: serial@78b0000 { @@ -394,8 +394,8 @@ blsp1_uart2: serial@78b0000 { clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; }; watchdog: watchdog@b017000 { From patchwork Sat Apr 2 18:40:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 555824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11AFBC433FE for ; Sat, 2 Apr 2022 18:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356753AbiDBSme (ORCPT ); Sat, 2 Apr 2022 14:42:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354778AbiDBSmd (ORCPT ); Sat, 2 Apr 2022 14:42:33 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11D804D9FC for ; Sat, 2 Apr 2022 11:40:24 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id p26-20020a05600c1d9a00b0038ccbff1951so4633160wms.1 for ; Sat, 02 Apr 2022 11:40:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0FPva/xF5QWD9GuBZmkDF4zJMJFtPU9JUPVfss7wEgA=; b=ym9CBYRNlyZUQNjyGH6kpXABn67E0eal9leUt0QBhtZJdtqSMbgGeiV/CddHZXUdC0 ID54p5tpITSPgdAblO4RlC59G3ujo3NQ0rGx5ajrOD5yJBVSa6CFTw7QFkhQWtu9hore 4JzBqhTFPf1ER5ByfUq1LHOo8rYtIDP3e7yx9hiYbDGZSFApvo2ldzAdrBtKv/OBSobR 5kqQuxxzDL7zPwcPVecA7KnpkrF85KdoH01R6RKK/lxZjm/dwB6Zzxqyk4v1G5uZ+YJz DTv3AgnB4EgDFkZQB/BjXLkZF8JuYhEScdwx1k/nNcU9S6hfvZO9P0BGTlJPmGKMwlyR uMpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0FPva/xF5QWD9GuBZmkDF4zJMJFtPU9JUPVfss7wEgA=; b=SBkZY4yZl1muaHWzABnqOfGkGV3Fpmw6CejXDNB3hDtOl8uY1iaPip2Zw4Br70iC/h 1/Z9MRAdXNU38FWMsh5E2DhpbFyNryBZyfZopAJ+OyzdNBibkzjVohPjcfhbHMpeW/Nh 0RI/3zZ+JdJDzD6fCCcUXzHWuuNZ5GMiLmalJfcvTUdYTwGP+XDYJHU8uSDEfVDwEp+V RNUwla2LLad3d+oKIO4dorbM5b/z+wIDaKmugM4BDzLDOLZqAqwZ76L2MrX8NVFe+uMC 03Pbve+7Q85oloMqk1VJUS93aIfkdCjmxWSMtzFSWY/Lj1Q4ayhCTSVLwgnBJBOjMThB DWYg== X-Gm-Message-State: AOAM532GbZAztT6UibY+iSnbfQ0qOC+gvIw53n2DRJeDTVW3shqtJ+z6 tDNnhyKuXxl/DVLzq21943k6e2wIR4Ywp1Uh X-Google-Smtp-Source: ABdhPJx+KbBUbfRJ/ITpnVRFc2VmBD3YtSvxiiWpGf1VKRS5lRLH2IYG/4eg9+kE+v7xzJ1zuIayKg== X-Received: by 2002:a05:600c:2244:b0:38c:a3ff:ef67 with SMTP id a4-20020a05600c224400b0038ca3ffef67mr12853149wmm.122.1648924822405; Sat, 02 Apr 2022 11:40:22 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id m20-20020a05600c4f5400b0038b5162260csm6760502wmq.23.2022.04.02.11.40.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 11:40:21 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Brown , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v3 5/9] ARM: dts: qcom: msm8660: disable GSBI8 Date: Sat, 2 Apr 2022 20:40:07 +0200 Message-Id: <20220402184011.132465-6-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220402184011.132465-1-krzysztof.kozlowski@linaro.org> References: <20220402184011.132465-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GSBI8 child node (I2C controller) is disabled, so as parent GSBI node should be the same. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/qcom-msm8660.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index a258abb23a64..47b97daecef1 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -212,6 +212,7 @@ gsbi8: gsbi@19800000 { ranges; syscon-tcsr = <&tcsr>; + status = "disabled"; gsbi8_i2c: i2c@19880000 { compatible = "qcom,i2c-qup-v1.1.1"; From patchwork Sat Apr 2 18:40:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 555823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2412C433EF for ; Sat, 2 Apr 2022 18:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358784AbiDBSmg (ORCPT ); Sat, 2 Apr 2022 14:42:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355261AbiDBSme (ORCPT ); Sat, 2 Apr 2022 14:42:34 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E7CE4BFFD for ; Sat, 2 Apr 2022 11:40:25 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id h4so8542621wrc.13 for ; Sat, 02 Apr 2022 11:40:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8UQnzpzJ7atASYcdmmpmKJN+w3hsF0/X9rG8MRnHqSQ=; b=sJkGlXQ6t/GZu/niHOpOZmjDOll5gznf77yzZ+d3nFHFi9zhmIBYWzO8zJm1lUtvHj mokqESv8EymQtzEj4HdDpdh2imD09qSWclAOV5dBnXy4uA+tnXRLnjsm8L52Jrcz1aBD kft5rp5Ubmhhn8OQ0zGKHEb/EyaRcr/tlJodiNTpHbeCiPHltu97uL/1OlqRkY4079Ap PPg1j02nGQGh2DU4qKEIpT+GG18rbfHnbmqU64fyVrAwR6ypo8aNywPOWJvt4ri3a6+U xDyAB98bBcx+xekpEefl5Ep6auS2KksQI4H1HtBOtqA38NlidZDO3ztz35Os8Cy+EN0Q pISg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8UQnzpzJ7atASYcdmmpmKJN+w3hsF0/X9rG8MRnHqSQ=; b=JTEvjMFgcH1GQfKH02lUZZ6Hxv6jv1UoLUoWP0viqwHkbYqkPtm1c9599lYDGRzbQv vrtcoRDMSLiB1xB2PRCZBlMB/5yxRBe/50pr7lGcXZidCs+yWOmpNIN3PjNqf4Hkm7ss nWRrWiQSYmYfKQ5C35wWw8TGF6voYJsuq72KPq5UYhTFkD6BvYGGz9Iv2nWQAx/RjIEO DSflsCAabi4pI8rWZg8tHub6zaqJjXqCYCqXbTotfzwJHYxAWeBvDAngX0pZeLUePkEg srHwa6DaznhT/xlp9uWjiTKYw51J/lZPQu8pc6yxHuDBW5PmaydRgUIEr2FQtFnIFdhu Ut7Q== X-Gm-Message-State: AOAM532+bO4I+lJc8icZCF6dr0oslqfULb+ez6W29wCi+guWG3vZIeWC MIgMORtAKIcr4un06C4p/dFHFA== X-Google-Smtp-Source: ABdhPJzgfFjUaD8MoK9zh4Fy6hmHDi8obj/pudrAdpzyXg8ImEW0WyON+B6gInWAdwqVSGua/RsS/A== X-Received: by 2002:a5d:5111:0:b0:205:a1aa:ab71 with SMTP id s17-20020a5d5111000000b00205a1aaab71mr11786912wrt.67.1648924823523; Sat, 02 Apr 2022 11:40:23 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id m20-20020a05600c4f5400b0038b5162260csm6760502wmq.23.2022.04.02.11.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 11:40:23 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Brown , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v3 6/9] spi: dt-bindings: qcom,spi-qup: convert to dtschema Date: Sat, 2 Apr 2022 20:40:08 +0200 Message-Id: <20220402184011.132465-7-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220402184011.132465-1-krzysztof.kozlowski@linaro.org> References: <20220402184011.132465-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) bindings to DT Schema. Signed-off-by: Krzysztof Kozlowski Acked-by: Kuldeep Singh Reviewed-by: Rob Herring --- .../devicetree/bindings/spi/qcom,spi-qup.txt | 103 ------------------ .../devicetree/bindings/spi/qcom,spi-qup.yaml | 81 ++++++++++++++ 2 files changed, 81 insertions(+), 103 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt deleted file mode 100644 index 5c090771c016..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt +++ /dev/null @@ -1,103 +0,0 @@ -Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) - -The QUP core is an AHB slave that provides a common data path (an output FIFO -and an input FIFO) for serial peripheral interface (SPI) mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programmable -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Should contain: - "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064. - "qcom,spi-qup-v2.1.1" for 8974 and later - "qcom,spi-qup-v2.2.1" for 8974 v2 and later. - -- reg: Should contain base register location and length -- interrupts: Interrupt number used by this controller - -- clocks: Should contain the core clock and the AHB clock. -- clock-names: Should be "core" for the core clock and "iface" for the - AHB clock. - -- #address-cells: Number of cells required to define a chip select - address on the SPI bus. Should be set to 1. -- #size-cells: Should be zero. - -Optional properties: -- spi-max-frequency: Specifies maximum SPI clock frequency, - Units - Hz. Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt -- num-cs: total number of chipselects -- cs-gpios: should specify GPIOs used for chipselects. - The gpios will be referred to as reg = in the SPI child - nodes. If unspecified, a single SPI device without a chip - select can be used. - -- dmas: Two DMA channel specifiers following the convention outlined - in bindings/dma/dma.txt -- dma-names: Names for the dma channels, if present. There must be at - least one channel named "tx" for transmit and named "rx" for - receive. - -SPI slave nodes must be children of the SPI master node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - spi_8: spi@f9964000 { /* BLSP2 QUP2 */ - - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf9964000 0x1000>; - interrupts = <0 102 0>; - spi-max-frequency = <19200000>; - - clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - - dmas = <&blsp1_bam 13>, <&blsp1_bam 12>; - dma-names = "rx", "tx"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi8_default>; - - device@0 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <19200000>; - spi-cpol; - }; - - device@1 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; /* Chip select 1 */ - spi-max-frequency = <9600000>; - spi-cpha; - }; - - device@2 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <2>; /* Chip select 2 */ - spi-max-frequency = <19200000>; - spi-cpol; - spi-cpha; - }; - - device@3 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <3>; /* Chip select 3 */ - spi-max-frequency = <19200000>; - spi-cpol; - spi-cpha; - spi-cs-high; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml new file mode 100644 index 000000000000..93f14dd01afc --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The QUP core is an AHB slave that provides a common data path (an output FIFO + and an input FIFO) for serial peripheral interface (SPI) mini-core. + + SPI in master mode supports up to 50MHz, up to four chip selects, + programmable data path from 4 bits to 32 bits and numerous protocol variants. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064 + - qcom,spi-qup-v2.1.1 # for 8974 and later + - qcom,spi-qup-v2.2.1 # for 8974 v2 and later + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: iface + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi@7575000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07575000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_spi1_default>; + pinctrl-1 = <&blsp1_spi1_sleep>; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + }; From patchwork Sat Apr 2 18:40:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 555822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A4FFC4321E for ; Sat, 2 Apr 2022 18:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357268AbiDBSmq (ORCPT ); Sat, 2 Apr 2022 14:42:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357255AbiDBSme (ORCPT ); Sat, 2 Apr 2022 14:42:34 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A011E50043 for ; Sat, 2 Apr 2022 11:40:28 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id l62-20020a1c2541000000b0038e4570af2fso3251329wml.5 for ; Sat, 02 Apr 2022 11:40:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sp/oLqlbge5GU7mZsZW/vx3cnsSFA9iABPk+CXY4wNg=; b=uQermoBxdAv6ihdtqTEbNjddI5LOjv2sgP8uaq/x7bM+rs+7OvofhXs1aFzKnXMqXs VqZ9BIvz2+6qyO6KrBEjovUZvAY3RjAJXc+uk2MUj4xYKyfTyipQBym0Lyar3l6iTFye gMChWkuyapkbpPU8fzvoZ8OzqRq7u7pUS5FWnSvzAjItqng+dJXb48A1IctyOJhTfL0y wGc/+JvG2Sx4PcyZlO6YEyO/JEDehtr8sUeWLNLSHNCsIcDfupzDab8ij3duScj2m4YB KfFLHIfkAIA7kIhfMJkQOS5xv55ZPFI8q9gLrlD+HUgU2kW+cwQ1eyQTSpOUIbDoi2qt /+Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sp/oLqlbge5GU7mZsZW/vx3cnsSFA9iABPk+CXY4wNg=; b=Bb1s2kSW6Ca3R9RlnsH6MnoTnQn5yxO9xsUlBzproTLKS7X/ri8eoN8I2nqfkmYDCw sQbALqMYtIEhp1Db5gWv/MYkb/jg4b8Zu14VSn0ZOXgwUOF9ZFEOLOlmbY1Sxh6lizJG vorJ1NnuB33GNIY5bjS4pzLoOuH8GiO9ksx4w9yr2CsNt/Q2JeFD4+pyZaA0m5t2UR4h CpUa2JTdaqP7AwOsef9nu3yadCOAIWYYQQVNHZ5Vktmk+n2KLM2cSxg9nMKdaNFL1eMh GDBsIqzJNH+QaX4YtkkvkpjuLBBw9/2nbdMP7yPiz3jovdjzEd3c6NcvSB9IPVjsNEtT 9l4Q== X-Gm-Message-State: AOAM530W8Jbd1XEMdkje45zZ3R/uhAPTMzACPGOVk5xhgNl32io6hmAq BlM7Akj6TJjHRp5relIr3EPMYw== X-Google-Smtp-Source: ABdhPJzKWhMSetsdvl9+noYgz+2YR/oqaR3HdqGzxC62zE4oTWSrcJcdEMLv0GwYLxCeb80tJWa+MA== X-Received: by 2002:a05:600c:600a:b0:38c:f953:adc0 with SMTP id az10-20020a05600c600a00b0038cf953adc0mr13523252wmb.188.1648924827120; Sat, 02 Apr 2022 11:40:27 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id m20-20020a05600c4f5400b0038b5162260csm6760502wmq.23.2022.04.02.11.40.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 11:40:26 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Brown , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v3 9/9] dt-bindings: qcom: qcom,gsbi: convert to dtschema Date: Sat, 2 Apr 2022 20:40:11 +0200 Message-Id: <20220402184011.132465-10-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220402184011.132465-1-krzysztof.kozlowski@linaro.org> References: <20220402184011.132465-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the Qualcomm General Serial Bus Interface (GSBI) to DT Schema. Signed-off-by: Krzysztof Kozlowski --- .../bindings/soc/qcom/qcom,gsbi.txt | 87 ------------ .../bindings/soc/qcom/qcom,gsbi.yaml | 133 ++++++++++++++++++ 2 files changed, 133 insertions(+), 87 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt deleted file mode 100644 index fe1855f09dcc..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt +++ /dev/null @@ -1,87 +0,0 @@ -QCOM GSBI (General Serial Bus Interface) Driver - -The GSBI controller is modeled as a node with zero or more child nodes, each -representing a serial sub-node device that is mux'd as part of the GSBI -configuration settings. The mode setting will govern the input/output mode of -the 4 GSBI IOs. - -Required properties: -- compatible: Should contain "qcom,gsbi-v1.0.0" -- cell-index: Should contain the GSBI index -- reg: Address range for GSBI registers -- clocks: required clock -- clock-names: must contain "iface" entry -- qcom,mode : indicates MUX value for configuration of the serial interface. - Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values. - -Optional properties: -- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference - dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values. -- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses - dma. - -Required properties if child node exists: -- #address-cells: Must be 1 -- #size-cells: Must be 1 -- ranges: Must be present - -Properties for children: - -A GSBI controller node can contain 0 or more child nodes representing serial -devices. These serial devices can be a QCOM UART, I2C controller, spi -controller, or some combination of aforementioned devices. - -See the following for child node definitions: -Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt -Documentation/devicetree/bindings/spi/qcom,spi-qup.txt -Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt - -Example for APQ8064: - -#include - - gsbi4@16300000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x100>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - qcom,mode = ; - qcom,crci = ; - - syscon-tcsr = <&tcsr>; - - /* child nodes go under here */ - - i2c_qup4: i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16380000 0x1000>; - interrupts = <0 153 0>; - - clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - - clock-frequency = <200000>; - - #address-cells = <1>; - #size-cells = <0>; - - }; - - uart4: serial@16340000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16340000 0x1000>, - <0x16300000 0x1000>; - interrupts = <0 152 0x0>; - clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,apq8064-tcsr", "syscon"; - reg = <0x1a400000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml new file mode 100644 index 000000000000..b97e359f3f90 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm General Serial Bus Interface (GSBI) + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The GSBI controller is modeled as a node with zero or more child nodes, each + representing a serial sub-node device that is mux'd as part of the GSBI + configuration settings. The mode setting will govern the input/output mode + of the 4 GSBI IOs. + + A GSBI controller node can contain 0 or more child nodes representing serial + devices. These serial devices can be a QCOM UART, I2C controller, spi + controller, or some combination of aforementioned devices. + +properties: + compatible: + enum: + - qcom,gsbi-v1.0.0 + + '#address-cells': + const: 1 + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The GSBI index. + + clocks: + maxItems: 1 + + clock-names: + const: iface + + qcom,crci: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + CRCI MUX value for QUP CRCI ports. Please reference + include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values. + + qcom,mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + MUX value for configuration of the serial interface. Please reference + include/dt-bindings/soc/qcom,gsbi.h for valid mux values. + + '#size-cells': + const: 1 + + syscon-tcsr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of TCSR syscon node.Required if child uses dma. + + ranges: true + + reg: + maxItems: 1 + +patternProperties: + "spi@[0-9a-f]+$": + type: object + $ref: /schemas/spi/qcom,spi-qup.yaml# + + "i2c@[0-9a-f]+$": + type: object + $ref: /schemas/i2c/qcom,i2c-qup.yaml# + + "serial@[0-9a-f]+$": + type: object + $ref: /schemas/serial/qcom,msm-uartdm.yaml# + +required: + - compatible + - cell-index + - clocks + - clock-names + - qcom,mode + - reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + + gsbi@12440000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12440000 0x100>; + cell-index = <1>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + qcom,mode = ; + + serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + }; + + i2c@12460000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x12460000 0x1000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_pins_sleep>; + pinctrl-names = "default", "sleep"; + interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* UART chosen */ + }; + };