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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id j3-20020adfd203000000b0020616cddfd5sm13901357wrh.7.2022.04.09.09.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 09:45:59 -0700 (PDT) From: Bryan O'Donoghue To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: dmitry.baryshkov@linaro.org, jonathan@marek.ca, hfink@snap.com, jgrahsl@snap.com, bryan.odonoghue@linaro.org Subject: [PATCH 1/4] arm64: dts: qcom: sm8250: Add camcc DT node Date: Sat, 9 Apr 2022 17:45:53 +0100 Message-Id: <20220409164556.2832782-2-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220409164556.2832782-1-bryan.odonoghue@linaro.org> References: <20220409164556.2832782-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the camcc DT node for the Camera Clock Controller on sm8250. Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index af8f22636436..906bc8ed25b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -3149,6 +3150,20 @@ videocc: clock-controller@abf0000 { #power-domain-cells = <1>; }; + camcc: clock-controller@ad00000 { + compatible = "qcom,sm8250-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sm8250-mdss"; reg = <0 0x0ae00000 0 0x1000>; From patchwork Sat Apr 9 16:45:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 559253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25607C4321E for ; Sat, 9 Apr 2022 16:46:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242758AbiDIQsN (ORCPT ); Sat, 9 Apr 2022 12:48:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242760AbiDIQsL (ORCPT ); Sat, 9 Apr 2022 12:48:11 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50BA11B7BC for ; Sat, 9 Apr 2022 09:46:04 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id i20so4045596wrb.13 for ; Sat, 09 Apr 2022 09:46:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jDJXVqRnHQKPHD8kA15Bj0py2ulSvTzcYuA88kraYds=; b=SRCLo+zVnn4lNeTUSMwWiwKYsmlNghVcSe9a8/I2gDD9334DgfYz9mxwwYMmxJ3usN DfGEFnQpbf9YNu5cMRVPqQr9BeC7jTs1SYy02X8jEdN5GLl2m+JCPqMzWJJ2F31HIvQ+ xj1KTrgihf78UFaS+ZWdI90c6xNjj0l401bJLvcmCQIOsl9t47McaPM3BukHfbYjARE9 fnR3ER/QT3J0tqzMs4VZ3oeEEHSO6MF/ncnJT7znO0bDqbAa36/oxB/20GiGi8YwQQc4 HL/F1TtnL2Zpue0Wf3BqrSmK43wivF9DwbdVupLmazkAWIPp6CQPNzejACedX0edBj4H TMsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jDJXVqRnHQKPHD8kA15Bj0py2ulSvTzcYuA88kraYds=; b=w3dBwMAQuJZ0lYvXoGaBa4NRHwHw+IGtVwCaJzZFpcK24mEpPgyJV9V4k/euoAZFPy JyQb+LBYapABAOsNI5WOxHQGxzazO75IuSEVcF02Tbxqqqf9Z2TRVf0DAUESiDvjr5Hs dSHJs41OtgSkzn9tguQvNKJraMsS13CaOJQxsf2Ylxd5qFUWf5ihzmEK4OuyxOJBpZ6z fREHKERaVqLh3jqd58SXTpngvE++BItsV9uBKInm9kZGa0jXTX3/xvZQextfEevXY/Go vK2m+DqvXloO01d6hMd2Lx6XSgja11g3PRFfALE8PMbDT0hwj3giJZE7pdOifIRt3G8D 54zw== X-Gm-Message-State: AOAM531ssQCbxXB8gyC2LOTqkn2u1p4LPu6UFNfDH7txBOJi7uP3UFpv VEtbCUAu15B6KuaDnMFVoHZlWg== X-Google-Smtp-Source: ABdhPJxIOrJpxcCprwDwc94ksJ6j0Y/EBAJV819QAUcCo9i5ixOzW1fV0Ov2zlN+GEwoJTN5b8HFiQ== X-Received: by 2002:a5d:5482:0:b0:206:b5c:ef4d with SMTP id h2-20020a5d5482000000b002060b5cef4dmr18509764wrv.152.1649522762865; Sat, 09 Apr 2022 09:46:02 -0700 (PDT) Received: from sagittarius-a.chello.ie (188-141-3-169.dynamic.upc.ie. [188.141.3.169]) by smtp.gmail.com with ESMTPSA id j3-20020adfd203000000b0020616cddfd5sm13901357wrh.7.2022.04.09.09.46.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 09:46:02 -0700 (PDT) From: Bryan O'Donoghue To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: dmitry.baryshkov@linaro.org, jonathan@marek.ca, hfink@snap.com, jgrahsl@snap.com, bryan.odonoghue@linaro.org Subject: [PATCH 4/4] arm64: dts: qcom: sm8250: camss: Add CCI definitions Date: Sat, 9 Apr 2022 17:45:56 +0100 Message-Id: <20220409164556.2832782-5-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220409164556.2832782-1-bryan.odonoghue@linaro.org> References: <20220409164556.2832782-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org sm8250 has two CCI busses with two I2C busses apiece. Co-developed-by: Julian Grahsl Signed-off-by: Julian Grahsl Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 82 ++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 91ed079edbf7..98e96527702b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3150,6 +3150,88 @@ videocc: clock-controller@abf0000 { #power-domain-cells = <1>; }; + cci0: cci@ac4f000 { + compatible = "qcom,sm8250-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4f000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac50000 { + compatible = "qcom,sm8250-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac50000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci2_default &cci3_default>; + pinctrl-1 = <&cci2_sleep &cci3_sleep>; + + status = "disabled"; + + cci_i2c2: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c3: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: camss@ac6a000 { compatible = "qcom,sm8250-camss"; status = "disabled";