From patchwork Mon Apr 11 15:43:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 559723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 614A6C433F5 for ; Mon, 11 Apr 2022 15:44:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348160AbiDKPqj (ORCPT ); Mon, 11 Apr 2022 11:46:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348174AbiDKPqY (ORCPT ); Mon, 11 Apr 2022 11:46:24 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E4386159 for ; Mon, 11 Apr 2022 08:44:09 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id ks6so7120106ejb.1 for ; Mon, 11 Apr 2022 08:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mbNpbkkEChotn+zfIrEUISzZtq6Ebit9E8w1dEveKi4=; b=aYr0ukfkZGIsCt/4FT/QKR69G8IU6TdAGT0VhxtNMxD/ZM2av3R60rfzy0Lr+z2jqX RNffGh7JAzN/ky5V6U8TCJAnWdy3iGs3KhP04uuK3EugGOnpLwwcGZ2fTIgLFM56bQaF tbuWxvmlORJFEJxu81ME/WoTRcDnrFtKZ4M8HuZecRxEPgqPKITFt+ju1BeHb2YcHKUa iR8iLpWXca6o/Mwk8EvwYFqlUBxH0JRF0IUfHs1g6bPNU08wkfwWhQOP7w/whgOjQjfI YX1kzMwC0NEyR+1iPz3swS1o1S5TWeDzVAip9VKO1Jfd+vnYpKHzQSkH5s+HiHLRM0Jw MFvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mbNpbkkEChotn+zfIrEUISzZtq6Ebit9E8w1dEveKi4=; b=4QT6wPbn+JfEcj8wD5aETyr0T6ZaqQeNEeLg2vcg0fVhY1Z+DBnYnIO8CYNnuKosrv Wuq4lW6h5ctD4CVX2cFjexkMO5+8JXkyOxY6Ir7QC4cFR5pqE6SCNxgRwcl6U3DsJ+8b vLx9dAd2mvBnk3IwjvjHFXw1uE/PUbTWvtZSv5YzTcZHounQUoZ4VoGyLJ5b00ao21pg MpW6sghlmEyeBZNXtzAa5BuWmAw1/2L2YL9ybkt2nF+kzmwmX2C4hSVcRac41XGQy02f BL+RkjUx+h5xKgIkeBsGHbsU6o4vkFPA8ESPgFeF2qwhoW3sy7k80NTpYKsKYsIY0SVj Kbrg== X-Gm-Message-State: AOAM531GTK/4vJOP2R5YQ/1//yp3j77MVIQLNrsNwsS/Z44kuyJ3WeIA tRQKnnCuviNINe0TtquOeIVa6A== X-Google-Smtp-Source: ABdhPJwrK+vLq5FHXsKcsbi/1tugMQSwYKotl7aV7TAwegLV/VGDWOX0mMt4H3we7pNjfWm9PA2Pzg== X-Received: by 2002:a17:906:d108:b0:6e8:7765:a70b with SMTP id b8-20020a170906d10800b006e87765a70bmr8961267ejz.436.1649691847786; Mon, 11 Apr 2022 08:44:07 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id t14-20020a170906608e00b006d1455acc62sm12173177ejj.74.2022.04.11.08.44.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 08:44:07 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Viresh Kumar , Nishanth Menon , Alim Akhtar , Avri Altman , "James E.J. Bottomley" , "Martin K. Petersen" , "Rafael J. Wysocki" , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-scsi@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [RFC PATCH v2 3/6] dt-bindings: ufs: common: add OPP table Date: Mon, 11 Apr 2022 17:43:44 +0200 Message-Id: <20220411154347.491396-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220411154347.491396-1-krzysztof.kozlowski@linaro.org> References: <20220411154347.491396-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Except scaling UFS and bus clocks, it's necessary to scale also the voltages of regulators or power domain performance state levels. Adding Operating Performance Points table allows to adjust power domain performance state, depending on the UFS clock speed. OPPv2 deprecates previous property limited to clock scaling: freq-table-hz. Signed-off-by: Krzysztof Kozlowski --- Not adding Rob's review tag because patch changed significantly. --- .../devicetree/bindings/ufs/ufs-common.yaml | 34 +++++++++++++++++-- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml b/Documentation/devicetree/bindings/ufs/ufs-common.yaml index 47a4e9e1a775..d7d2c8a136bb 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-common.yaml +++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml @@ -20,11 +20,24 @@ properties: items: - description: Minimum frequency for given clock in Hz - description: Maximum frequency for given clock in Hz + deprecated: true description: | + Preferred is operating-points-v2. + Array of operating frequencies in Hz stored in the same order - as the clocks property. If this property is not defined or a value in the - array is "0" then it is assumed that the frequency is set by the parent - clock or a fixed rate clock source. + as the clocks property. If either this property or operating-points-v2 is + not defined or a value in the array is "0" then it is assumed that the + frequency is set by the parent clock or a fixed rate clock source. + + operating-points-v2: + description: + Preferred over freq-table-hz. + If present, each OPP must contain array of frequencies stored in the same + order for each clock. If clock frequency in the array is "0" then it is + assumed that the frequency is set by the parent clock or a fixed rate + clock source. + + opp-table: true interrupts: maxItems: 1 @@ -75,8 +88,23 @@ properties: dependencies: freq-table-hz: [ 'clocks' ] + operating-points-v2: [ 'clocks', 'clock-names' ] required: - interrupts +allOf: + - if: + required: + - freq-table-hz + then: + properties: + operating-points-v2: false + - if: + required: + - operating-points-v2 + then: + properties: + freq-table-hz: false + additionalProperties: true From patchwork Mon Apr 11 15:43:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 559722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F107CC433F5 for ; Mon, 11 Apr 2022 15:44:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348194AbiDKPqu (ORCPT ); Mon, 11 Apr 2022 11:46:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348196AbiDKPq2 (ORCPT ); Mon, 11 Apr 2022 11:46:28 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EF26101F for ; Mon, 11 Apr 2022 08:44:10 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id i27so31742635ejd.9 for ; Mon, 11 Apr 2022 08:44:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bUHecTwVVvrne6C2zn7NEqF69WKs5io5wOl9BsR+pdo=; b=BaMULQQDH7+BY7SGNbOzUIqSAU7zrXml4onrxL4y4kDEEBKfZZ/bxvgYRMvA8nZB4y HGKNJHTI2Q54ob0+Rm+ceREjsPZrO+X5JYdUGI7pEIL95bJAlXHH/acTk3aqCLogGolG vsUFz93L4n6nI6UbeVVAFl98x13XvQtJ8zlOuro8bzhskFn5hn3Kap2o5d62qzicWJUD nGJzBH/IsQZ1NP4Cu5olOQN2X8l1QeN7oZ1HXZXl4r3S8+pn/iuIyTeWIKX2Zpgi5ZTw yBsGhkgqf727wDaQ2/rgiAe1GVW0FLHmnUoMD0BbfrbRdWM/FullRXxWoRXK5Nfy6WAw 0nfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bUHecTwVVvrne6C2zn7NEqF69WKs5io5wOl9BsR+pdo=; b=ulW0ns7ZY//p4lZaOw2xkHpdSnQ1XUZ/+TgNv0FPEBHtnfEFFMnVrImnZ+riHXQNAq MmtKrcvr0ucDenfuBWX0d+qIX2hngQWsZIm3Qr6VtWIquzJ4RO2W+Vhhv0w21/Sxxx2X mJ15iHqfK80ddN5j0gTqDrsKSw5rRturUTfWvaHS8K40pXfY/H2J48UcxzzKbWig1jRA D/hVixCoyOowsxXXSzkZEWIXkDClBPDwIOLwgS+KejiVXz+Gb4Zm50qeZP14hlPWXXG0 8pa2h0jtT6Wfkh46+2g7IiSORVrw38H379uQ/o9oyuwK1hVCyNt9yBdrNKgtN98rkX45 dKLg== X-Gm-Message-State: AOAM533Nov4n1f7SsofVlAaxCUZK/RQ2T2l9CBG2Jgwaa3JJOvs8cubi i96NOwfmzsJzvPW5TxwDjoZLjg== X-Google-Smtp-Source: ABdhPJwwG9Grjj6nk3K3sUNY+XKJcYXGnzmhTUqb0CMKRGbYy5SXYghPI801vigi57Cv8+gkb+cPHA== X-Received: by 2002:a17:906:e110:b0:6e6:75e0:946c with SMTP id gj16-20020a170906e11000b006e675e0946cmr29924830ejb.611.1649691849033; Mon, 11 Apr 2022 08:44:09 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id t14-20020a170906608e00b006d1455acc62sm12173177ejj.74.2022.04.11.08.44.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 08:44:08 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Viresh Kumar , Nishanth Menon , Alim Akhtar , Avri Altman , "James E.J. Bottomley" , "Martin K. Petersen" , "Rafael J. Wysocki" , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-scsi@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [RFC PATCH v2 4/6] PM: opp: allow control of multiple clocks Date: Mon, 11 Apr 2022 17:43:45 +0200 Message-Id: <20220411154347.491396-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220411154347.491396-1-krzysztof.kozlowski@linaro.org> References: <20220411154347.491396-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Devices might need to control several clocks when scaling the frequency and voltage. Example is the Universal Flash Storage (UFS) which scales several independent clocks with change of performance levels. Add parsing of multiple clocks and clock names and scale all of them, when needed. If only one clock is provided, the code should behave the same as before. Signed-off-by: Krzysztof Kozlowski --- drivers/opp/core.c | 205 ++++++++++++++++++++++++++++++++--------- drivers/opp/of.c | 48 ++++++++++ drivers/opp/opp.h | 9 +- include/linux/pm_opp.h | 23 +++++ 4 files changed, 242 insertions(+), 43 deletions(-) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 2945f3c1ce09..5dcd7157f6ab 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -66,6 +66,21 @@ static struct opp_table *_find_opp_table_unlocked(struct device *dev) return ERR_PTR(-ENODEV); } +static void _put_clocks(struct opp_table *opp_table) +{ + int i; + + if (!opp_table->clks) + return; + + for (i = opp_table->clk_count - 1; i >= 0; i--) + clk_put(opp_table->clks[i]); + + kfree(opp_table->clks); + opp_table->clks = NULL; + opp_table->clk_count = -1; +}; + /** * _find_opp_table() - find opp_table struct using device pointer * @dev: device pointer used to lookup OPP table @@ -772,6 +787,30 @@ static inline int _generic_set_opp_clk_only(struct device *dev, struct clk *clk, return ret; } +static int _generic_set_opp_clks_only(struct device *dev, + struct opp_table *opp_table, + struct dev_pm_opp *opp) +{ + int i, ret; + + if (!opp_table->clks) + return 0; + + for (i = 0; i < opp_table->clk_count; i++) { + if (opp->rates[i]) { + ret = _generic_set_opp_clk_only(dev, opp_table->clks[i], + opp->rates[i]); + if (ret) { + dev_err(dev, "%s: failed to set clock %pC rate: %d\n", + __func__, opp_table->clks[i], ret); + return ret; + } + } + } + + return 0; +} + static int _generic_set_opp_regulator(struct opp_table *opp_table, struct device *dev, struct dev_pm_opp *opp, @@ -796,7 +835,7 @@ static int _generic_set_opp_regulator(struct opp_table *opp_table, } /* Change frequency */ - ret = _generic_set_opp_clk_only(dev, opp_table->clk, freq); + ret = _generic_set_opp_clks_only(dev, opp_table, opp); if (ret) goto restore_voltage; @@ -820,7 +859,7 @@ static int _generic_set_opp_regulator(struct opp_table *opp_table, return 0; restore_freq: - if (_generic_set_opp_clk_only(dev, opp_table->clk, old_opp->rate)) + if (_generic_set_opp_clks_only(dev, opp_table, old_opp)) dev_err(dev, "%s: failed to restore old-freq (%lu Hz)\n", __func__, old_opp->rate); restore_voltage: @@ -880,7 +919,7 @@ static int _set_opp_custom(const struct opp_table *opp_table, } data->regulators = opp_table->regulators; - data->clk = opp_table->clk; + data->clk = (opp_table->clks ? opp_table->clks[0] : NULL); data->dev = dev; data->old_opp.rate = old_opp->rate; data->new_opp.rate = freq; @@ -969,8 +1008,8 @@ static void _find_current_opp(struct device *dev, struct opp_table *opp_table) struct dev_pm_opp *opp = ERR_PTR(-ENODEV); unsigned long freq; - if (!IS_ERR(opp_table->clk)) { - freq = clk_get_rate(opp_table->clk); + if (opp_table->clks && !IS_ERR(opp_table->clks[0])) { + freq = clk_get_rate(opp_table->clks[0]); opp = _find_freq_ceil(opp_table, &freq); } @@ -1070,7 +1109,7 @@ static int _set_opp(struct device *dev, struct opp_table *opp_table, scaling_down); } else { /* Only frequency scaling */ - ret = _generic_set_opp_clk_only(dev, opp_table->clk, freq); + ret = _generic_set_opp_clks_only(dev, opp_table, opp); } if (ret) @@ -1135,11 +1174,15 @@ int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq) * equivalent to a clk_set_rate() */ if (!_get_opp_count(opp_table)) { - ret = _generic_set_opp_clk_only(dev, opp_table->clk, target_freq); + if (opp_table->clks) + ret = _generic_set_opp_clk_only(dev, + opp_table->clks[0], + target_freq); goto put_opp_table; } - freq = clk_round_rate(opp_table->clk, target_freq); + if (opp_table->clks) + freq = clk_round_rate(opp_table->clks[0], target_freq); if ((long)freq <= 0) freq = target_freq; @@ -1156,6 +1199,11 @@ int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq) __func__, freq, ret); goto put_opp_table; } + /* + * opp->rates are used for scaling clocks, so be sure accurate + * 'freq' is used, instead what was defined via e.g. Devicetree. + */ + opp->rates[0] = freq; } ret = _set_opp(dev, opp_table, opp, freq); @@ -1246,7 +1294,8 @@ static struct opp_table *_allocate_opp_table(struct device *dev, int index) INIT_LIST_HEAD(&opp_table->dev_list); INIT_LIST_HEAD(&opp_table->lazy); - /* Mark regulator count uninitialized */ + /* Mark regulator/clk count uninitialized */ + opp_table->clk_count = -1; opp_table->regulator_count = -1; opp_dev = _add_opp_dev(dev, opp_table); @@ -1295,21 +1344,32 @@ static struct opp_table *_update_opp_table_clk(struct device *dev, * Return early if we don't need to get clk or we have already tried it * earlier. */ - if (!getclk || IS_ERR(opp_table) || opp_table->clk) + if (!getclk || IS_ERR(opp_table) || opp_table->clks) return opp_table; + opp_table->clks = kmalloc_array(1, sizeof(*opp_table->clks), + GFP_KERNEL); + if (!opp_table->clks) + return ERR_PTR(-ENOMEM); + /* Find clk for the device */ - opp_table->clk = clk_get(dev, NULL); + opp_table->clks[0] = clk_get(dev, NULL); - ret = PTR_ERR_OR_ZERO(opp_table->clk); - if (!ret) + ret = PTR_ERR_OR_ZERO(opp_table->clks[0]); + if (!ret) { + opp_table->clk_count = 1; return opp_table; + } if (ret == -ENOENT) { + opp_table->clk_count = 0; dev_dbg(dev, "%s: Couldn't find clock: %d\n", __func__, ret); return opp_table; } + kfree(opp_table->clks); + opp_table->clks = NULL; + opp_table->clk_count = -1; dev_pm_opp_put_opp_table(opp_table); dev_err_probe(dev, ret, "Couldn't find clock\n"); @@ -1408,9 +1468,7 @@ static void _opp_table_kref_release(struct kref *kref) _of_clear_opp_table(opp_table); - /* Release clk */ - if (!IS_ERR(opp_table->clk)) - clk_put(opp_table->clk); + _put_clocks(opp_table); if (opp_table->paths) { for (i = 0; i < opp_table->path_count; i++) @@ -2144,9 +2202,51 @@ EXPORT_SYMBOL_GPL(devm_pm_opp_set_regulators); * This must be called before any OPPs are initialized for the device. */ struct opp_table *dev_pm_opp_set_clkname(struct device *dev, const char *name) +{ + return dev_pm_opp_set_clknames(dev, &name, 1); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_clkname); + +/** + * dev_pm_opp_put_clkname() - Releases resources blocked for clk. + * @opp_table: OPP table returned from dev_pm_opp_set_clkname(). + */ +void dev_pm_opp_put_clkname(struct opp_table *opp_table) +{ + return dev_pm_opp_put_clknames(opp_table); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_put_clkname); + +/** + * devm_pm_opp_set_clkname() - Set clk name for the device + * @dev: Device for which clk name is being set. + * @name: Clk name. + * + * This is a resource-managed variant of dev_pm_opp_set_clkname(). + * + * Return: 0 on success and errorno otherwise. + */ +int devm_pm_opp_set_clkname(struct device *dev, const char *name) +{ + return devm_pm_opp_set_clknames(dev, &name, 1); +} +EXPORT_SYMBOL_GPL(devm_pm_opp_set_clkname); + +/** + * dev_pm_opp_set_clknames() - Set clk names for the device + * @dev: Device for which clock names are being set. + * @names: Array of pointers to the names of the clocks. + * @count: Number of clocks. + * + * See: dev_pm_opp_set_clkname() + */ +struct opp_table *dev_pm_opp_set_clknames(struct device *dev, + const char * const names[], + unsigned int count) { struct opp_table *opp_table; - int ret; + struct clk *clk; + int ret, i; opp_table = _add_opp_table(dev, false); if (IS_ERR(opp_table)) @@ -2159,70 +2259,92 @@ struct opp_table *dev_pm_opp_set_clkname(struct device *dev, const char *name) } /* clk shouldn't be initialized at this point */ - if (WARN_ON(opp_table->clk)) { + if (WARN_ON(opp_table->clks)) { ret = -EBUSY; goto err; } - /* Find clk for the device */ - opp_table->clk = clk_get(dev, name); - if (IS_ERR(opp_table->clk)) { - ret = dev_err_probe(dev, PTR_ERR(opp_table->clk), - "%s: Couldn't find clock\n", __func__); + opp_table->clks = kmalloc_array(count, sizeof(*opp_table->clks), + GFP_KERNEL); + if (!opp_table->clks) { + ret = -ENOMEM; goto err; } + for (i = 0; i < count; i++) { + clk = clk_get(dev, names[i]); + if (IS_ERR(clk)) { + ret = dev_err_probe(dev, PTR_ERR(clk), + "%s: Couldn't find clock %s\n", + __func__, names[i]); + goto free_clks; + } + + opp_table->clks[i] = clk; + } + + opp_table->clk_count = count; + return opp_table; +free_clks: + while (i != 0) + clk_put(opp_table->clks[--i]); + + kfree(opp_table->clks); + opp_table->clks = NULL; + opp_table->clk_count = -1; err: dev_pm_opp_put_opp_table(opp_table); return ERR_PTR(ret); } -EXPORT_SYMBOL_GPL(dev_pm_opp_set_clkname); +EXPORT_SYMBOL_GPL(dev_pm_opp_set_clknames); /** - * dev_pm_opp_put_clkname() - Releases resources blocked for clk. - * @opp_table: OPP table returned from dev_pm_opp_set_clkname(). + * dev_pm_opp_put_clknames() - Releases resources blocked for clk. + * @opp_table: OPP table returned from dev_pm_opp_set_clknames(). */ -void dev_pm_opp_put_clkname(struct opp_table *opp_table) +void dev_pm_opp_put_clknames(struct opp_table *opp_table) { if (unlikely(!opp_table)) return; - clk_put(opp_table->clk); - opp_table->clk = ERR_PTR(-EINVAL); + _put_clocks(opp_table); dev_pm_opp_put_opp_table(opp_table); } -EXPORT_SYMBOL_GPL(dev_pm_opp_put_clkname); +EXPORT_SYMBOL_GPL(dev_pm_opp_put_clknames); -static void devm_pm_opp_clkname_release(void *data) +static void devm_pm_opp_clknames_release(void *data) { - dev_pm_opp_put_clkname(data); + dev_pm_opp_put_clknames(data); } /** - * devm_pm_opp_set_clkname() - Set clk name for the device - * @dev: Device for which clk name is being set. - * @name: Clk name. + * devm_pm_opp_set_clknames() - Set clock names for the device + * @dev: Device for which clock names are being set. + * @names: Array of pointers to the names of the clocks. + * @count: Number of clocks. * - * This is a resource-managed variant of dev_pm_opp_set_clkname(). + * This is a resource-managed variant of dev_pm_opp_set_clknames(). * * Return: 0 on success and errorno otherwise. */ -int devm_pm_opp_set_clkname(struct device *dev, const char *name) +int devm_pm_opp_set_clknames(struct device *dev, + const char * const names[], + unsigned int count) { struct opp_table *opp_table; - opp_table = dev_pm_opp_set_clkname(dev, name); + opp_table = dev_pm_opp_set_clknames(dev, names, count); if (IS_ERR(opp_table)) return PTR_ERR(opp_table); - return devm_add_action_or_reset(dev, devm_pm_opp_clkname_release, + return devm_add_action_or_reset(dev, devm_pm_opp_clknames_release, opp_table); } -EXPORT_SYMBOL_GPL(devm_pm_opp_set_clkname); +EXPORT_SYMBOL_GPL(devm_pm_opp_set_clknames); /** * dev_pm_opp_register_set_opp_helper() - Register custom set OPP helper @@ -2637,7 +2759,8 @@ int dev_pm_opp_add(struct device *dev, unsigned long freq, unsigned long u_volt) if (IS_ERR(opp_table)) return PTR_ERR(opp_table); - /* Fix regulator count for dynamic OPPs */ + /* Fix regulator/clk count for dynamic OPPs */ + opp_table->clk_count = 1; opp_table->regulator_count = 1; ret = _opp_add_v1(opp_table, dev, freq, u_volt, true); diff --git a/drivers/opp/of.c b/drivers/opp/of.c index 440ab5a03df9..26ab58b71c2d 100644 --- a/drivers/opp/of.c +++ b/drivers/opp/of.c @@ -767,6 +767,47 @@ void dev_pm_opp_of_remove_table(struct device *dev) } EXPORT_SYMBOL_GPL(dev_pm_opp_of_remove_table); +static int _read_clocks(struct dev_pm_opp *opp, struct opp_table *opp_table, + struct device_node *np) +{ + int count, ret; + u64 *freq; + + count = of_property_count_u64_elems(np, "opp-hz"); + if (count < 0) { + pr_err("%s: Invalid %s property (%d)\n", + __func__, of_node_full_name(np), count); + return count; + } + + if (count != opp_table->clk_count) { + pr_err("%s: number of rates %d does not match number of clocks %d in %s\n", + __func__, count, opp_table->clk_count, + of_node_full_name(np)); + return -EINVAL; + } + + freq = kmalloc_array(count, sizeof(*freq), GFP_KERNEL); + if (!freq) + return -ENOMEM; + + ret = of_property_read_u64_array(np, "opp-hz", freq, count); + if (ret) { + pr_err("%s: error parsing %s: %d\n", __func__, + of_node_full_name(np), ret); + ret = -EINVAL; + goto free_freq; + } + + opp->rates = freq; + return 0; + +free_freq: + kfree(freq); + + return ret; +} + static int _read_bw(struct dev_pm_opp *new_opp, struct opp_table *table, struct device_node *np, bool peak) { @@ -827,6 +868,13 @@ static int _read_opp_key(struct dev_pm_opp *new_opp, struct opp_table *table, } *rate_not_available = !!ret; + if (!ret) { + ret = _read_clocks(new_opp, table, np); + /* The properties were found but we failed to parse them */ + if (ret && ret != -ENODEV) + return ret; + } + /* * Bandwidth consists of peak and average (optional) values: * opp-peak-kBps = ; diff --git a/drivers/opp/opp.h b/drivers/opp/opp.h index 45e3a55239a1..2c4502cff3b2 100644 --- a/drivers/opp/opp.h +++ b/drivers/opp/opp.h @@ -60,6 +60,7 @@ extern struct list_head opp_tables, lazy_opp_tables; * @pstate: Device's power domain's performance state. * @rate: Frequency in hertz * @level: Performance level + * @rates: Frequency rates for the clocks. * @supplies: Power supplies voltage/current values * @bandwidth: Interconnect bandwidth values * @clock_latency_ns: Latency (in nanoseconds) of switching to this OPP's @@ -84,6 +85,7 @@ struct dev_pm_opp { unsigned long rate; unsigned int level; + u64 *rates; struct dev_pm_opp_supply *supplies; struct dev_pm_opp_icc_bw *bandwidth; @@ -149,7 +151,9 @@ enum opp_table_access { * @supported_hw: Array of version number to support. * @supported_hw_count: Number of elements in supported_hw array. * @prop_name: A name to postfix to many DT properties, while parsing them. - * @clk: Device's clock handle + * @clks: Device clocks handles + * @clk_count: Number of clocks. Its value can be -1 (uninitialized), 0 (no + * clock handle provided) or > 0 (has clock handles). * @regulators: Supply regulators * @regulator_count: Number of power supply regulators. Its value can be -1 * (uninitialized), 0 (no opp-microvolt property) or > 0 (has opp-microvolt @@ -200,7 +204,8 @@ struct opp_table { unsigned int *supported_hw; unsigned int supported_hw_count; const char *prop_name; - struct clk *clk; + struct clk **clks; + int clk_count; struct regulator **regulators; int regulator_count; struct icc_path **paths; diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 0d85a63a1f78..cb50ccf6f818 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -158,6 +158,13 @@ int devm_pm_opp_set_regulators(struct device *dev, const char * const names[], u struct opp_table *dev_pm_opp_set_clkname(struct device *dev, const char *name); void dev_pm_opp_put_clkname(struct opp_table *opp_table); int devm_pm_opp_set_clkname(struct device *dev, const char *name); +struct opp_table *dev_pm_opp_set_clknames(struct device *dev, + const char * const names[], + unsigned int count); +void dev_pm_opp_put_clknames(struct opp_table *opp_table); +int devm_pm_opp_set_clknames(struct device *dev, + const char * const names[], + unsigned int count); struct opp_table *dev_pm_opp_register_set_opp_helper(struct device *dev, int (*set_opp)(struct dev_pm_set_opp_data *data)); void dev_pm_opp_unregister_set_opp_helper(struct opp_table *opp_table); int devm_pm_opp_register_set_opp_helper(struct device *dev, int (*set_opp)(struct dev_pm_set_opp_data *data)); @@ -386,6 +393,22 @@ static inline int devm_pm_opp_set_clkname(struct device *dev, const char *name) return -EOPNOTSUPP; } +static inline struct opp_table *dev_pm_opp_set_clknames(struct device *dev, + const char * const names[], + unsigned int count) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline void dev_pm_opp_put_clknames(struct opp_table *opp_table) {} + +static inline int devm_pm_opp_set_clknames(struct device *dev, + const char * const names[], + unsigned int count) +{ + return -EOPNOTSUPP; +} + static inline struct opp_table *dev_pm_opp_attach_genpd(struct device *dev, const char * const *names, struct device ***virt_devs) { return ERR_PTR(-EOPNOTSUPP); From patchwork Mon Apr 11 15:43:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 559721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B0A0C4321E for ; Mon, 11 Apr 2022 15:44:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348251AbiDKPqx (ORCPT ); Mon, 11 Apr 2022 11:46:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348208AbiDKPq3 (ORCPT ); Mon, 11 Apr 2022 11:46:29 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7045B846 for ; Mon, 11 Apr 2022 08:44:13 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id z99so10352961ede.5 for ; Mon, 11 Apr 2022 08:44:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fU0hWQzn7l8dJNLIMz5BIxCZUns693+M8CLZSpbHGLA=; b=TMn/tnTA+w5TRa4vNuxS5vEJFOk5yiXG5dLIwTHI+6D9zp71rfgpAnjTEpO4zmD3di hSiK6prSo1T1hrLP4OM47zkcxCeGCa5N71/Mh043fmIZmyoawgPhb9oyqm0hnNcttIgq eo8c0K35dQmvk2Xi29V4HadfSMbrnFl0dnIKXUtPyuve7F32+GnsbY8KZUlrIxV8NU3K ON+HX/M+XVMrMprIQ/U1GhyrBbFH5yKRUhju/TgdlQUnk5iI7nSaznj2TIZXRmxYRGdg qYa+8sxevq25oPSMmILdZRNnK7rSZKDE3eEbIYoFm0jHR1/SjtBBdQosvohu0P5PBLY6 fI4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fU0hWQzn7l8dJNLIMz5BIxCZUns693+M8CLZSpbHGLA=; b=P3t67vkJVhtQbQjIMGx/JCwz3MplR7wLlHUA+jrVG/LFGYs/o/3SyAwHZwU7oB+uMq mQDybjzUB5AY6qmtxaldbg/jKogFcL/d2fJhU88/cZM1zG4ZIBCAc3IlaI8HSE2eNt8u EYDng0RPMgMn4/RYl6lP47wZehzXpVvGFMmSQcDOyxgPY4a8VzGavWGnZpt+kWPU/j39 MiT9+mYT1onYDHTfZmeJOsXeqEA9CftkYf60biY2S8lBahvgxdLJWA6FIhHvPwrTB6Jk MZ+qRLGmXPgtF+8C2SLnlPHngcxfR+49eGrlFCMLm7Vo/zHwo9ExeC79M4Hi/UG9QAzh vybw== X-Gm-Message-State: AOAM533sXy56hWsfkZ1wIts3OF8CzjPq/l24t5YScGF+2YSyT2Vg4ato A/uiUHIXM6SSPqmvOS+xBBbD4g== X-Google-Smtp-Source: ABdhPJyBq4Yl6LDEdydbHJ5/4b8uC0V4SNm/51/Z48/ZlLGb4PTPG74I33M/AeumvQmbioftCHhorw== X-Received: by 2002:a05:6402:11cf:b0:41c:dbc7:79d2 with SMTP id j15-20020a05640211cf00b0041cdbc779d2mr34495460edw.50.1649691851702; Mon, 11 Apr 2022 08:44:11 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id t14-20020a170906608e00b006d1455acc62sm12173177ejj.74.2022.04.11.08.44.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 08:44:11 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Viresh Kumar , Nishanth Menon , Alim Akhtar , Avri Altman , "James E.J. Bottomley" , "Martin K. Petersen" , "Rafael J. Wysocki" , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-scsi@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [RFC PATCH v2 6/6] arm64: dts: qcom: sdm845: control RPMHPD performance states with UFS Date: Mon, 11 Apr 2022 17:43:47 +0200 Message-Id: <20220411154347.491396-7-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220411154347.491396-1-krzysztof.kozlowski@linaro.org> References: <20220411154347.491396-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org UFS, when scaling gears, should choose appropriate performance state of RPMHPD power domain controller. Since UFS belongs to UFS_PHY_GDSC power domain, add necessary parent power domain to GCC. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 43 +++++++++++++++++++++------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b31bf62e8680..920e4b0c71cf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1078,6 +1078,7 @@ gcc: clock-controller@100000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SDM845_CX>; }; qfprom@784000 { @@ -2326,18 +2327,40 @@ ufs_mem_hc: ufshc@1d84000 { <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 300000000>; + operating-points-v2 = <&ufs_opp_table>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000 + 0 + 0 + 37500000 + 0 + 0 + 0 + 0 + // FIXME: value 0 copied from freq-table-hz + 0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000 + 0 + 0 + 150000000 + 0 + 0 + 0 + 0 + 300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ufs_mem_phy: phy@1d87000 {