From patchwork Fri Dec 14 05:23:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153741 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1671352ljp; Thu, 13 Dec 2018 21:24:53 -0800 (PST) X-Google-Smtp-Source: AFSGD/Xgr0F8LObGz0RDWu0WnH39kzXS4syU1kCh0atBlXFrX3favEocS1M+8l/afjVh5JCTCddw X-Received: by 2002:a0c:8b64:: with SMTP id d36mr1416362qvc.233.1544765093729; Thu, 13 Dec 2018 21:24:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765093; cv=none; d=google.com; s=arc-20160816; b=JTF1qaWU/k74E55Xdtcc+IDUw9MSQpdEYrK6nnqPq0avp6IzSuOlzAWlMi5F2FlXvZ L9jN9YNVIsT7zYGPVxsOGkgPkdYUC5iX7TUDz/5+KutGWiZ9IboLW9beh/Www8GA7qS6 CRNiD5RPPbkbQ+3R7bfwELpGCamNXzkTVmA8eI7Az2aIgnm+YAwp2HymD1eeTsNqXQtF m/Qanda62tEau3wszJzr7cG/GGG+gQi0vLHbk3AL5TN9xhSmy3AdUbHIC9oL30n48urE ka90dlcxDVOjevSVE6mvvFnXDS9RL9ArYXE6olHcUZRApygfu065wTxBYsDngknTHX57 UsQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=sXNa5kiWHyvH55kN+5zwG+Y/7FtWzXdt3Wqp2JQJMqU=; b=eME/nAlt1u5CGnZbebmKD4q6/x6bmzGh6CgiqW7YV5bcrzAoaucKGYmcqVvbJDTa0M svEBW7Mo6gHJKFj1HCl9pIxJ3soYhxtMlWyV0yoTFSYDU1tUud29e7MMiQhRtQA8ShbC cdDCwwDuaqTtKb5vdj0EEkOxbMoepyLTT/om56dQDn1V/Q7XUT8SVG2yKCkX12K34Ucm hxYQWoR4RE4epW57M2lfEvuc4FCqXUS//CSCDjDCpdXx3w39VTZ+0GhaAh3oFTMl3GYR NbBnFUVi/KENSyVKMTXZ9xRPGK/sYT3jRgLIAxOfLfntoCq1h0G9H80jB3YPyRntC5DX D9bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cx5uh0mp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o61si693399qte.74.2018.12.13.21.24.53 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:24:53 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cx5uh0mp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59431 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfy1-0004Qf-5h for patch@linaro.org; Fri, 14 Dec 2018 00:24:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55611) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxW-0004On-Bx for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxR-0005Jj-GQ for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:21 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:46940) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxP-0005Iy-K2 for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:15 -0500 Received: by mail-oi1-x242.google.com with SMTP id x202so3606881oif.13 for ; Thu, 13 Dec 2018 21:24:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sXNa5kiWHyvH55kN+5zwG+Y/7FtWzXdt3Wqp2JQJMqU=; b=cx5uh0mprpuMe0TVpAzg1NimXHgNf48Dp37Y6BeZJWtr+1/qbgbrW+7iS/IzO+ENQh YvdAvlf99mMVsCMMkbXrl8PwTegUpSv1CUneIU+62bQj8Yzb8CAlEBceY4Ee2KespvZ9 wTHp3pE17TnGIUznkHyWnvKVQzNLos2XsCLRc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sXNa5kiWHyvH55kN+5zwG+Y/7FtWzXdt3Wqp2JQJMqU=; b=gP/H4+CT7jQwhPGhc/oI1bV0kWmq7/rNIyAGLdem+LD0+NZdcmpP47tB9EarAkoYnj S5ihOyBUk0WANALS+ZKnMLWqhOivz93idosuVyQVq+4WLvaPRdr4o/3ZUVC00SztGiEE cmZ6mAzli+HFLmCqNhpbcOe9zrWexqUdEmts2uMxLnUdHayGZXqN4ju9jwNl0i9NnYqh BST6lZCTaXOsgvENuAhPfIkFS3y4NfxZMhS1zCupuVogwaOcmDq+ZN2/Ma5S7u8UhLzH UESKdYQThpUcOUeoPx+L38I1uCoD+B3BUVSmCt55jKL2znLAaqOgGOV8Sdl+y28Lz2ej PGSQ== X-Gm-Message-State: AA+aEWaVXdVNuUZ4K7TrlpTO+jpZk1vJTNXYSi1rwY/cq6miP4XBmEbr 48BWF59kxX//bgO4BAdhxUvi95qkfTkB3w== X-Received: by 2002:aca:a648:: with SMTP id p69mr950567oie.205.1544765054514; Thu, 13 Dec 2018 21:24:14 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:23:44 -0600 Message-Id: <20181214052410.11863-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v2 01/27] target/arm: Add state for the ARMv8.3-PAuth extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add storage space for the 5 encryption keys. Signed-off-by: Richard Henderson ---- v2: Remove pointless double migration. Use a struct to make it clear which half is which. --- target/arm/cpu.h | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c943f35dd9..39d4afdfe6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -201,11 +201,16 @@ typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; -/* In AArch32 mode, predicate registers do not exist at all. */ #ifdef TARGET_AARCH64 +/* In AArch32 mode, predicate registers do not exist at all. */ typedef struct ARMPredicateReg { uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); } ARMPredicateReg; + +/* In AArch32 mode, PAC keys do not exist at all. */ +typedef struct ARMPACKey { + uint64_t lo, hi; +} ARMPACKey; #endif @@ -605,6 +610,14 @@ typedef struct CPUARMState { uint32_t cregs[16]; } iwmmxt; +#ifdef TARGET_AARCH64 + ARMPACKey apia_key; + ARMPACKey apib_key; + ARMPACKey apda_key; + ARMPACKey apdb_key; + ARMPACKey apga_key; +#endif + #if defined(CONFIG_USER_ONLY) /* For usermode syscall translation. */ int eabi; @@ -3324,6 +3337,21 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; } +static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) +{ + /* + * Note that while QEMU will only implement the architected algorithm + * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation + * defined algorithms, and thus API+GPI, and this predicate controls + * migration of the 128-bit keys. + */ + return (id->id_aa64isar1 & + (FIELD_DP64(0, ID_AA64ISAR1, APA, -1) | + FIELD_DP64(0, ID_AA64ISAR1, API, -1) | + FIELD_DP64(0, ID_AA64ISAR1, GPA, -1) | + FIELD_DP64(0, ID_AA64ISAR1, GPI, -1))) != 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ From patchwork Fri Dec 14 05:23:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153746 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1674307ljp; Thu, 13 Dec 2018 21:30:18 -0800 (PST) X-Google-Smtp-Source: AFSGD/UvjUBB0VQkbDiwEL8SfZThRiWcHUYfv+HK7+yTbn12258nkYj65MmVZN7IiL65dbCbyume X-Received: by 2002:a37:97c1:: with SMTP id z184mr1386436qkd.39.1544765418739; Thu, 13 Dec 2018 21:30:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765418; cv=none; d=google.com; s=arc-20160816; b=CsP7cA2Dj6uy692aghQH0+Abyud0CT3SiduDuyUSNK4plYkA5b2AhfSkuLBt1jssM8 asICdeWDXPEF916woaR8FQcEaq4lseF9B7ZTpJYi5Jg+d9YeReQiExL11hmpUa0l9H0k OnuCXD7MtxGwZVOci9C3lhK975B0nJPQASVXqZPJSX+DvpyuqIm2OHWlsGVQtNhPEj7x N9dGiS5PityvGuxgLjM76oknuhWEojXIY1wy5zUekk8TvcJUgzkADPl8U9JnzgdfsxCN wORYkZCnJW2j2bc3e9Mg9NRTcpdmZWSVKAj/14LfzAQLoHJewNYccxp9+ltD2zVYrYpk RFmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5o/z5l3bO66wgkYApWu4JJ3RvuJtCbD8lHdwebj4GOg=; b=T9cT1xnTJZb4MBOSOsN+CxC26Z0VYCAEbrbjJB5H39gtgZn51t8XVeka9uxfwkGw8A j0SRKX/mQ7kEPGTcs+CTujysF66aPP5i0OBHqUoMjkJ9WykkrYx/OhGd8S165EBlPZJi rtmnznT07UNtZSlzp9RJzcKj/ARaRUCHv0sDyA7rJn88QfOUxD9joBoXEL/2l9TCPFKM MA0uJMjp/oN5HpFeAoT3w990Y0bm6C5bdToOOpcjrvlcLDGWg+5uqrjZa1KlEQ9xD8Vy APeTPEwvHGsMLJtQUA0zDHwROhCoTrpH4HgOq9Pm8DLsVGSJ6mKuuG9AXb6mcTNfDDzp 00CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WaVcDcpL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v2 02/27] target/arm: Add SCTLR bits through ARMv8.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Post v8.4 bits taken from SysReg_v85_xml-00bet8. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Review fixups from Peter. --- target/arm/cpu.h | 45 +++++++++++++++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 12 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 39d4afdfe6..cd2519d43e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -989,12 +989,15 @@ void pmccntr_sync(CPUARMState *env); #define SCTLR_A (1U << 1) #define SCTLR_C (1U << 2) #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ -#define SCTLR_SA (1U << 3) +#define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ +#define SCTLR_SA (1U << 3) /* AArch64 only */ #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ +#define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ +#define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ #define SCTLR_ITD (1U << 7) /* v8 onward */ #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ @@ -1002,35 +1005,53 @@ void pmccntr_sync(CPUARMState *env); #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ #define SCTLR_F (1U << 10) /* up to v6 */ -#define SCTLR_SW (1U << 10) /* v7 onward */ -#define SCTLR_Z (1U << 11) +#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ +#define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ +#define SCTLR_EOS (1U << 11) /* v8.5-ExS */ #define SCTLR_I (1U << 12) -#define SCTLR_V (1U << 13) +#define SCTLR_V (1U << 13) /* AArch32 only */ +#define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ #define SCTLR_RR (1U << 14) /* up to v7 */ #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ #define SCTLR_nTWI (1U << 16) /* v8 onward */ -#define SCTLR_HA (1U << 17) +#define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ #define SCTLR_BR (1U << 17) /* PMSA only */ #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ #define SCTLR_nTWE (1U << 18) /* v8 onward */ #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ -#define SCTLR_UWXN (1U << 20) /* v7 onward */ -#define SCTLR_FI (1U << 21) -#define SCTLR_U (1U << 22) +#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ +#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ +#define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ +#define SCTLR_EIS (1U << 22) /* v8.5-ExS */ #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ +#define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ #define SCTLR_VE (1U << 24) /* up to v7 */ #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ #define SCTLR_EE (1U << 25) #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ -#define SCTLR_NMFI (1U << 27) -#define SCTLR_TRE (1U << 28) -#define SCTLR_AFE (1U << 29) -#define SCTLR_TE (1U << 30) +#define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ +#define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ +#define SCTLR_TRE (1U << 28) /* AArch32 only */ +#define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ +#define SCTLR_AFE (1U << 29) /* AArch32 only */ +#define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ +#define SCTLR_TE (1U << 30) /* AArch32 only */ +#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ +#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ +#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ +#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ +#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ +#define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ +#define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ +#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ +#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ +#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ #define CPTR_TCPAC (1U << 31) #define CPTR_TTA (1U << 20) From patchwork Fri Dec 14 05:23:46 2018 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v2 03/27] target/arm: Add PAuth active bit to tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are 5 bits of state that could be added, but to save space within tbflags, add only a single enable bit. Helpers will determine the rest of the state at runtime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Fix whitespace, comment grammar. --- target/arm/cpu.h | 4 ++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 19 +++++++++++++++++++ target/arm/translate-a64.c | 1 + 4 files changed, 26 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cd2519d43e..898243c93e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3032,6 +3032,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) #define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) #define ARM_TBFLAG_ZCR_LEN_SHIFT 4 #define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) +#define ARM_TBFLAG_PAUTH_ACTIVE_SHIFT 8 +#define ARM_TBFLAG_PAUTH_ACTIVE_MASK (1ull << ARM_TBFLAG_PAUTH_ACTIVE_SHIFT) /* some convenience accessor macros */ #define ARM_TBFLAG_AARCH64_STATE(F) \ @@ -3074,6 +3076,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) #define ARM_TBFLAG_ZCR_LEN(F) \ (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) +#define ARM_TBFLAG_PAUTH_ACTIVE(F) \ + (((F) & ARM_TBFLAG_PAUTH_ACTIVE_MASK) >> ARM_TBFLAG_PAUTH_ACTIVE_SHIFT) static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 1550aa8bc7..d8a8bb4e9c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -68,6 +68,8 @@ typedef struct DisasContext { bool is_ldex; /* True if a single-step exception will be taken to the current EL */ bool ss_same_el; + /* True if v8.3-PAuth is active. */ + bool pauth_active; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 644599b29d..bd0cff5c27 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12981,6 +12981,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags |= sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; flags |= zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; } + + if (cpu_isar_feature(aa64_pauth, cpu)) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + uint64_t sctlr; + if (current_el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr = env->cp15.sctlr_el[1]; + } else { + sctlr = env->cp15.sctlr_el[current_el]; + } + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags |= ARM_TBFLAG_PAUTH_ACTIVE_MASK; + } + } } else { *pc = env->regs[15]; flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e1da1e4d6f..7c1cc1ce8e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13407,6 +13407,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->sve_excp_el = ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags); dc->sve_len = (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16; + dc->pauth_active = ARM_TBFLAG_PAUTH_ACTIVE(dc->base.tb->flags); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Fri Dec 14 05:23:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153748 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1674344ljp; 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X-Received-From: 2607:f8b0:4864:20::236 Subject: [Qemu-devel] [PATCH v2 04/27] target/arm: Add PAuth helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The cryptographic internals are stubbed out for now, but the enable and trap bits are checked. Signed-off-by: Richard Henderson ---- v2: Remove trap from xpac* helpers; these are now side-effect free. Use struct ARMPACKey. --- target/arm/helper-a64.h | 12 +++ target/arm/internals.h | 6 ++ target/arm/helper-a64.c | 166 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 184 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 9d3a907049..28aa0af69d 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -85,3 +85,15 @@ DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) + +DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacdb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacga, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autia, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autib, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) +DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index 78e026d6e9..6bc0daf560 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -259,6 +259,7 @@ enum arm_exception_class { EC_CP14DTTRAP = 0x06, EC_ADVSIMDFPACCESSTRAP = 0x07, EC_FPIDTRAP = 0x08, + EC_PACTRAP = 0x09, EC_CP14RRTTRAP = 0x0c, EC_ILLEGALSTATE = 0x0e, EC_AA32_SVC = 0x11, @@ -426,6 +427,11 @@ static inline uint32_t syn_sve_access_trap(void) return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; } +static inline uint32_t syn_pactrap(void) +{ + return EC_PACTRAP << ARM_EL_EC_SHIFT; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 61799d20e1..bb64700e10 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -898,4 +898,170 @@ uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp) return float16_sqrt(a, s); } +/* + * Helpers for ARMv8.3-PAuth. + */ +static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, + ARMPACKey key) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, + ARMPACKey *key, bool data) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, + ARMPACKey *key, bool data, int keynumber) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) +{ + g_assert_not_reached(); /* FIXME */ +} + +static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, + uintptr_t ra) +{ + CPUState *cs = ENV_GET_CPU(env); + + cs->exception_index = EXCP_UDEF; + env->exception.syndrome = syn_pactrap(); + env->exception.target_el = target_el; + cpu_loop_exit_restore(cs, ra); +} + +static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra) +{ + if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + uint64_t hcr = arm_hcr_el2_eff(env); + bool trap = !(hcr & HCR_API); + /* FIXME: ARMv8.1-VHE: trap only applies to EL1&0 regime. */ + /* FIXME: ARMv8.3-NV: HCR_NV trap takes precedence for ERETA[AB]. */ + if (trap) { + pauth_trap(env, 2, ra); + } + } + if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { + if (!(env->cp15.scr_el3 & SCR_API)) { + pauth_trap(env, 3, ra); + } + } +} + +static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit) +{ + uint32_t sctlr; + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr = env->cp15.sctlr_el[1]; + } else { + sctlr = env->cp15.sctlr_el[el]; + } + return (sctlr & bit) != 0; +} + +uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apia_key, false); +} + +uint64_t HELPER(pacib)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apib_key, false); +} + +uint64_t HELPER(pacda)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apda_key, true); +} + +uint64_t HELPER(pacdb)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apdb_key, true); +} + +uint64_t HELPER(pacga)(CPUARMState *env, uint64_t x, uint64_t y) +{ + uint64_t pac; + + pauth_check_trap(env, arm_current_el(env), GETPC()); + pac = pauth_computepac(x, y, env->apga_key); + + return pac & 0xffffffff00000000ull; +} + +uint64_t HELPER(autia)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apia_key, false, 0); +} + +uint64_t HELPER(autib)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apib_key, false, 1); +} + +uint64_t HELPER(autda)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apda_key, true, 0); +} + +uint64_t HELPER(autdb)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apdb_key, true, 1); +} + +uint64_t HELPER(xpaci)(CPUARMState *env, uint64_t a) +{ + return pauth_strip(env, a, false); +} + +uint64_t HELPER(xpacd)(CPUARMState *env, uint64_t a) +{ + return pauth_strip(env, a, true); +} From patchwork Fri Dec 14 05:23:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153744 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1672765ljp; Thu, 13 Dec 2018 21:27:26 -0800 (PST) X-Google-Smtp-Source: AFSGD/WdgZufKXGdqZW4Zh7aZ7oX+b/aa2pIKkzOX9z0RqU7vxQDtaNJUk2KcqvlSLwaITn8ykT6 X-Received: by 2002:aed:2946:: with SMTP id s64mr1440860qtd.383.1544765246225; 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X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v2 05/27] target/arm: Decode PAuth within system hint space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 93 +++++++++++++++++++++++++++++++++----- 1 file changed, 81 insertions(+), 12 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7c1cc1ce8e..0df344f9e8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1471,33 +1471,102 @@ static void handle_hint(DisasContext *s, uint32_t insn, } switch (selector) { - case 0: /* NOP */ - return; - case 3: /* WFI */ + case 000: /* NOP */ + break; + case 003: /* WFI */ s->base.is_jmp = DISAS_WFI; - return; + break; + case 001: /* YIELD */ /* When running in MTTCG we don't generate jumps to the yield and * WFE helpers as it won't affect the scheduling of other vCPUs. * If we wanted to more completely model WFE/SEV so we don't busy * spin unnecessarily we would need to do something more involved. */ - case 1: /* YIELD */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { s->base.is_jmp = DISAS_YIELD; } - return; - case 2: /* WFE */ + break; + case 002: /* WFE */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { s->base.is_jmp = DISAS_WFE; } - return; - case 4: /* SEV */ - case 5: /* SEVL */ + break; + case 004: /* SEV */ + case 005: /* SEVL */ /* we treat all as NOP at least for now */ - return; + break; + case 007: /* XPACLRI */ + if (s->pauth_active) { + gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); + } + break; + case 010: /* PACIA1716 */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 012: /* PACIB1716 */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 014: /* AUTIA1716 */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 016: /* AUTIB1716 */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 030: /* PACIAZ */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 031: /* PACIASP */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 032: /* PACIBZ */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 033: /* PACIBSP */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 034: /* AUTIAZ */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 035: /* AUTIASP */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 036: /* AUTIBZ */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 037: /* AUTIBSP */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; default: /* default specified as NOP equivalent */ - return; + break; } } From patchwork Fri Dec 14 05:23:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153747 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1674343ljp; Thu, 13 Dec 2018 21:30:21 -0800 (PST) X-Google-Smtp-Source: AFSGD/VI8PXH+9YX1nxE+O3RfrelVvs32pZC9MnUvp3POCkoSWSZOeyWhOzuNdfM868aHGk9MKWb X-Received: by 2002:a0c:91e8:: with SMTP id r37mr1448605qvr.141.1544765421359; Thu, 13 Dec 2018 21:30:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765421; cv=none; d=google.com; s=arc-20160816; b=CiEdhPo/PzH5qkWWfwCur3xj72XLnOtQmQ7n+HtwLbtd7Gkk3wn1O5VrDTyzUfUo3n 3FfG3wHM9rhDMqvk0p10s0KUJLlVHFHwrmI6EanaYANoO+jzz4xBaswMU775XDmOaqxL V1DIvqnC9xdGcNPAvYV/f1E1ozqmWp2ArgZfK7LoDBaiOiloHYNgxWDTxJ9MlFosd2jE ywWIX8xRaRo4dnvI4tgRKU8JthhjR+xHIatc8ZtUiV6saeTTIeK2VPPX0q6pLUoqZI04 /6D6ulPsxzezlUXFYMg5tL9ZhJdGAMW7/30mJ8nNVQPqaTxmdmOdt+bfUcoTiU3BRRY1 8CwQ== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id b10si2235270qvt.55.2018.12.13.21.30.21 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:30:21 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Xf3nTQc0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59453 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXg3I-0000SX-PD for patch@linaro.org; Fri, 14 Dec 2018 00:30:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxY-0004PG-Dj for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxX-0005Lw-Dl for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:24 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:44186) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxX-0005Ks-6l for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:23 -0500 Received: by mail-ot1-x341.google.com with SMTP id f18so4281441otl.11 for ; Thu, 13 Dec 2018 21:24:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xLK16dXcE1/3hAYx2nGnEtmWP589qVwfWbOpdPd0plw=; b=Xf3nTQc0H9HVcepn6LCmp1rYokJCRWCJFlb3hSk49XOxweD0Q2TYfjFpMOOJ034RQr Mg6VDBkXcNoN1ffI2r+YZ7AU6+x3VnVS0fBtoRwpqihyKxqPGpKLVSyBK5GkUAtaykfW erxEH034cRxM01xC/4uj7JCIcrFr9tkG+7v/A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xLK16dXcE1/3hAYx2nGnEtmWP589qVwfWbOpdPd0plw=; b=jb+cBAE9Fy2GSSTz0DOJ9HXzozjYG5VO//PVUXnAXhGVlBiKnmxwgf0anUPKB1KIM6 p9xmx3C8XQrJlb1kobaIousfnx5HCXJalHkGcEf/AmR3HYSo1IFKXC5meJEPqQV46m/R 9HAb45WlzE/NAKESyCptKDAw1K+nY+n11dU1PzcnOeR+tKuzAIAONO5NNGHgsHWJhICB TMJnp8LeQMtg0Yoak+c3sNkNSOEZtYzA7sqLdy9DQch+AOZmnS+ujbGK8aCQNQS9rxJI CZwgsmaU+U3cmM2kue0OdETt3DpI6dWoFKohVenNuCDQFt+R3YCFxCtNWiSGxNNzTOyM WAHQ== X-Gm-Message-State: AA+aEWbRdcRGwg4UhRfJIHUshok5RMhOT3HxIgwnvMkU8d7DDRnPKyhc Ssndh3WVluZRZfjf3i0EQJbq5KnpugBLQA== X-Received: by 2002:a9d:332:: with SMTP id 47mr1248190otv.260.1544765060305; Thu, 13 Dec 2018 21:24:20 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:23:49 -0600 Message-Id: <20181214052410.11863-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v2 06/27] target/arm: Rearrange decode in disas_data_proc_1src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now properly signals unallocated for REV64 with SF=0. Allows for the opcode2 field to be decoded shortly. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0df344f9e8..c5ec430b42 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4563,38 +4563,51 @@ static void handle_rev16(DisasContext *s, unsigned int sf, */ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { - unsigned int sf, opcode, rn, rd; + unsigned int sf, opcode, opcode2, rn, rd; - if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { + if (extract32(insn, 29, 1)) { unallocated_encoding(s); return; } sf = extract32(insn, 31, 1); opcode = extract32(insn, 10, 6); + opcode2 = extract32(insn, 16, 5); rn = extract32(insn, 5, 5); rd = extract32(insn, 0, 5); - switch (opcode) { - case 0: /* RBIT */ +#define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7)) + + switch (MAP(sf, opcode2, opcode)) { + case MAP(0, 0x00, 0x00): /* RBIT */ + case MAP(1, 0x00, 0x00): handle_rbit(s, sf, rn, rd); break; - case 1: /* REV16 */ + case MAP(0, 0x00, 0x01): /* REV16 */ + case MAP(1, 0x00, 0x01): handle_rev16(s, sf, rn, rd); break; - case 2: /* REV32 */ + case MAP(0, 0x00, 0x02): /* REV/REV32 */ + case MAP(1, 0x00, 0x02): handle_rev32(s, sf, rn, rd); break; - case 3: /* REV64 */ + case MAP(1, 0x00, 0x03): /* REV64 */ handle_rev64(s, sf, rn, rd); break; - case 4: /* CLZ */ + case MAP(0, 0x00, 0x04): /* CLZ */ + case MAP(1, 0x00, 0x04): handle_clz(s, sf, rn, rd); break; - case 5: /* CLS */ + case MAP(0, 0x00, 0x05): /* CLS */ + case MAP(1, 0x00, 0x05): handle_cls(s, sf, rn, rd); break; + default: + unallocated_encoding(s); + break; } + +#undef MAP } static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, From patchwork Fri Dec 14 05:23:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153756 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1678504ljp; Thu, 13 Dec 2018 21:37:05 -0800 (PST) X-Google-Smtp-Source: AFSGD/W20PKfFdzsKnmQkDdmOQ9t7eEkhv5CbZbdCCOxzvWZKlyP1IVRk6kAoiBoiTB3Z852YmLx X-Received: by 2002:a0c:d1f5:: with SMTP id k50mr1483612qvh.247.1544765825039; Thu, 13 Dec 2018 21:37:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765825; cv=none; d=google.com; s=arc-20160816; b=SsB+NYPXeaKvg8kfNWdlpyDig9Dplqs0xeh9z2zWLOQL7ZEyRZYkuxkuyhbEvic5GW iV0ngo64oqvejpAYAAe0k9De19AkkxCgolbFHm1Atg8dGseqPwha+/1L8KeHg++OpnrM ybxujL55OsiCzMQu3MVbtXvc8WqyaW9Uj+cIvq+rjUf3Z+sCzyNN8ez3PLgMrcSncG9K w2Q4I5FS6PNia607HDxcgXNBZChqbcxHQl5AJsDjEXGDCIQnmKo2MN8w+yRq3vn9w2Vg DRtbtHB4llWo8U07cG7Q3QbwDpKZdE8H+nZvPZfXfJ5/NIBbck+92xJFwwvJIj024XKn GdtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=qQ2kBkEIooqXMwtWosEViqdXhdu/HbTiJ7UnjMq3Or0=; b=k2pP4h+Pa/62fIWi0e6d4iTwBnrboTAT5wiyX52wF8Al/yeLvW7AX+yhPRVn/dWhgb BPX9m0Dt7DjdCIOSTwZ/oMccBjRPJAQ5pULQynWDSsYyLOwzav3vqDhNjkjw59c2h6Bw SEMUDx9K50nMXwJChw/H0gMxtEI/nLSN7nNRI+y5A+EhCP8UgqtrQ7fLQAsWpKA0cbGV 3I6W4oR18A1jWr3aaFcPdu00D5k4HXcJ7eMD/wQPQiikGs76QOlF/VJ6jrfdTNih69Bn 4Z5JsKh8SA/MmaYBdIjh2v58hl3Q8QLDLPTJihxcSc4em3hN/XnZ7YAy9EI2ZUa/yZNW svDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kf3MoZ1D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v2 07/27] target/arm: Decode PAuth within disas_data_proc_1src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 146 +++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c5ec430b42..7ba4c996cf 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4564,6 +4564,7 @@ static void handle_rev16(DisasContext *s, unsigned int sf, static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { unsigned int sf, opcode, opcode2, rn, rd; + TCGv_i64 tcg_rd; if (extract32(insn, 29, 1)) { unallocated_encoding(s); @@ -4602,7 +4603,152 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) case MAP(1, 0x00, 0x05): handle_cls(s, sf, rn, rd); break; + case MAP(1, 0x01, 0x00): /* PACIA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x01): /* PACIB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x02): /* PACDA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x03): /* PACDB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x04): /* AUTIA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x05): /* AUTIB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x06): /* AUTDA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x07): /* AUTDB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x08): /* PACIZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x09): /* PACIZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0a): /* PACDZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0b): /* PACDZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0c): /* AUTIZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0d): /* AUTIZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0e): /* AUTDZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0f): /* AUTDZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x10): /* XPACI */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd); + } + break; + case MAP(1, 0x01, 0x11): /* XPACD */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd); + } + break; default: + do_unallocated: unallocated_encoding(s); break; } From patchwork Fri Dec 14 05:23:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153753 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1676752ljp; Thu, 13 Dec 2018 21:34:14 -0800 (PST) X-Google-Smtp-Source: AFSGD/VpREntDl/qbuRxkL8JUASqegI1SZjOL/K/PcA9Zt6wleufBS8xs8/R0vRbZlxZ71UM4M7W X-Received: by 2002:a0c:98ca:: with SMTP id g10mr1497702qvd.13.1544765653916; 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X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v2 08/27] target/arm: Decode PAuth within disas_data_proc_2src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7ba4c996cf..d034a5edf3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4884,6 +4884,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) case 11: /* RORV */ handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); break; + case 12: /* PACGA */ + if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + gen_helper_pacga(cpu_reg(s, rd), cpu_env, + cpu_reg(s, rn), cpu_reg_sp(s, rm)); + break; case 16: case 17: case 18: @@ -4899,6 +4906,7 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) break; } default: + do_unallocated: unallocated_encoding(s); break; } From patchwork Fri Dec 14 05:23:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153759 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1679986ljp; Thu, 13 Dec 2018 21:39:47 -0800 (PST) X-Google-Smtp-Source: AFSGD/XfTwnoxB7Qk7BNB47TYHrIRxIPihmGc1K8lr/+9c+x8kVV0KxoTCDg0wKQ0hU37OGO8OzZ X-Received: by 2002:a37:298f:: with SMTP id p15mr1376966qkp.327.1544765986986; Thu, 13 Dec 2018 21:39:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765986; cv=none; d=google.com; s=arc-20160816; b=0ZMftI95wKp38zsFUEWlgULlQO2eLmJH2VI01nlfJf539ANwbPkGZJQrnWeusMinI/ eBXPEU0amSyjrI29bWaaWJxOYMV9WoFzf5LUVUP1tYOWtQGRBmwCe0aN8l756zPu5nBz TKLMZWpDxawgnTaYrHqFAAZu4+1OosDfNB/iKgRv8NpABJhfn80ApEN9bsr+ofuSNdW4 6fBYoVGTd18eLvAVDSlfDuq6k9xygvOWDzDfi/ZwrGCghni+Qn/q0GLAphQaSBM/12sc xfgU13KI/ic+XsrE1xkWUl68u94SqIz363hq+i/2Bi3bTRjGY1RMs2zXeErx07IAhpRn B53g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=803Yw2OXJqRSKdeY9Wz9b9X5C0iN/r0nE17YIv2B6sg=; b=AQA/KrAoIUK545vGDgtVZY9lE/tG3NJT+pOUn2opXzt15ymavn+bp17VXvx95wNP2y FiZzi3UMwUc78HPBvP7JHwEd2zev2uy14lnVzTx9s97+1Zy6WMHHAJCH1F884Bl95laL yOOUF6c7f964Sjmomwa1Py/04a/JrCAoilu0Uy7qreKIq5d8i0EMr3BdrYjOFm2cEj7C 4+53TWcQ2icoBQ/AbaQBH1HfPVGhw7d52LZdj+AkHjcyHULH4rlm8pGXwSTrE8ohf43g BD0nU3fcMNfs39KBW5yqYvc9q09qL9Z2lH+VFDoAzRqeeOgCDFZhUlDpXgPpuDB/GTk5 lDxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C+VBhPKn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v2 09/27] target/arm: Move helper_exception_return to helper-a64.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is only used by AArch64. Code movement only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 + target/arm/helper.h | 1 - target/arm/helper-a64.c | 155 ++++++++++++++++++++++++++++++++++++++++ target/arm/op_helper.c | 155 ---------------------------------------- 4 files changed, 157 insertions(+), 156 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 28aa0af69d..55299896c4 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -86,6 +86,8 @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) +DEF_HELPER_1(exception_return, void, env) + DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/helper.h b/target/arm/helper.h index 8c9590091b..53a38188c6 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -79,7 +79,6 @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr) DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) DEF_HELPER_1(clear_pstate_ss, void, env) -DEF_HELPER_1(exception_return, void, env) DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bb64700e10..f70c8d9818 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -887,6 +887,161 @@ uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp) return float16_to_uint16(a, fpst); } +static int el_from_spsr(uint32_t spsr) +{ + /* Return the exception level that this SPSR is requesting a return to, + * or -1 if it is invalid (an illegal return) + */ + if (spsr & PSTATE_nRW) { + switch (spsr & CPSR_M) { + case ARM_CPU_MODE_USR: + return 0; + case ARM_CPU_MODE_HYP: + return 2; + case ARM_CPU_MODE_FIQ: + case ARM_CPU_MODE_IRQ: + case ARM_CPU_MODE_SVC: + case ARM_CPU_MODE_ABT: + case ARM_CPU_MODE_UND: + case ARM_CPU_MODE_SYS: + return 1; + case ARM_CPU_MODE_MON: + /* Returning to Mon from AArch64 is never possible, + * so this is an illegal return. + */ + default: + return -1; + } + } else { + if (extract32(spsr, 1, 1)) { + /* Return with reserved M[1] bit set */ + return -1; + } + if (extract32(spsr, 0, 4) == 1) { + /* return to EL0 with M[0] bit set */ + return -1; + } + return extract32(spsr, 2, 2); + } +} + +void HELPER(exception_return)(CPUARMState *env) +{ + int cur_el = arm_current_el(env); + unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); + uint32_t spsr = env->banked_spsr[spsr_idx]; + int new_el; + bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; + + aarch64_save_sp(env, cur_el); + + arm_clear_exclusive(env); + + /* We must squash the PSTATE.SS bit to zero unless both of the + * following hold: + * 1. debug exceptions are currently disabled + * 2. singlestep will be active in the EL we return to + * We check 1 here and 2 after we've done the pstate/cpsr write() to + * transition to the EL we're going to. + */ + if (arm_generate_debug_exceptions(env)) { + spsr &= ~PSTATE_SS; + } + + new_el = el_from_spsr(spsr); + if (new_el == -1) { + goto illegal_return; + } + if (new_el > cur_el + || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { + /* Disallow return to an EL which is unimplemented or higher + * than the current one. + */ + goto illegal_return; + } + + if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) { + /* Return to an EL which is configured for a different register width */ + goto illegal_return; + } + + if (new_el == 2 && arm_is_secure_below_el3(env)) { + /* Return to the non-existent secure-EL2 */ + goto illegal_return; + } + + if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { + goto illegal_return; + } + + qemu_mutex_lock_iothread(); + arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + + if (!return_to_aa64) { + env->aarch64 = 0; + /* We do a raw CPSR write because aarch64_sync_64_to_32() + * will sort the register banks out for us, and we've already + * caught all the bad-mode cases in el_from_spsr(). + */ + cpsr_write(env, spsr, ~0, CPSRWriteRaw); + if (!arm_singlestep_active(env)) { + env->uncached_cpsr &= ~PSTATE_SS; + } + aarch64_sync_64_to_32(env); + + if (spsr & CPSR_T) { + env->regs[15] = env->elr_el[cur_el] & ~0x1; + } else { + env->regs[15] = env->elr_el[cur_el] & ~0x3; + } + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " + "AArch32 EL%d PC 0x%" PRIx32 "\n", + cur_el, new_el, env->regs[15]); + } else { + env->aarch64 = 1; + pstate_write(env, spsr); + if (!arm_singlestep_active(env)) { + env->pstate &= ~PSTATE_SS; + } + aarch64_restore_sp(env, new_el); + env->pc = env->elr_el[cur_el]; + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " + "AArch64 EL%d PC 0x%" PRIx64 "\n", + cur_el, new_el, env->pc); + } + /* + * Note that cur_el can never be 0. If new_el is 0, then + * el0_a64 is return_to_aa64, else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); + + qemu_mutex_lock_iothread(); + arm_call_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + + return; + +illegal_return: + /* Illegal return events of various kinds have architecturally + * mandated behaviour: + * restore NZCV and DAIF from SPSR_ELx + * set PSTATE.IL + * restore PC from ELR_ELx + * no change to exception level, execution state or stack pointer + */ + env->pstate |= PSTATE_IL; + env->pc = env->elr_el[cur_el]; + spsr &= PSTATE_NZCV | PSTATE_DAIF; + spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); + pstate_write(env, spsr); + if (!arm_singlestep_active(env)) { + env->pstate &= ~PSTATE_SS; + } + qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " + "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc); +} + /* * Square Root and Reciprocal square root */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ef72361a36..24229981cd 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1014,161 +1014,6 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) } } -static int el_from_spsr(uint32_t spsr) -{ - /* Return the exception level that this SPSR is requesting a return to, - * or -1 if it is invalid (an illegal return) - */ - if (spsr & PSTATE_nRW) { - switch (spsr & CPSR_M) { - case ARM_CPU_MODE_USR: - return 0; - case ARM_CPU_MODE_HYP: - return 2; - case ARM_CPU_MODE_FIQ: - case ARM_CPU_MODE_IRQ: - case ARM_CPU_MODE_SVC: - case ARM_CPU_MODE_ABT: - case ARM_CPU_MODE_UND: - case ARM_CPU_MODE_SYS: - return 1; - case ARM_CPU_MODE_MON: - /* Returning to Mon from AArch64 is never possible, - * so this is an illegal return. - */ - default: - return -1; - } - } else { - if (extract32(spsr, 1, 1)) { - /* Return with reserved M[1] bit set */ - return -1; - } - if (extract32(spsr, 0, 4) == 1) { - /* return to EL0 with M[0] bit set */ - return -1; - } - return extract32(spsr, 2, 2); - } -} - -void HELPER(exception_return)(CPUARMState *env) -{ - int cur_el = arm_current_el(env); - unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); - uint32_t spsr = env->banked_spsr[spsr_idx]; - int new_el; - bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; - - aarch64_save_sp(env, cur_el); - - arm_clear_exclusive(env); - - /* We must squash the PSTATE.SS bit to zero unless both of the - * following hold: - * 1. debug exceptions are currently disabled - * 2. singlestep will be active in the EL we return to - * We check 1 here and 2 after we've done the pstate/cpsr write() to - * transition to the EL we're going to. - */ - if (arm_generate_debug_exceptions(env)) { - spsr &= ~PSTATE_SS; - } - - new_el = el_from_spsr(spsr); - if (new_el == -1) { - goto illegal_return; - } - if (new_el > cur_el - || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { - /* Disallow return to an EL which is unimplemented or higher - * than the current one. - */ - goto illegal_return; - } - - if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) { - /* Return to an EL which is configured for a different register width */ - goto illegal_return; - } - - if (new_el == 2 && arm_is_secure_below_el3(env)) { - /* Return to the non-existent secure-EL2 */ - goto illegal_return; - } - - if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { - goto illegal_return; - } - - qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); - qemu_mutex_unlock_iothread(); - - if (!return_to_aa64) { - env->aarch64 = 0; - /* We do a raw CPSR write because aarch64_sync_64_to_32() - * will sort the register banks out for us, and we've already - * caught all the bad-mode cases in el_from_spsr(). - */ - cpsr_write(env, spsr, ~0, CPSRWriteRaw); - if (!arm_singlestep_active(env)) { - env->uncached_cpsr &= ~PSTATE_SS; - } - aarch64_sync_64_to_32(env); - - if (spsr & CPSR_T) { - env->regs[15] = env->elr_el[cur_el] & ~0x1; - } else { - env->regs[15] = env->elr_el[cur_el] & ~0x3; - } - qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " - "AArch32 EL%d PC 0x%" PRIx32 "\n", - cur_el, new_el, env->regs[15]); - } else { - env->aarch64 = 1; - pstate_write(env, spsr); - if (!arm_singlestep_active(env)) { - env->pstate &= ~PSTATE_SS; - } - aarch64_restore_sp(env, new_el); - env->pc = env->elr_el[cur_el]; - qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " - "AArch64 EL%d PC 0x%" PRIx64 "\n", - cur_el, new_el, env->pc); - } - /* - * Note that cur_el can never be 0. If new_el is 0, then - * el0_a64 is return_to_aa64, else el0_a64 is ignored. - */ - aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); - - qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); - qemu_mutex_unlock_iothread(); - - return; - -illegal_return: - /* Illegal return events of various kinds have architecturally - * mandated behaviour: - * restore NZCV and DAIF from SPSR_ELx - * set PSTATE.IL - * restore PC from ELR_ELx - * no change to exception level, execution state or stack pointer - */ - env->pstate |= PSTATE_IL; - env->pc = env->elr_el[cur_el]; - spsr &= PSTATE_NZCV | PSTATE_DAIF; - spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); - pstate_write(env, spsr); - if (!arm_singlestep_active(env)) { - env->pstate &= ~PSTATE_SS; - } - qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " - "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc); -} - /* Return true if the linked breakpoint entry lbn passes its checks */ static bool linked_bp_matches(ARMCPU *cpu, int lbn) { From patchwork Fri Dec 14 05:23:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153750 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1676435ljp; Thu, 13 Dec 2018 21:33:39 -0800 (PST) X-Google-Smtp-Source: AFSGD/VCptr6lTPL1+tLibIrr03nKP7F4cpce4J/L+78hshHSFhXC6hfohc2fEtQIpUNGFtu5ErE X-Received: by 2002:ac8:1b34:: with SMTP id y49mr1539382qtj.374.1544765619119; Thu, 13 Dec 2018 21:33:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765619; cv=none; d=google.com; s=arc-20160816; b=W3jeHp6iZWwPVAmcQO6PscoZN7PQNxb3i5uinVfnHo3TBCUKS7BV8zM7Cjp9YlR+2D GzB7ehMDvFFybBDUzCoZcXTNPhASUOS5ryKLDwdjIPDu66OEIQwuMQyPMFNVS90UDOr7 q0SMb7/kRupBM1C7N1sePStUQl+C7Hct6VFAoGJ/5Nu45Y/XkwoRZ81G+2WquXx1TvpA GE/EmmzaitEFFrxppkGv1XUy1EWjZao8WA7WXIgBbGKGCVueU+2WErv8oQAH44p+UHou Dtz7AtOUuoFD49rc9ZgarFEptrHdhSMxFQFNgmRpc4PbPLK1qmRWW1LXjDi8WHcCUkkk aqCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=mPTleWvG/khzrsFEcdVNmfNlDqu5p82Vi8rcgi/0BXg=; b=pVpXfcudLNcg1G5caIKa/PWNyAJqEve9Ya1iCXALPurR2+MIayiJ5OG24B7fipxbAl ll1c29Omk41u1qKMhB/1Rl8rd1cfoV/kktbOVIA9T/QLuepYxDCML28B/z6XJ+SIk6Uo iFGMZAYySCStF6KBp18+t6boKtf6/poUNzA5p/DV4zKTW/C5FrrbwjyrwmlSVShvxMGZ rYBC2Bqbn4b50wJcNTot3F3CTBtPgySVX5dOE2ZKgIVTCs+d5f7C1+TUyPV+Ti13T/qD wHThpdW12K0HLMiRGBHKYlUX0H8U40kbor52tUc4HrYVJlAF6I3T70rM3aNMURdcl8rZ s09w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YbP9kF7U; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::236 Subject: [Qemu-devel] [PATCH v2 10/27] target/arm: Add new_pc argument to helper_exception_return X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 +- target/arm/helper-a64.c | 10 +++++----- target/arm/translate-a64.c | 7 ++++++- 3 files changed, 12 insertions(+), 7 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 55299896c4..aff8d6c9f3 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -86,7 +86,7 @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) -DEF_HELPER_1(exception_return, void, env) +DEF_HELPER_2(exception_return, void, env, i64) DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index f70c8d9818..79cc9cf47b 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -925,7 +925,7 @@ static int el_from_spsr(uint32_t spsr) } } -void HELPER(exception_return)(CPUARMState *env) +void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { int cur_el = arm_current_el(env); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); @@ -991,9 +991,9 @@ void HELPER(exception_return)(CPUARMState *env) aarch64_sync_64_to_32(env); if (spsr & CPSR_T) { - env->regs[15] = env->elr_el[cur_el] & ~0x1; + env->regs[15] = new_pc & ~0x1; } else { - env->regs[15] = env->elr_el[cur_el] & ~0x3; + env->regs[15] = new_pc & ~0x3; } qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", @@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env) env->pstate &= ~PSTATE_SS; } aarch64_restore_sp(env, new_el); - env->pc = env->elr_el[cur_el]; + env->pc = new_pc; qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); @@ -1031,7 +1031,7 @@ illegal_return: * no change to exception level, execution state or stack pointer */ env->pstate |= PSTATE_IL; - env->pc = env->elr_el[cur_el]; + env->pc = new_pc; spsr &= PSTATE_NZCV | PSTATE_DAIF; spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); pstate_write(env, spsr); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d034a5edf3..c84c2dbb66 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1981,6 +1981,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; + TCGv_i64 dst; opc = extract32(insn, 21, 4); op2 = extract32(insn, 16, 5); @@ -2011,7 +2012,11 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - gen_helper_exception_return(cpu_env); + dst = tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + gen_helper_exception_return(cpu_env, dst); + tcg_temp_free_i64(dst); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } From patchwork Fri Dec 14 05:23:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153762 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1682135ljp; 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X-Received-From: 2607:f8b0:4864:20::230 Subject: [Qemu-devel] [PATCH v2 11/27] target/arm: Rearrange decode in disas_uncond_b_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will enable PAuth decode in a subsequent patch. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 47 +++++++++++++++++++++++++++++--------- 1 file changed, 36 insertions(+), 11 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c84c2dbb66..30086a5d7f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1989,32 +1989,54 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) rn = extract32(insn, 5, 5); op4 = extract32(insn, 0, 5); - if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { - unallocated_encoding(s); - return; + if (op2 != 0x1f) { + goto do_unallocated; } switch (opc) { case 0: /* BR */ case 1: /* BLR */ case 2: /* RET */ - gen_a64_set_pc(s, cpu_reg(s, rn)); + switch (op3) { + case 0: + if (op4 != 0) { + goto do_unallocated; + } + dst = cpu_reg(s, rn); + break; + + default: + goto do_unallocated; + } + + gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc == 1) { tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); } break; + case 4: /* ERET */ if (s->current_el == 0) { - unallocated_encoding(s); - return; + goto do_unallocated; + } + switch (op3) { + case 0: + if (op4 != 0) { + goto do_unallocated; + } + dst = tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + break; + + default: + goto do_unallocated; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - dst = tcg_temp_new_i64(); - tcg_gen_ld_i64(dst, cpu_env, - offsetof(CPUARMState, elr_el[s->current_el])); + gen_helper_exception_return(cpu_env, dst); tcg_temp_free_i64(dst); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { @@ -2023,14 +2045,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) /* Must exit loop to check un-masked IRQs */ s->base.is_jmp = DISAS_EXIT; return; + case 5: /* DRPS */ - if (rn != 0x1f) { - unallocated_encoding(s); + if (op3 != 0 || op4 != 0 || rn != 0x1f) { + goto do_unallocated; } else { unsupported_encoding(s, insn); } return; + default: + do_unallocated: unallocated_encoding(s); return; } From patchwork Fri Dec 14 05:23:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153745 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1673129ljp; Thu, 13 Dec 2018 21:28:07 -0800 (PST) X-Google-Smtp-Source: AFSGD/XgFrSjvOR9BKOC5rLw6StZWS5FCq5EvtZDrPLEqApYoErobQJfFZMWR4vb2hdvdGrhQZVu X-Received: by 2002:a0c:fa8f:: with SMTP id o15mr1497692qvn.135.1544765287637; Thu, 13 Dec 2018 21:28:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765287; cv=none; d=google.com; s=arc-20160816; b=mOfouVMKU4A8DbzJV8P5TN3hvAZ4GNh9fBWFrRnaXhF+Edvnmt8t4x6UWqnuBBe+hU aBixFBBtlabvavlwOs3pbyJjAvMPo7dKwsXzgRFEuMRdU+fMtwcNgESmDHbNs+25eqlU IajNru0bwro/WkS8VUUSCD5+o7iVKtVS0aeYzXPni3veMlQcS3R6n3lQA5oPqQewlN9R FIc9IQgndgdE0NhhVduCXKVzxWNZbzIlt/TstwJRBNb6tRfYfwzVSFrZzqP8qTtHdxUK +SuaQzc+HhyFaWIsOSh/2w/Drg7YQLLDNPG4Txsb+VqLbHGKxepnIVSJ8rkCrlB/zYys st4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ibadInM9T3RbGOG0kOgkioR76NG5vSTRyjFmOZT3e1M=; b=JlemQTS9Ou7kPjD2Kg9l2Uyt58jUDtphwgshx5Zx40VEL/B1wO/3jT0Wt2JupJgr7X M+lm5Wth2Pqm9/z2+p9reqcjPcW479ALH2bF947ICA6OEa0bAGFxZG3pBh3Sig/23UUr tFOaQvojAZvhfRbUo0xHDYB6JWTQTOxJcrh0Mb14bVu9+TKRviIHXhuET92uaEbdiWeV F5cUOf63+GgnLQJM2wjJ5THkxUMNlPpJU7PKO7D2gtk9VIp/AwAkPVhrbobxFKMx5H39 NvPedVnkQmZLVZ4w5zMhsi+fiG8oimvvCiO7+SLRBdHnUJQGR1wB1RH9+AgM3ypR0o+q QemQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=G2FyXZk5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v2 12/27] target/arm: Decode PAuth within disas_uncond_b_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 30086a5d7f..e62d248894 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1982,6 +1982,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; TCGv_i64 dst; + TCGv_i64 modifier; opc = extract32(insn, 21, 4); op2 = extract32(insn, 16, 5); @@ -1999,12 +2000,44 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) case 2: /* RET */ switch (op3) { case 0: + /* BR, BLR, RET */ if (op4 != 0) { goto do_unallocated; } dst = cpu_reg(s, rn); break; + case 2: + case 3: + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (opc == 2) { + /* RETAA, RETAB */ + if (rn != 0x1f || op4 != 0x1f) { + goto do_unallocated; + } + rn = 30; + modifier = cpu_X[31]; + } else { + /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ + if (op4 != 0x1f) { + goto do_unallocated; + } + modifier = new_tmp_a64_zero(s); + } + if (s->pauth_active) { + dst = new_tmp_a64(s); + if (op3 == 2) { + gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); + } else { + gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); + } + } else { + dst = cpu_reg(s, rn); + } + break; + default: goto do_unallocated; } @@ -2016,12 +2049,38 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) } break; + case 8: /* BRAA */ + case 9: /* BLRAA */ + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (op3 != 2 || op3 != 3) { + goto do_unallocated; + } + if (s->pauth_active) { + dst = new_tmp_a64(s); + modifier = cpu_reg_sp(s, op4); + if (op3 == 2) { + gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); + } else { + gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); + } + } else { + dst = cpu_reg(s, rn); + } + gen_a64_set_pc(s, dst); + /* BLRAA also needs to load return address */ + if (opc == 9) { + tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); + } + break; + case 4: /* ERET */ if (s->current_el == 0) { goto do_unallocated; } switch (op3) { - case 0: + case 0: /* ERET */ if (op4 != 0) { goto do_unallocated; } @@ -2030,6 +2089,27 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) offsetof(CPUARMState, elr_el[s->current_el])); break; + case 2: /* ERETAA */ + case 3: /* ERETAB */ + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (rn != 0x1f || op4 != 0x1f) { + goto do_unallocated; + } + dst = tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + if (s->pauth_active) { + modifier = cpu_X[31]; + if (op3 == 2) { + gen_helper_autia(dst, cpu_env, dst, modifier); + } else { + gen_helper_autib(dst, cpu_env, dst, modifier); + } + } + break; + default: goto do_unallocated; } From patchwork Fri Dec 14 05:23:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153742 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1671461ljp; Thu, 13 Dec 2018 21:25:03 -0800 (PST) X-Google-Smtp-Source: AFSGD/XqfxXpZj/P/3FW/6513MgMrcpykb0SLBZPvemMg1upJ7JSuzd8xIuO8KzV1uYed7VTruBC X-Received: by 2002:aed:2803:: with SMTP id r3mr1455234qtd.316.1544765103210; Thu, 13 Dec 2018 21:25:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765103; cv=none; d=google.com; s=arc-20160816; b=WvOpIt5AUrtnEDN8m7vvGSqYLajDnecuHeAnXZfx/m+b6kWmDtlmrHD8J8U4Ytdz3S XFBKONc79azSMDJg/CIlPDsgDuOAj19BTX3Q+KwXvU7vh03LTwu8yTEXoGnha4Kum3Dt EWS5Hd2vwhOCZpt7x3dqgoWvh0A/qrJIo1tKYn1MlLzjZduh32xOzUmHTJENp/kH0YFf N5i1DvrzX9Ft+xz7IRWUcHfpY4OG8NbowScKdHI2a9kBr8f02jTqER51wR6YM4nXV4Sr HNFGPma9a/NXI+BPXdryEECB0IgsNFQ9CTJQ9X/z3U9xUJlmbNQ+rKuKs2pNEJ8hVo2F RqEQ== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id x24si2230969qkh.97.2018.12.13.21.25.03 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:25:03 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LRBEBCsq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59433 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfyA-0004eS-MG for patch@linaro.org; Fri, 14 Dec 2018 00:25:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55757) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxi-0004TS-G9 for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxd-0005PX-Cs for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:32 -0500 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]:33295) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxd-0005Ot-7c for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:29 -0500 Received: by mail-oi1-x231.google.com with SMTP id c206so3659730oib.0 for ; Thu, 13 Dec 2018 21:24:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6OI+UPAp5FYiypogPPtR+ujzpAY2Etryh32yM0PnSA8=; b=LRBEBCsqDcD2qLOy5opoKDajZWn06n+J86t5+kf8en2QR/Rk3vhRXIPcyMITi5TXCT 4iQP2598Jqdh09sPPp6Y1esir7V/v/iAvxfBMc8TbWaRK+EKwP5xxjBBe/913QRjginq x5ns8v5DwptBibTX4FV4piagkRGJNeVP2y53s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6OI+UPAp5FYiypogPPtR+ujzpAY2Etryh32yM0PnSA8=; b=pC0SJ2eYYgfPxbf/WU1tVarWcqoIJbu77zQng21u3IbjulHPpATnkHMUqy840IG72h dd4JnKw/IVPHebvtOn+qU+LLf266dK0paWe21ANggQqV8/tKEvr8mVk4qoIAHj6dsMFl 6GBzrveE8kkx5HTtd0UN9BmP/aXIWJ5WTMMz1+iYGPSV3kbnuXgvbcF+ge78kgIgSfSL h4qbOAgDigiJLwKk59lfXavxN/r5JnVcI8rboB98Umq8LhcCdg7gHjA4T3pCXmlIe+qf G4Max1WQWZW6uGJeBXgAPrlWB4sf8sa/yqKhci/f62qUPe6b2nDF2Oeg2SvXQOOfO2+Q qRNQ== X-Gm-Message-State: AA+aEWZpZVerSk907N437Zoova+X497C/YZ8yWV3gl72E8QPzcLrTyHi 8XoxLsjToZzfFx0ZCeZ5k2VXHoQfT/xLcg== X-Received: by 2002:aca:2803:: with SMTP id 3mr1011816oix.85.1544765068221; Thu, 13 Dec 2018 21:24:28 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:23:56 -0600 Message-Id: <20181214052410.11863-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::231 Subject: [Qemu-devel] [PATCH v2 13/27] target/arm: Decode Load/store register (pac) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not that there are any stores involved, but why argue with ARM's naming convention. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 62 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e62d248894..c57c89d98a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3146,6 +3146,65 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, s->be_data | size | MO_ALIGN); } +/* PAC memory operations + * + * 31 30 27 26 24 22 21 12 11 10 5 0 + * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ + * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | + * +------+-------+---+-----+-----+------------+---+---+----+-----+ + * + * Rt: the result register + * Rn: base address or SP + * Rs: the source register for the operation + * V: vector flag (always 0 as of v8.3) + * M: clear for key DA, set for key DB + * W: pre-indexing flag + * S: sign for imm9. + */ +static void disas_ldst_pac(DisasContext *s, uint32_t insn, + int size, int rt, bool is_vector) +{ + int rn = extract32(insn, 5, 5); + bool is_wback = extract32(insn, 11, 1); + bool use_key_a = !extract32(insn, 23, 1); + int offset, memidx; + TCGv_i64 tcg_addr, tcg_rt; + + if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { + unallocated_encoding(s); + return; + } + + if (rn == 31) { + gen_check_sp_alignment(s); + } + tcg_addr = read_cpu_reg_sp(s, rn, 1); + + if (s->pauth_active) { + if (use_key_a) { + gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } else { + gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } + } + + /* Form the 10-bit signed, scaled offset. */ + offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); + offset = sextract32(offset << size, 10 + size, 0); + tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + + tcg_rt = cpu_reg(s, rt); + memidx = get_mem_index(s); + do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, + /* is_signed */ false, /* extend */ false, memidx, + /* iss_valid */ true, /* iss_srt */ rt, + /* iss_sf */ true, /* iss_ar */ false); + + if (is_wback) { + tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); + } +} + /* Load/store register (all forms) */ static void disas_ldst_reg(DisasContext *s, uint32_t insn) { @@ -3171,6 +3230,9 @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn) case 2: disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); return; + default: + disas_ldst_pac(s, insn, size, rt, is_vector); + return; } break; case 1: From patchwork Fri Dec 14 05:23:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153749 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1676430ljp; Thu, 13 Dec 2018 21:33:39 -0800 (PST) X-Google-Smtp-Source: AFSGD/WaIQwZEJbmlcxyqRVjrk97ypx4q+dcyJeUaMo4IxRQTx7vJMVc7G0KTOXmsCsS+OfjCbm6 X-Received: by 2002:a37:c3c3:: with SMTP id r64mr1416478qkl.70.1544765618941; Thu, 13 Dec 2018 21:33:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765618; cv=none; d=google.com; s=arc-20160816; b=LZUBJ3CLOGiWf/EGOkVaKLPl1VS4lmfWCL6ST2AG+/X5aUACxlAPWKTWZge20YmCYt b35A1IwCy7WzqpKM2m1zByXoFc+CcyAX9GAF/IK/OOsCJrexPZLSelPA0Pj4yEBlDVDJ fLX0DHjCvsSwEqaMjsjsafs4v7s3r/gvwZ/KbZ+3L1lK1FRowuxXOFTF+AK56K8waSWr H8SJtvTOaV8CHZSDCRD9kU0Zu7mnAOtR6nUghAwecBMjM/lqAVObb9Mj+T2M395pGvRE ls/gYScTARniFS1gicDuom9ng2WCIp+kKSfDzBWE/e3IAU9DV4GZjwnHLKH4ErdbkBsr Aatg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AUMg+u27uMOuJ6XW+OsUe7C34ZHfjbNbRhgYaArpPkM=; b=BnvvGpICuxZCljj9suki5VZq7Hm9PI6pjI3UszmuysztqtZtbu7Bt3L+Vx1rCiJsRO hYS5FJYEPUegabj55vZNjO7Cf3hgYjwI+Y0G68zwihrwYVHE+dTg96VKQMvGXW8EkHbD NBfVoqKYLLPF3ccurqXFH3FWF0ttWm06NSC22nLgDii7rmEEwSiDl4S5Nq1nBoKb9FM4 YifyJkCFxmZ9nPg93eTL8oGIn100owu1wRgrCOhhKtEUFmis/fL04vNgh0+1TcjwWact MhrjWPuHmTMGWIKXaW5ifM9BMlzTWy7hWcUu4kZ3WLasDE11KNayMr02dS7DPoJ2j25k 0cTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BrZ00UN0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v2 14/27] target/arm: Move cpu_mmu_index out of line X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is, or will shortly become, too big to inline. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 48 +++++---------------------------------------- target/arm/helper.c | 44 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 43 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 898243c93e..6435997111 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2739,54 +2739,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) } /* Return the MMU index for a v7M CPU in the specified security and - * privilege state + * privilege state. */ -static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, - bool priv) -{ - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; - - if (priv) { - mmu_idx |= ARM_MMU_IDX_M_PRIV; - } - - if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; - } - - if (secstate) { - mmu_idx |= ARM_MMU_IDX_M_S; - } - - return mmu_idx; -} +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv); /* Return the MMU index for a v7M CPU in the specified security state */ -static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, - bool secstate) -{ - bool priv = arm_current_el(env) != 0; - - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); -} +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); /* Determine the current mmu_idx to use for normal loads/stores */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - int el = arm_current_el(env); - - if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); - - return arm_to_core_mmu_idx(mmu_idx); - } - - if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); - } - return el; -} +int cpu_mmu_index(CPUARMState *env, bool ifetch); /* Indexes used when registering address spaces with cpu_address_space_init */ typedef enum ARMASIdx { diff --git a/target/arm/helper.c b/target/arm/helper.c index bd0cff5c27..56960411e3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12949,6 +12949,50 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv) +{ + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; + + if (priv) { + mmu_idx |= ARM_MMU_IDX_M_PRIV; + } + + if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; + } + + if (secstate) { + mmu_idx |= ARM_MMU_IDX_M_S; + } + + return mmu_idx; +} + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + bool priv = arm_current_el(env) != 0; + + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + int el = arm_current_el(env); + + if (arm_feature(env, ARM_FEATURE_M)) { + ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); + + return arm_to_core_mmu_idx(mmu_idx); + } + + if (el < 2 && arm_is_secure_below_el3(env)) { + return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + } + return el; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { From patchwork Fri Dec 14 05:23:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153757 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1679785ljp; Thu, 13 Dec 2018 21:39:24 -0800 (PST) X-Google-Smtp-Source: AFSGD/XKATOzWzCwKv52slv115wu3D3WG0ynkmgeXICHEcsDsGq0IeWGnrSzHoQNDLheTP+xadAq X-Received: by 2002:a37:ba06:: with SMTP id k6mr1394131qkf.115.1544765964525; Thu, 13 Dec 2018 21:39:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765964; cv=none; d=google.com; s=arc-20160816; b=UYYTCsLLg78DwXGYtQEd+CT5tVvh3fyWDnzpSeM6aJ0d4PXFbojammOhvia6/Pb+w2 rcoTsszTakdZX/vl34Dqwg+m/RaOldVUGU+q/o5U+yNpsNs4U/5zgItTvBUWpGOywl1n ZBtt67wugt0Df1EADx+NYIjCKv4K+7qXI2+bdOIXtBeid3fJPCJsjspvbp4SZ7kulb3Z ztbhzdGK+Dxt3Ty4THiAtxF/vDhDNIDq3mAJr2Q+c+pZvxy9nDDKxLKo83vPniILHvoK XUkg2TjynUs5sDhp8ghVzbJR8J6cO4SjznZ2lI87Aubw43k7c2Q6deYfSJmKykgsgMYH lEqA== ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v2 15/27] target/arm: Introduce arm_mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The pattern ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); is computing the full ARMMMUIdx, stripping off the ARM bits, and then putting them back. Avoid the extra two steps with the appropriate helper function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Move arm_mmu_idx declaration to internals.h. --- target/arm/cpu.h | 9 ++++++++- target/arm/internals.h | 8 ++++++++ target/arm/helper.c | 27 ++++++++++++++++----------- 3 files changed, 32 insertions(+), 12 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6435997111..3cc7a069ce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2747,7 +2747,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); -/* Determine the current mmu_idx to use for normal loads/stores */ +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ int cpu_mmu_index(CPUARMState *env, bool ifetch); /* Indexes used when registering address spaces with cpu_address_space_init */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 6bc0daf560..4a52fe58b6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -912,4 +912,12 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); +/** + * arm_mmu_idx: + * @env: The cpu environment + * + * Return the full ARMMMUIdx for the current translation regime. + */ +ARMMMUIdx arm_mmu_idx(CPUARMState *env); + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 56960411e3..50c1db16dd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7117,7 +7117,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, limit = env->v7m.msplim[M_REG_S]; } } else { - mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + mmu_idx = arm_mmu_idx(env); frame_sp_p = &env->regs[13]; limit = v7m_sp_limit(env); } @@ -7298,7 +7298,7 @@ static bool v7m_push_stack(ARMCPU *cpu) CPUARMState *env = &cpu->env; uint32_t xpsr = xpsr_read(env); uint32_t frameptr = env->regs[13]; - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); /* Align stack pointer if the guest wants that */ if ((frameptr & 4) && @@ -11073,7 +11073,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, int prot; bool ret; ARMMMUFaultInfo fi = {}; - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); *attrs = (MemTxAttrs) {}; @@ -12977,26 +12977,31 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } -int cpu_mmu_index(CPUARMState *env, bool ifetch) +ARMMMUIdx arm_mmu_idx(CPUARMState *env) { - int el = arm_current_el(env); + int el; if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); - - return arm_to_core_mmu_idx(mmu_idx); + return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } + el = arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + return ARMMMUIdx_S1SE0 + el; + } else { + return ARMMMUIdx_S12NSE0 + el; } - return el; +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return arm_to_core_mmu_idx(arm_mmu_idx(env)); } void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); uint32_t flags; From patchwork Fri Dec 14 05:23:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153755 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1678202ljp; Thu, 13 Dec 2018 21:36:35 -0800 (PST) X-Google-Smtp-Source: AFSGD/VkwPdqTmn7PmuEx8ME5E1b7IBxg/DE+4bgyNbDvfQq8DoGryWzSjfJzJsUyCZ6cb0FfcJi X-Received: by 2002:ac8:64a:: with SMTP id e10mr1468376qth.314.1544765795219; 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X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v2 16/27] target/arm: Introduce arm_stage1_mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While we could expose stage_1_mmu_idx, the combination is probably going to be more useful. Signed-off-by: Richard Henderson --- target/arm/internals.h | 15 +++++++++++++++ target/arm/helper.c | 7 +++++++ 2 files changed, 22 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 4a52fe58b6..1d0d0392c9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -920,4 +920,19 @@ void arm_cpu_update_vfiq(ARMCPU *cpu); */ ARMMMUIdx arm_mmu_idx(CPUARMState *env); +/** + * arm_stage1_mmu_idx: + * @env: The cpu environment + * + * Return the ARMMMUIdx for the stage1 traversal for the current regime. + */ +#ifdef CONFIG_USER_ONLY +static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) +{ + return ARMMMUIdx_S1NSE0; +} +#else +ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); +#endif + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 50c1db16dd..b1c0ff923f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12998,6 +12998,13 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch) return arm_to_core_mmu_idx(arm_mmu_idx(env)); } +#ifndef CONFIG_USER_ONLY +ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) +{ + return stage_1_mmu_idx(arm_mmu_idx(env)); +} +#endif + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { From patchwork Fri Dec 14 05:24:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153763 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1682919ljp; Thu, 13 Dec 2018 21:44:40 -0800 (PST) X-Google-Smtp-Source: AFSGD/X9IemtJKVvZIHkJ3IJp6T0pr66E5k9WACQUphF5HvNUKc7xIMDGjcLKjGHudjh/aAVj3Uh X-Received: by 2002:ac8:e0b:: with SMTP id a11mr1588525qti.140.1544766280441; Thu, 13 Dec 2018 21:44:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544766280; cv=none; d=google.com; s=arc-20160816; b=Cyr3LETsKXpiW80iED27c3OhruD6L031tpf8hVZOb+Bt5BZ5jnYleIPmk42Q4um2Hx SFkEDKkwXy38NEcXREldMsHyWKb2xq+uSdV9NnyCkCSkPlaVE9kIA0LWo7PHJGbQIMji HWTnhC0ad8buUa/8OrrEtt3sCNPiDVXo+g092ECvRsKrx+c66McXvTITOLK434J0aY3i v7tq+7/2UTTHXxcb8oND55jvhWs9TkovYpzpH/VKoDU5nJ3J8A/cfPewUic7hNweL7g1 uNKV44tK9h3g6NNg24inqXoz3vUqAjCaQSZaeO9F8DaY2A/W1Ak5MyuBeHPPmy+eo6wt pC0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=iAOlwRwzjzgBH9S2Zyt3PqiDY4VgK54UrZa3GrRPYok=; b=GkFYrHq3EYA7+n7IRNK9LYbpyI9TzL4uCDXlhlBwcoQ9pGayj9hs7C0XyFdLQws4hQ wDPEjHQcun0p9RlEX3PZG/z7WqTKUV/vh7xoSPvux0tj2Djaj1ZNxZnVV027EoEbRFCM QdzMS01F6E78+Std5Dkhp1hqfwHcFjaD6BgXN3F4/V81L3FByLvH0zoRqgFeje0IwL8x ezb3brmhbEm2rGcVF+Gsa6kHUMYmS0G8fvHi/SxmCrul2fyt2bsj5yxLqS4bSVbFnRWA XLX1Bsz+BHjq9AjkpLTZ60SULONUskrCkfLmi70JlZzW+XjP2hVnqnBvnUvZBrv4/NmS 4EYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=d3jOGDpR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v2 17/27] target/arm: Create ARMVAParameters and helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out functions to extract the virtual address parameters. Let the functions choose T0 or T1 address space half, if present. Extract (most of) the control bits that vary between EL or Tx. Signed-off-by: Richard Henderson ---- v2: Incorporate feedback wrt VTCR, HTCR, and more. --- target/arm/internals.h | 16 +++ target/arm/helper.c | 286 +++++++++++++++++++++++------------------ 2 files changed, 174 insertions(+), 128 deletions(-) -- 2.17.2 diff --git a/target/arm/internals.h b/target/arm/internals.h index 1d0d0392c9..9ef9d01ee2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -935,4 +935,20 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); #endif +/* + * Parameters of a given virtual address, as extracted from a the + * translation control register (TCR) for a given regime. + */ +typedef struct ARMVAParameters { + unsigned tsz : 8; + unsigned select : 1; + bool tbi : 1; + bool epd : 1; + bool hpd : 1; + bool ha : 1; + bool hd : 1; + bool using16k : 1; + bool using64k : 1; +} ARMVAParameters; + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index b1c0ff923f..3422fa5943 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9744,6 +9744,133 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } +static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint32_t el = regime_el(env, mmu_idx); + bool tbi, tbid, epd, hpd, ha, hd, using16k, using64k; + int select, tsz; + + /* Bit 55 is always between the two regions, and is canonical for + * determining if address tagging is enabled. + */ + select = extract64(va, 55, 1); + + if (el > 1) { + tsz = extract32(tcr, 0, 6); + using64k = extract32(tcr, 14, 1); + using16k = extract32(tcr, 15, 1); + if (mmu_idx == ARMMMUIdx_S2NS) { + /* VTCR_EL2 */ + tbi = tbid = hpd = false; + } else { + tbi = extract32(tcr, 20, 1); + hpd = extract32(tcr, 24, 1); + tbid = extract32(tcr, 29, 1); + } + ha = extract32(tcr, 21, 1); + hd = extract32(tcr, 22, 1); + epd = false; + } else if (!select) { + tsz = extract32(tcr, 0, 6); + epd = extract32(tcr, 7, 1); + using64k = extract32(tcr, 14, 1); + using16k = extract32(tcr, 15, 1); + tbi = extract64(tcr, 37, 1); + ha = extract64(tcr, 39, 1); + hd = extract64(tcr, 40, 1); + hpd = extract64(tcr, 41, 1); + tbid = extract64(tcr, 51, 1); + } else { + int tg = extract32(tcr, 30, 2); + using16k = tg == 1; + using64k = tg == 3; + tsz = extract32(tcr, 16, 6); + epd = extract32(tcr, 23, 1); + tbi = extract64(tcr, 38, 1); + ha = extract64(tcr, 39, 1); + hd = extract64(tcr, 40, 1); + hpd = extract64(tcr, 42, 1); + tbid = extract64(tcr, 52, 1); + } + tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ + tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ + + return (ARMVAParameters) { + .tsz = tsz, + .select = select, + .tbi = tbi & (data | !tbid), + .epd = epd, + .hpd = hpd, + .ha = ha, + .hd = hd, + .using16k = using16k, + .using64k = using64k, + }; +} + +static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, + ARMMMUIdx mmu_idx) +{ + uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint32_t el = regime_el(env, mmu_idx); + int select, tsz; + bool epd, hpd; + + if (mmu_idx == ARMMMUIdx_S2NS) { + /* VTCR */ + bool sext = extract32(tcr, 4, 1); + bool sign = extract32(tcr, 3, 1); + + /* If the sign-extend bit is not the same as t0sz[3], the result + * is unpredictable. Flag this as a guest error. + */ + if (sign != sext) { + qemu_log_mask(LOG_GUEST_ERROR, + "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); + } + tsz = sextract32(tcr, 0, 4) + 8; + select = 0; + hpd = false; + epd = false; + } else if (el == 2) { + /* HTCR */ + tsz = extract32(tcr, 0, 3); + select = 0; + hpd = extract64(tcr, 24, 1); + epd = false; + } else { + int t0sz = extract32(tcr, 0, 3); + int t1sz = extract32(tcr, 16, 3); + + if (t1sz == 0) { + select = va > (0xffffffffu >> t0sz); + } else { + /* Note that we will detect errors later. */ + select = va >= ~(0xffffffffu >> t1sz); + } + if (!select) { + tsz = t0sz; + epd = extract32(tcr, 7, 1); + hpd = extract64(tcr, 41, 1); + } else { + tsz = t1sz; + epd = extract32(tcr, 23, 1); + hpd = extract64(tcr, 42, 1); + } + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &= extract32(tcr, 6, 1); + } + + return (ARMVAParameters) { + .tsz = tsz, + .select = select, + .epd = epd, + .hpd = hpd, + }; +} + static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, @@ -9755,26 +9882,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, /* Read an LPAE long-descriptor translation table. */ ARMFaultType fault_type = ARMFault_Translation; uint32_t level; - uint32_t epd = 0; - int32_t t0sz, t1sz; - uint32_t tg; + ARMVAParameters param; uint64_t ttbr; - int ttbr_select; hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; - target_ulong page_size; + target_ulong page_size, top_bits; uint32_t attrs; - int32_t stride = 9; - int32_t addrsize; - int inputsize; - int32_t tbi = 0; + int32_t stride; + int addrsize, inputsize; TCR *tcr = regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); - bool ttbr1_valid = true; + bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); - bool hpd = false; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -9783,91 +9904,43 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, * support for those page table walks. */ if (aarch64) { + param = aa64_va_parameters(env, address, mmu_idx, + access_type != MMU_INST_FETCH); level = 0; - addrsize = 64; - if (el > 1) { - if (mmu_idx != ARMMMUIdx_S2NS) { - tbi = extract64(tcr->raw_tcr, 20, 1); - } - } else { - if (extract64(address, 55, 1)) { - tbi = extract64(tcr->raw_tcr, 38, 1); - } else { - tbi = extract64(tcr->raw_tcr, 37, 1); - } - } - tbi *= 8; - /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it * invalid. */ - if (el > 1) { - ttbr1_valid = false; - } + ttbr1_valid = (el < 2); + addrsize = 64 - 8 * param.tbi; + inputsize = 64 - param.tsz; } else { + param = aa32_va_parameters(env, address, mmu_idx); level = 1; - addrsize = 32; /* There is no TTBR1 for EL2 */ - if (el == 2) { - ttbr1_valid = false; - } + ttbr1_valid = (el != 2); + addrsize = (mmu_idx == ARMMMUIdx_S2NS ? 40 : 32); + inputsize = addrsize - param.tsz; } - /* Determine whether this address is in the region controlled by - * TTBR0 or TTBR1 (or if it is in neither region and should fault). - * This is a Non-secure PL0/1 stage 1 translation, so controlled by - * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: + /* We determined the region when collecting the parameters, but we + * have not yet validated that the address is valid for the region. + * Extract the top bits and verify that they all match select. */ - if (aarch64) { - /* AArch64 translation. */ - t0sz = extract32(tcr->raw_tcr, 0, 6); - t0sz = MIN(t0sz, 39); - t0sz = MAX(t0sz, 16); - } else if (mmu_idx != ARMMMUIdx_S2NS) { - /* AArch32 stage 1 translation. */ - t0sz = extract32(tcr->raw_tcr, 0, 3); - } else { - /* AArch32 stage 2 translation. */ - bool sext = extract32(tcr->raw_tcr, 4, 1); - bool sign = extract32(tcr->raw_tcr, 3, 1); - /* Address size is 40-bit for a stage 2 translation, - * and t0sz can be negative (from -8 to 7), - * so we need to adjust it to use the TTBR selecting logic below. - */ - addrsize = 40; - t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8; - - /* If the sign-extend bit is not the same as t0sz[3], the result - * is unpredictable. Flag this as a guest error. */ - if (sign != sext) { - qemu_log_mask(LOG_GUEST_ERROR, - "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); - } - } - t1sz = extract32(tcr->raw_tcr, 16, 6); - if (aarch64) { - t1sz = MIN(t1sz, 39); - t1sz = MAX(t1sz, 16); - } - if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { - /* there is a ttbr0 region and we are in it (high bits all zero) */ - ttbr_select = 0; - } else if (ttbr1_valid && t1sz && - !extract64(~address, addrsize - t1sz, t1sz - tbi)) { - /* there is a ttbr1 region and we are in it (high bits all one) */ - ttbr_select = 1; - } else if (!t0sz) { - /* ttbr0 region is "everything not in the ttbr1 region" */ - ttbr_select = 0; - } else if (!t1sz && ttbr1_valid) { - /* ttbr1 region is "everything not in the ttbr0 region" */ - ttbr_select = 1; - } else { - /* in the gap between the two regions, this is a Translation fault */ + top_bits = sextract64(address, inputsize, addrsize - inputsize); + if (-top_bits != param.select || (param.select && !ttbr1_valid)) { + /* In the gap between the two regions, this is a Translation fault */ fault_type = ARMFault_Translation; goto do_fault; } + if (param.using64k) { + stride = 13; + } else if (param.using16k) { + stride = 11; + } else { + stride = 9; + } + /* Note that QEMU ignores shareability and cacheability attributes, * so we don't need to do anything with the SH, ORGN, IRGN fields * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the @@ -9875,56 +9948,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, * implement any ASID-like capability so we can ignore it (instead * we will always flush the TLB any time the ASID is changed). */ - if (ttbr_select == 0) { - ttbr = regime_ttbr(env, mmu_idx, 0); - if (el < 2) { - epd = extract32(tcr->raw_tcr, 7, 1); - } - inputsize = addrsize - t0sz; - - tg = extract32(tcr->raw_tcr, 14, 2); - if (tg == 1) { /* 64KB pages */ - stride = 13; - } - if (tg == 2) { /* 16KB pages */ - stride = 11; - } - if (aarch64 && el > 1) { - hpd = extract64(tcr->raw_tcr, 24, 1); - } else { - hpd = extract64(tcr->raw_tcr, 41, 1); - } - if (!aarch64) { - /* For aarch32, hpd0 is not enabled without t2e as well. */ - hpd &= extract64(tcr->raw_tcr, 6, 1); - } - } else { - /* We should only be here if TTBR1 is valid */ - assert(ttbr1_valid); - - ttbr = regime_ttbr(env, mmu_idx, 1); - epd = extract32(tcr->raw_tcr, 23, 1); - inputsize = addrsize - t1sz; - - tg = extract32(tcr->raw_tcr, 30, 2); - if (tg == 3) { /* 64KB pages */ - stride = 13; - } - if (tg == 1) { /* 16KB pages */ - stride = 11; - } - hpd = extract64(tcr->raw_tcr, 42, 1); - if (!aarch64) { - /* For aarch32, hpd1 is not enabled without t2e as well. */ - hpd &= extract64(tcr->raw_tcr, 6, 1); - } - } + ttbr = regime_ttbr(env, mmu_idx, param.select); /* Here we should have set up all the parameters for the translation: * inputsize, ttbr, epd, stride, tbi */ - if (epd) { + if (param.epd) { /* Translation table walk disabled => Translation fault on TLB miss * Note: This is always 0 on 64-bit EL2 and EL3. */ @@ -10037,7 +10067,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } /* Merge in attributes from table descriptors */ attrs |= nstable << 3; /* NS */ - if (hpd) { + if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; } From patchwork Fri Dec 14 05:24:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153765 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1683698ljp; Thu, 13 Dec 2018 21:46:04 -0800 (PST) X-Google-Smtp-Source: AFSGD/VdR+FTPcAbNFcLrF6/zHkhHeLoQiGjyPfg0EI237x1TJquXrwg7+rgycfD2QaRXVFpPUGO X-Received: by 2002:ae9:dec5:: with SMTP id s188mr765877qkf.127.1544766364741; Thu, 13 Dec 2018 21:46:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544766364; cv=none; d=google.com; s=arc-20160816; b=cLFjj9kwTb2912X5fhQFGiUvq8kdgY23J9B8JxtGHlydABEGSVVthvRPplbNaeT9sW ax1X2OSfa5GQYf0EpTUQQq+eNw6tlo4/uP/BgKG0ctqB4dK/jAvsCtUpp1GYFNwkNlJ5 443YqLWAabJD0MgyYHXgVUNVG3BxSJBraI8SrdWAxo24e1TV5PFEq/8Qvh8Qre5XnBNi ruDhQ2RXInKeRyZUpB+nf45kKAqxX7KkLCI3wWPEZmkqD/+azk8kP4H5wJ8KOgScmezM pbydjAtUH4MywHLgkrzCGJRt1izfTQiBSu1tJeGcchMdDaPeMG4ksv74135HyvNrQBsE r98A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=/I3auZHuWfajL94gMEfxagNYYa9G7egKOKTHpoNXvLA=; b=r9Wd8thp+JF8CbwZzhv2rxsY2HDXpYvsyWhqlDx/7dbobZxHvTJKZ2skz//0MXT6HX d32xIaqxcq+3YseTXxGjgWvl0bneh9CZXibWWwvoSR1FYzsI3P9FnQc9qagXfCdqrjIA py3Wkbmd3xNHENRmQSGq+0sSkxFx6xE+dbm21gwHbdS5Za+LthoJDJTxYIxGLednLDNY X0tH4tfDpx0rS++TAmjxj8CdCzuGyZfU6aPnOBGl/IYfz7ueYJYJddsbNvdnfxVfZf2U H0r/p8d5dCvUYXdzxQQKZWJK1TI8mWVRJpIURbbXQmBZPCnMSjXl1JcLN4CO+eWrhBuo S2ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OfbMA9W1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id b48si2322248qtk.45.2018.12.13.21.46.04 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:46:04 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OfbMA9W1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59541 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXgIW-0006HF-9x for patch@linaro.org; Fri, 14 Dec 2018 00:46:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxu-0004ma-5v for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxo-0005Tx-5X for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:46 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:37728) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxk-0005Rp-Hi for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:38 -0500 Received: by mail-oi1-x243.google.com with SMTP id y23so3631596oia.4 for ; Thu, 13 Dec 2018 21:24:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/I3auZHuWfajL94gMEfxagNYYa9G7egKOKTHpoNXvLA=; b=OfbMA9W1gZY/aXkoO+cxCt+cox6mMjTkx1uya9f81Dk6XmLXopZ9BM1pYghkGtSbxr tljP8ghxTL7dhOsc8n5FX7ikDkhxXlCiDeDA+hLudsoR7fIyzOuOVMSb46aIHYyP7Nu7 W3/aUXvO2qJpeg/Lk0dnA2YZ2b2T68fJDwfgg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/I3auZHuWfajL94gMEfxagNYYa9G7egKOKTHpoNXvLA=; b=AlU54BByZtwiYiKZvKPeZuRDt2jdEiS6xyKegn9sU6n9r3Pgo4glfhE5eUR/j7Lxjd yODG3y6Cip3mgim9udpNbPOaHzCzbnm1jXgZ/LZxsSvyCVwOFmrz+bzMErdw9xuTYMGv 9uj3gMg93Cf7MpyWUoUOMdxUr+XZoud3YEoNsGWmaeD8vfaY3QXY32RSVqnKNB6eDcYH A6shn6JGrchvbTQXesRxj3J8D5kKv+ourFcSDFC1B/powOAxFRkAXn7yooBFQhpTpBFA lhQRgOY8uccEUfdWMY4G8/5g9vJ8KRr+CIh4KcZdHb6Fs/xno9wvqmtXNvWGrD7V1nTa WYew== X-Gm-Message-State: AA+aEWaZ35ivf6e6Ef3YMukHgYAYBhIOYb+12oJtRPVl7sRNVx5GglMx 9rOo0r6q/GD90qV3TaMwYOLWOyqgO+rHuQ== X-Received: by 2002:aca:43c6:: with SMTP id q189mr1015778oia.340.1544765073735; Thu, 13 Dec 2018 21:24:33 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:24:01 -0600 Message-Id: <20181214052410.11863-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH v2 18/27] target/arm: Reuse aa64_va_parameters for setting tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 35 -------------------------- target/arm/helper.c | 61 ++++++++++++--------------------------------- 2 files changed, 16 insertions(+), 80 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3cc7a069ce..7c7dbc216c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3079,41 +3079,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) } #endif -#ifndef CONFIG_USER_ONLY -/** - * arm_regime_tbi0: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI0 value from the appropriate TCR for the current EL - * - * Returns: the TBI0 value. - */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); - -/** - * arm_regime_tbi1: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI1 value from the appropriate TCR for the current EL - * - * Returns: the TBI1 value. - */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); -#else -/* We can't handle tagged addresses properly in user-only mode */ -static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} - -static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} -#endif - void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); diff --git a/target/arm/helper.c b/target/arm/helper.c index 3422fa5943..bd1b683766 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8957,48 +8957,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) return mmu_idx; } -/* Returns TBI0 value for current regime el */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - tcr = regime_tcr(env, mmu_idx); - el = regime_el(env, mmu_idx); - - if (el > 1) { - return extract64(tcr->raw_tcr, 20, 1); - } else { - return extract64(tcr->raw_tcr, 37, 1); - } -} - -/* Returns TBI1 value for current regime el */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - tcr = regime_tcr(env, mmu_idx); - el = regime_el(env, mmu_idx); - - if (el > 1) { - return 0; - } else { - return extract64(tcr->raw_tcr, 38, 1); - } -} - /* Return the TTBR associated with this translation regime */ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) @@ -13048,9 +13006,22 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *pc = env->pc; flags = ARM_TBFLAG_AARCH64_STATE_MASK; - /* Get control bits for tagged addresses */ - flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); - flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); + +#ifndef CONFIG_USER_ONLY + /* Get control bits for tagged addresses. Note that the + * translator only uses this for instruction addresses. + */ + { + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0, p1; + + p0 = aa64_va_parameters(env, 0, stage1, false); + p1 = aa64_va_parameters(env, -1, stage1, false); + + flags |= p0.tbi << ARM_TBFLAG_TBI0_SHIFT; + flags |= p1.tbi << ARM_TBFLAG_TBI1_SHIFT; + } +#endif if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el = sve_exception_el(env, current_el); From patchwork Fri Dec 14 05:24:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153767 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1685852ljp; Thu, 13 Dec 2018 21:49:49 -0800 (PST) X-Google-Smtp-Source: AFSGD/WAkF67Y7tA+0N5yYTsC/dokFdL+ScudDQmBOzlLrPTnZeTzIxFi48fUZdTf1M5VKLmQgDY X-Received: by 2002:a37:bb82:: with SMTP id l124mr838093qkf.188.1544766589862; Thu, 13 Dec 2018 21:49:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544766589; cv=none; d=google.com; s=arc-20160816; b=EYxSIjKZJQUoF29BIZlQ6o1oxacaNvXCqUW7ujxMkmzEud3V0uwnNZNRxwcSfglA04 Crj5FlaCL8hYeE+8+QQ3LW3qekLBxGzd7o3xe3bnMGSgTMxBDXV0wNRCv3zEq4+igZzf Vdu7HDYtRg22R4klgxl8o5k9E1cJ4GIV3semRcWs35dhm4qciw0e72Y2gI+2CJYyh9tg gGGSi8wZb8uwPecLa0jqrXADQPg+JNm8jhzVbI9dnWXmxTt6Y4OFzU0kkFaI/UX9deJW Vc6IOkh1BlIBjwdqol2uMSElUnehwQHKvMWdVrnbczPfvRjPyIhXp3+EqWoslPrWr0k5 2BAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4KA8zbUOIv7pZJObxZbOzQNnbAlJZmuvqEm8g4lAP+s=; b=Yb9UPIfUsE22xvySjqnIIqyK2uu73ZeN8SOd7d8lZ0JpYDoUdVniHEsBoZP9+1AlYD dRjyptiBTJoxvXwVxWZmg28yTJghBegdlUQ6q8FUpHI9MQk3+qUBMThk5sgp5X4rI/Mf aW2tkfLzl2hnE6cXfGE2Ug/I3xJtsuU1q+Z7UXdk6t2b37XRy33dQCXyheW4DErmGseD V1xgl3DQk55r54PeSpOqb+vIIAMse19L0I2m49f2TyUcuSlU6uRpqMC9lQf/gOgeVEUu 3BcYC4C8BailWzcZO6+bRarEl7tvEFG6m4vUw7CgN+D2ZRyzAd+4rrGKuJwxQL2ywYt9 dy3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TQ3aLo3c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i31si45003qtb.238.2018.12.13.21.49.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:49:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TQ3aLo3c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59551 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXgM9-000065-EN for patch@linaro.org; Fri, 14 Dec 2018 00:49:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55872) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxu-0004mW-4H for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxo-0005Tr-4c for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:45 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:34182) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxk-0005SN-Ft for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:36 -0500 Received: by mail-ot1-x342.google.com with SMTP id t5so4342304otk.1 for ; Thu, 13 Dec 2018 21:24:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4KA8zbUOIv7pZJObxZbOzQNnbAlJZmuvqEm8g4lAP+s=; b=TQ3aLo3cl7nr5EfDIErWRNS/bSjD5AuDwH9j/yGIHDYY1q7Y+sjAomQjZPE9VPCpsB ZTJvx8fQ7zG+or6ugAQh1wR7rrxkT3d64t2UZYJDv0PlWNt7UAhXAN9hiPCeQwL0aFin YH6IAXf/ll7vMlqWtB1q4/eKKEBE0/JfGMtkY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4KA8zbUOIv7pZJObxZbOzQNnbAlJZmuvqEm8g4lAP+s=; b=BzOMU7QZGVHO4aLPRPMn6OZdpBsCyJqFB35MC16IAI9PgdXWLp81KhAIJAiQuu4g5E 6jN2eKYAs2KQvWDJNBghlPxT6er0XdqRdfleDNanddqzXsasROK40PBglUXHpRfbW8q6 vBk4hsSCcFongQuer9TbeYvNfPhuxwpKB93gAgQPHaadjTV+2wfXZdJn+45HiaBKi1Jd CuyUi3IYHVIsp/PwDJrJS38UEdL+NUhUXBbRFLP/NvgSqg2NadXGlgOWAKHG4E09U2x1 0sUW8xKtd5p8CBoS6Z5h0IqXDTuthNHPHBF91Aww7NkWeofh6k6N6vJV2QHtAYMVwf1e ewtg== X-Gm-Message-State: AA+aEWZCIPg3+fpRCdUL6IzkyoS16qlgPmBWA3s2NIlQ+dDcIt+Mse1y 5srJILNdzqtR/3GR2dftlWu5E3zvYvaRjQ== X-Received: by 2002:a9d:76da:: with SMTP id p26mr1084334otl.366.1544765074876; Thu, 13 Dec 2018 21:24:34 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:24:02 -0600 Message-Id: <20181214052410.11863-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v2 19/27] target/arm: Export aa64_va_parameters to internals.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We need to reuse this from helper-a64.c. Provide a stub definition for CONFIG_USER_ONLY. This matches the stub definitions that we removed for arm_regime_tbi{0,1} before. Signed-off-by: Richard Henderson --- target/arm/internals.h | 17 +++++++++++++++++ target/arm/helper.c | 4 ++-- 2 files changed, 19 insertions(+), 2 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 9ef9d01ee2..4fbef58126 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -951,4 +951,21 @@ typedef struct ARMVAParameters { bool using64k : 1; } ARMVAParameters; +#ifdef CONFIG_USER_ONLY +static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, + uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + return (ARMVAParameters) { + /* 48-bit address space */ + .tsz = 16, + /* We can't handle tagged addresses properly in user-only mode */ + .tbi = false, + }; +} +#else +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data); +#endif + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index bd1b683766..b9ffc07fbc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9702,8 +9702,8 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } -static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); From patchwork Fri Dec 14 05:24:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153766 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1685084ljp; Thu, 13 Dec 2018 21:48:35 -0800 (PST) X-Google-Smtp-Source: AFSGD/UBLxG1wDu55sbHzJhwpnle5kJuDGaPDK1NA8vchyGGIcoNzliQel3bLEMQQ1olvfDFSOf8 X-Received: by 2002:a37:2a14:: with SMTP id q20mr1336288qkh.185.1544766515478; Thu, 13 Dec 2018 21:48:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544766515; cv=none; d=google.com; s=arc-20160816; b=WAdbzB3mKhEEMQLl+TYeoENPvWODj8yu8zARJOm5bTnlCbkPAo0yRergJ/fZz1jbnX vjtMjysUjJU6WsnLoUeDiiYN20L//EXP9zu/DGn40DDcfpTVQPwTZrfJ8rA5Z7+eNzas RVhia5qN4oiiqHoZE5L0hbw1gnOwYcEY0kbLxAqDkXZD9WRBvomJAmCw5i4OyIgTgvCT RwhOqbGBqf9dVsTVUXA1/LrNctjdaAQMMlB1jIeh8eSS7408JFbT7rH2+C247/oNjX7X b5GNQ4TvCcVYL12rXelHInD74fO/UNNPPSk5yj1yjnNQt6sAWxBlAFAIxSr1f0dQbn0y 8+Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Ukd5Hww0uE7Rkd0I9rxEuSLCu7Rgr66DnlqjrnEw6mc=; b=hY7peGbzOWzu3HBr0LEVcKCNMsmSmutXU/LbNB0d/2IDXLptBfwoPbAJEW4iLD04TE i9ym1har9BYjDTTuhi24RIMchwR3L7BClvQDEYDcD5EYX8qfvV83pSAqOGV/bQpFID+4 NQCNB6FUXNcMq7s/kg11MsSbLCd7ST3spTwcQtQaYdjOAx6fZ4XxTlWAeMgX0mUvrga0 s+M14jmqnP06GkZrk46dpdsMbFCVl7ojUTZGIPNRnG5hiyfiv26NmqaRB9F/N/syHxiw /nLNpSJcB3o3DN/xEcIVrm5M03FrvloZl4TYWQqFs6cXFtFuDWM09vcs3khkojZEdpiw oFpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cFyvJCkk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id g14si2429016qti.392.2018.12.13.21.48.35 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:48:35 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cFyvJCkk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59548 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXgKx-0007FA-1g for patch@linaro.org; Fri, 14 Dec 2018 00:48:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxu-0004mf-6W for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxo-0005UB-AH for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:46 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:41519) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxo-0005Sa-2l for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:40 -0500 Received: by mail-oi1-x243.google.com with SMTP id j21so3624865oii.8 for ; Thu, 13 Dec 2018 21:24:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ukd5Hww0uE7Rkd0I9rxEuSLCu7Rgr66DnlqjrnEw6mc=; b=cFyvJCkkkbihPbR3F2/fvjzdPF2RBsKVmEPxl/vTZJSRJT7jyffH18A/3xUoLdYwFr sVi1A9Wq22EiwRA3u7a5/zLdQZ5jQF+QGWJ6Z8A895u2oJCPofNkL8v8e9KJuqh0Dvy5 OeQA2ymH7gq3u4RZXJNmQfXU4+0dRkcQQY8NM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ukd5Hww0uE7Rkd0I9rxEuSLCu7Rgr66DnlqjrnEw6mc=; b=qZp01MVNQ0DO7JrqkE/MGha01VLlQXs0Vpv0jiPgwEwkw6ayy5kK0aWGhb1pR+5uUx pFKl4Rh0k3OlM9pfXakGENJmn5ZRSTKrd7DGOGaFtsDSCJqie7ZRY0kUenICsYrkbTut fUhmmjZctDh53QNjYE8UPapGZglgg8JFN0OMmTttkKArRGOp1ewwWdv5BncBDowTAFOB Wf11mTbFrH6Hqe4uwnG5Xgwez1cZwGKg24E/sVqwgiyrLBzwysdUuBMIlsdgzjoTOgRJ gDWWsxyfCQ6Jmy6yP0TpSQXmdalb3M06lD5TpyYYsqA68qED34wGpI3sPThhIAnfE+WX DnpA== X-Gm-Message-State: AA+aEWYjtBQWE6dEN8vT/wHUirpIZNuN6qrS6JFF7WE+1pueAE7k8WHj MN6rNEPzTOcXfoQIJBUBJSq6L5UiQXB56g== X-Received: by 2002:aca:3092:: with SMTP id w140mr995060oiw.237.1544765075879; Thu, 13 Dec 2018 21:24:35 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:24:03 -0600 Message-Id: <20181214052410.11863-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH v2 20/27] target/arm: Implement pauth_strip X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Stripping out the authentication data does not require any crypto, it merely requires the virtual address parameters. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 79cc9cf47b..329af51232 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1069,6 +1069,15 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, g_assert_not_reached(); /* FIXME */ } +static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +{ + uint64_t extfield = -param.select; + int bot_pac_bit = 64 - param.tsz; + int top_pac_bit = 64 - 8 * param.tbi; + + return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield); +} + static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data, int keynumber) { @@ -1077,7 +1086,10 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + + return pauth_original_ptr(ptr, param); } static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, From patchwork Fri Dec 14 05:24:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153761 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1681133ljp; Thu, 13 Dec 2018 21:41:44 -0800 (PST) X-Google-Smtp-Source: AFSGD/Wo7XMLUmmQvP13pfQSY9aqZBHJoZlv8C20nHg7fUu9gL1V2KnJcqpsO6gVrL/PmXEplw2I X-Received: by 2002:ac8:2585:: with SMTP id e5mr1497014qte.233.1544766104558; Thu, 13 Dec 2018 21:41:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544766104; cv=none; d=google.com; s=arc-20160816; b=NzMtmIaZtxTfaJvbKw9wiTZWMuKVB3DN2CA4WZ054ARwse8n+QbMe947bbH202/YxQ X6vEydTdDAy+Td7hJ5pU3yf8KC17j7LIa2R3DlurIqd1ssqopq86km+U0gPlEQv6T8qi swrsXftrJ71CyiubE10NSOSnJb4Cc2+VLkJoSJw1Jwy5m39iNyHiMG/B+lRn7KLp4XJB 5dw2YLKD9u4rp3m5/5Lc9p1ZdG7/nnSOC7O0w9qUijc7zwvYQJsPIe67wQRRvVdoMnfx 3e4kU8i2FnTSh5sLYXI4v0iHVKHGCJItmNBjpeATiVZ5pRRyCzoHokpydLCETWhyBz+l IfdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=QFHXVN9HoAm57mg/uppS1q9X/be1g/wjjh6mIB0wBzs=; b=eoAIzesmKi6d2MfCtKe4szreDyVbz/b5G4HppoHxCBPf9dCHieqNeLQOCdiVZSfKZx QZ47fn8FrfQiIWwTqjqfbBb7t4gKAMcZMIAk1u4gO73JbXEWBODd+UA9qiMemSoLTUms UZ56wAzw4qMS9kz4HMqTt+kCeklCuIqykIzD0uX8dwXxcZUliAjcMOY+AW2kuTirHd65 2eZa7o303w9qf8qKb2d7KpTJFx3p+oR20SkTCVHKNsrX7NyNf8Nwb+bswCi9oM7GdDsV uawsFnOJT4tLfPzInkL7u27TUkqI3FKBvwZpcLgE4F5Vt5RIpjvPChEXb2ZFAgRV56my RD0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RDYDnuzy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id a2si1859314qvj.165.2018.12.13.21.41.44 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:41:44 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RDYDnuzy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59515 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXgEJ-0002Co-KF for patch@linaro.org; Fri, 14 Dec 2018 00:41:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55875) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxu-0004mY-5o for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxq-0005V2-7Z for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:46 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:35960) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxo-0005T8-9D for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:40 -0500 Received: by mail-ot1-x344.google.com with SMTP id k98so4328312otk.3 for ; Thu, 13 Dec 2018 21:24:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QFHXVN9HoAm57mg/uppS1q9X/be1g/wjjh6mIB0wBzs=; b=RDYDnuzybaYYlWHaXFwkgC23+Z+H3tzXIX5R+/ROpiepGhQhq0HA2lKWCL7TzStTmY jlqz1+Blcq2mbz+OYfpD+joa6duR+fZfyuOPsp+q0NVB318cOm2yAWMQQuvziRakZf8a LINpZNPsKGCnnfWXeC5qc9/IZBQNnRoPfApNc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QFHXVN9HoAm57mg/uppS1q9X/be1g/wjjh6mIB0wBzs=; b=U4Gi+AMJi5iiMto8JhQIV4bQ+pM7vSnMC6/eps338BdmRBXSlKaFsm8eA3701ITx/f i4TpgaISKLVxmYPGI1rhqS/+k6+lIrXA800oN3Mu64fvTzt0j8lXRdzzDbeupzErlrI8 zIk4vGHne2OCFzphjtpgeZBQYFNh1J5qTSrPGq5Dt81fS8xNajm2J4DceUZUCI5MxnrH 2DYvaKwUJcsPlXoR6UlZxGCF2jH1cQ/n0oiRGorBZxNMxwC50czSf4aBD9nrxies2dEd bQ3jmVxNmQVkz1/CB80eiFpS4Cz28V42lXF58uonGcjQ/6IlNCuZLn6Mp7MhcjX5u92D IOow== X-Gm-Message-State: AA+aEWZ6g4uuma+uelj6FDeky1et89LTzcX8481v9idHNIqVN4jCCIk9 GtzkgMT+Dm2btzL8vW/gW0kh+GEN39aEUA== X-Received: by 2002:a9d:6b11:: with SMTP id g17mr1156616otp.70.1544765076909; Thu, 13 Dec 2018 21:24:36 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:24:04 -0600 Message-Id: <20181214052410.11863-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v2 21/27] target/arm: Implement pauth_auth X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not really functional yet, because the crypto is not yet implemented. This, however follows the Auth pseudo function. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 329af51232..87cff7d96a 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1081,7 +1081,26 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data, int keynumber) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + int bot_bit, top_bit; + uint64_t pac, orig_ptr, test; + + orig_ptr = pauth_original_ptr(ptr, param); + pac = pauth_computepac(orig_ptr, modifier, *key); + bot_bit = 64 - param.tsz; + top_bit = 64 - 8 * param.tbi; + + test = (pac ^ ptr) & ~MAKE_64BIT_MASK(55, 1); + if (unlikely(extract64(test, bot_bit, top_bit - bot_bit))) { + int error_code = (keynumber << 1) | (keynumber ^ 1); + if (param.tbi) { + return deposit64(ptr, 53, 2, error_code); + } else { + return deposit64(ptr, 61, 2, error_code); + } + } + return orig_ptr; } static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) From patchwork Fri Dec 14 05:24:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153764 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1683023ljp; Thu, 13 Dec 2018 21:44:52 -0800 (PST) X-Google-Smtp-Source: AFSGD/WzdlTFV9zqsNb9aBHvq0mZust5xKHRgeVBf5fj1x0pertH+kzIHbcH7QIAkho0IHcK4Mo/ X-Received: by 2002:ac8:278a:: with SMTP id w10mr1528659qtw.149.1544766291971; Thu, 13 Dec 2018 21:44:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544766291; cv=none; d=google.com; s=arc-20160816; b=XbTcdcm2FDvWFircwnVmejC225XRafhNf1SgXoFAYLNRW9npoKJGg87vnK0BDo1QZF bki6LebULa0D2LdY/+mn7SFkXII3aHk9eviNYeWssQlNHAQGz7QxYNkL/HRoKuyOE02h IxBwdZVhbdS7a7Zo2cf6gy6gy0z4IeWpKQ7/e+YcQiWIHr9Jc4T2hYNNI78m5eItVxZJ /O83+PdwDuarImAsMac4XaqHz7XCkuF3/SgQ82t7+3JZmUXn3NMqd4jD4Ahl7DOA0WaF gpiYvpo3aztq3G+cKVOIQ4w1Ur2kpokNYCs6RUgrRLcz2JsONM1uLKhprt+Jz5RcPMGY 5HAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=D0KeTZX6NEE2gCU4mzJT7v+AQLT+zWTV0IKozs79+gI=; b=o3KVuwFSevfknFJ/j84j4eGk7279XjQbS7vHJJi9lBERoortEA1ROyfPG7axJs+i5h 1WDjcGbBpZcMBPBASkwoL+qKHOdETr631RFs+WaLTYXugX8N1fZJa6c2ujHd40FxYbPu T97Cbd4ow0pV7fqqcELBcepGrR1YoTNWP47FILZTjshhX/+xUWzRg3p7pFEJTDQTCi/p jqzfVih2sRinCnSEeNg+SjzqUJA5peHrlfm4Gt9Q8iD07A1Tuehstjux7+xrapSGImR6 pc8ws7udTafqNllTh+9Gb7QsiU14jwmdclh7JkEaBNUABThR1LTsZ5dn+pmC4fz5CQ+z HmHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HIkc+LLx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id o14si982234qtb.200.2018.12.13.21.44.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:44:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HIkc+LLx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXgHL-0005E6-IF for patch@linaro.org; Fri, 14 Dec 2018 00:44:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55886) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxu-0004me-6U for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxq-0005VA-Bw for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:46 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:38618) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxp-0005TQ-00 for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:41 -0500 Received: by mail-ot1-x344.google.com with SMTP id e12so4318454otl.5 for ; Thu, 13 Dec 2018 21:24:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D0KeTZX6NEE2gCU4mzJT7v+AQLT+zWTV0IKozs79+gI=; b=HIkc+LLxgdmXub+WxKLrtRj6FZ3wU8VNZOJmDLd9Z1N9fp9KuS/Xj6rI0zjgaGv4x2 Fd/SVW2kVTjCEHHqVJA+cTvfdgwBZfRDlpouwhn6W9lCROmMRXOUspKkdkCBUjuFNA8o rJfA8l7cONIscYnjwc5ARC4qumLOZmq8EEO7c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D0KeTZX6NEE2gCU4mzJT7v+AQLT+zWTV0IKozs79+gI=; b=X2CwV21RuNriY+j/TnesNXnB6tW7K7zYhz9kVVVtPsdb1ruB1Ty1ZpIdl3wkb9y/OM gCTcourozaAU7PnZInhet/HpqDwo3YRPBkIl/LhjteUVzW4SVQmNYr/MUV817GwTzT8Q JQ/fVHDI60lwSm79q3DAOwj+i/4cRdNdK0aixdw9G8S5dYabzoo0MGqK8veoflfaxe7g h2o9to5jTXclAMx7KAiTwa2n2eLmv+Xw4Zx9/bbDaS9din/sCClBIH0IMxHhJj+ZUcCU KTtavwiSVc9oJQUQ8q8qgCvztIyZMdTCOY771xWCG5F4+/xq7H0Ix2jGGXR2B2s3xqCa q4cQ== X-Gm-Message-State: AA+aEWbplZI8O9MYwH5zQy8APMFVye7x1lfK/ZZCgyLQBJg1rXFTj3pw +D2QXCE5wshVOLPc2iBjFK26/kw1m9Qi5w== X-Received: by 2002:a05:6830:1584:: with SMTP id i4mr1089061otr.116.1544765077950; Thu, 13 Dec 2018 21:24:37 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:24:05 -0600 Message-Id: <20181214052410.11863-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v2 22/27] target/arm: Implement pauth_addpac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not really functional yet, because the crypto is not yet implemented. This, however follows the AddPAC pseudo function. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 40 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 87cff7d96a..19486b9677 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1066,7 +1066,45 @@ static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + uint64_t pac, ext_ptr, ext, test; + int bot_bit, top_bit; + + /* If tagged pointers are in use, use ptr<55>, otherwise ptr<63>. */ + if (param.tbi) { + ext = sextract64(ptr, 55, 1); + } else { + ext = sextract64(ptr, 63, 1); + } + + /* Build a pointer with known good extension bits. */ + top_bit = 64 - 8 * param.tbi; + bot_bit = 64 - param.tsz; + ext_ptr = deposit64(ptr, bot_bit, top_bit - bot_bit, ext); + + pac = pauth_computepac(ext_ptr, modifier, *key); + + /* Check if the ptr has good extension bits and corrupt the + * pointer authentication code if not. + */ + test = sextract64(ptr, bot_bit, top_bit - bot_bit); + if (test != 0 && test != -1) { + pac ^= 1ull << (top_bit - 1); + } + + /* Preserve the determination between upper and lower at bit 55, + * and insert pointer authentication code. + */ + if (param.tbi) { + ptr &= ~MAKE_64BIT_MASK(bot_bit, 55 - bot_bit + 1); + pac &= MAKE_64BIT_MASK(bot_bit, 54 - bot_bit + 1); + } else { + ptr &= MAKE_64BIT_MASK(0, bot_bit); + pac &= ~(MAKE_64BIT_MASK(55, 1) | MAKE_64BIT_MASK(0, bot_bit)); + } + ext &= MAKE_64BIT_MASK(55, 1); + return pac | ext | ptr; } static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) From patchwork Fri Dec 14 05:24:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153760 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1680088ljp; Thu, 13 Dec 2018 21:39:57 -0800 (PST) X-Google-Smtp-Source: AFSGD/WhnMYLpT+mVTTBIko7QmSkdA9HgLvKDn+2d5DER/Qy3hY0YA/Uu4J0J2YhloLz9HrHzDEx X-Received: by 2002:a37:d1c5:: with SMTP id o66mr1408010qkl.293.1544765997554; Thu, 13 Dec 2018 21:39:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765997; cv=none; d=google.com; s=arc-20160816; b=jC6e7ZF4jbrPcAwwjCVNeWrnaqvCYz/J6Qo4SDdl0ONs+EY8uZmWu+vLlujc8bXLEf kRJR3NUlVq+xXSXAdCsB69pf1mYSZWHmj5KRxumXEnF/qDuIhHiv5N+h+Z/HgVOuXxp2 0HyDCZ0amJajQh6Z+GzTpjeNmkdDLkFR5J0RKvBKV7o1+HemNscU5UZaaJSntrwMoxPy uPXRL59rqtYbfQU9E3rAnFR2tGzH1ZngsaKfVqkGlxWa+jn7WEg1+G3P2W1L6Qx0OOS4 5fNTw5ZbGhyeyGHvEbkrhnZDKD05awdJYyuwM5GrIZbhJjpWmgc0smgkANd/BdlNAzBg D2eA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=250qEhnq+TUnyD+ms+pDEFXmUEcfmZeEXSJ+VxZZrPM=; b=ZJgAOMRQjtqvDMkuA6rc1aOrcgCfIoEwhk/EIe4B3K4CKNy/MYVJxpcpjaP7LWWlMJ 5w9Vy0kMRuh23xd5kP8m4GGZFyQ5h/AH3/Wrjjor6ITzIFWYsh0wiTRUaNK/Gxcu86Ae zXSFdWGbhD84PKOGwWOb78lm8bJbe0cfNxJmFSYq64D+iXJdhxcNNvi6MPhbregSLu4A 6WbYHNgac7RT90hO7Oo48bNmF/w/pLdOJcAXlG/unbjgB/5T3XL7W2EgVmFqheQN1qHd rfMbbSYoGVHFQLEMYUfs9EP4refoSZrBl7Mxd6rG4SVB7DaJOVwftE+4ZWxMnKlAz90l aadQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NNSXb+dL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id c41si1664270qtk.178.2018.12.13.21.39.57 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:39:57 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NNSXb+dL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59509 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXgCb-0001Qh-1u for patch@linaro.org; Fri, 14 Dec 2018 00:39:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55878) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxu-0004mb-5v for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxq-0005Uu-1U for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:46 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:39256) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxo-0005Th-6a for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:40 -0500 Received: by mail-oi1-x243.google.com with SMTP id i6so3628562oia.6 for ; Thu, 13 Dec 2018 21:24:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=250qEhnq+TUnyD+ms+pDEFXmUEcfmZeEXSJ+VxZZrPM=; b=NNSXb+dL2xmJUDJroMRiCyupXFFv37bwgKHgxh/6KD1Xt8vgvkpxYxM+KTDHyl+KL/ n/XtXarbxe0vFjoMA0z7BXkLzEvQ6kT1JjH8UGxLe9RozXE5yZAnN02BY/xyBGYsz2jY nvmPoXahPncD+ph7KNjKUXG9FrhyGwH1JDXHQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=250qEhnq+TUnyD+ms+pDEFXmUEcfmZeEXSJ+VxZZrPM=; b=VuBqpYZ9Wr3nYMgzwaCcR/YfVIIsK+8yRfm6ahwZ47+2jJnh+BakDl3AcwQHVrW/Sj COPdiV4BY78Vb2pmJcaYRuXr2RT1iX/0W05lRB1d6pxYVgDUsO5nqYIMxF8Siso4P9su HRdXs1MsiVWkddDen48n+fclNzq4lIiV6UQs6KaVlr/RN52dRG4DXnUIwUCtzILdGpeu qutcTbeMl5aBJiVcTAf7KGjnJzWjo8vv07qxSlNLaScUDsmDn7KrsZcMPHHnkAd7VTwL zoX1qszzuhFS7Ixfiehuel+q8sh2WmvwIovCL80WbzDkTYzwAge5R4ZihOh5u0mnOir6 DiIQ== X-Gm-Message-State: AA+aEWY2sdZgMVMLT8DnnsGBaMs06LDI5uVtKn+cCsPRejYaqDx9dAIe Vf9ihH/o0VlC2t7v5vpHPgGWIbQ7hi6e+w== X-Received: by 2002:aca:32d7:: with SMTP id y206mr908748oiy.151.1544765078990; Thu, 13 Dec 2018 21:24:38 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:24:06 -0600 Message-Id: <20181214052410.11863-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH v2 23/27] target/arm: Implement pauth_computepac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the main crypto routine, an implementation of QARMA. This matches, as much as possible, ARM pseudocode. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 241 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 240 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 19486b9677..1da7867a42 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1057,10 +1057,249 @@ uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp) * Helpers for ARMv8.3-PAuth. */ +static uint64_t pac_cell_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= extract64(i, 52, 4); + o |= extract64(i, 24, 4) << 4; + o |= extract64(i, 44, 4) << 8; + o |= extract64(i, 0, 4) << 12; + + o |= extract64(i, 28, 4) << 16; + o |= extract64(i, 48, 4) << 20; + o |= extract64(i, 4, 4) << 24; + o |= extract64(i, 40, 4) << 28; + + o |= i & MAKE_64BIT_MASK(32, 4); + o |= extract64(i, 12, 4) << 36; + o |= extract64(i, 56, 4) << 40; + o |= extract64(i, 8, 4) << 44; + + o |= extract64(i, 36, 4) << 48; + o |= extract64(i, 16, 4) << 52; + o |= extract64(i, 40, 4) << 56; + o |= i & MAKE_64BIT_MASK(60, 4); + + return o; +} + +static uint64_t pac_cell_inv_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= extract64(i, 12, 4); + o |= extract64(i, 24, 4) << 4; + o |= extract64(i, 48, 4) << 8; + o |= extract64(i, 36, 4) << 12; + + o |= extract64(i, 56, 4) << 16; + o |= extract64(i, 44, 4) << 20; + o |= extract64(i, 4, 4) << 24; + o |= extract64(i, 16, 4) << 28; + + o |= i & MAKE_64BIT_MASK(32, 4); + o |= extract64(i, 52, 4) << 36; + o |= extract64(i, 28, 4) << 40; + o |= extract64(i, 8, 4) << 44; + + o |= extract64(i, 20, 4) << 48; + o |= extract64(i, 0, 4) << 52; + o |= extract64(i, 40, 4) << 56; + o |= i & MAKE_64BIT_MASK(60, 4); + + return o; +} + +static uint64_t pac_sub(uint64_t i) +{ + static const uint8_t sub[16] = { + 0xb, 0x6, 0x8, 0xf, 0xc, 0x0, 0x9, 0xe, + 0x3, 0x7, 0x4, 0x5, 0xd, 0x2, 0x1, 0xa, + }; + uint64_t o = 0; + int b; + + for (b = 0; b < 64; b += 16) { + o |= (uint64_t)sub[(i >> b) & 0xf] << b; + } + return o; +} + +static uint64_t pac_inv_sub(uint64_t i) +{ + static const uint8_t inv_sub[16] = { + 0x5, 0xe, 0xd, 0x8, 0xa, 0xb, 0x1, 0x9, + 0x2, 0x6, 0xf, 0x0, 0x4, 0xc, 0x7, 0x3, + }; + uint64_t o = 0; + int b; + + for (b = 0; b < 64; b += 16) { + o |= (uint64_t)inv_sub[(i >> b) & 0xf] << b; + } + return o; +} + +static int rot_cell(int cell, int n) +{ + cell |= cell << 4; + cell >>= n; + return cell & 0xf; +} + +static uint64_t pac_mult(uint64_t i) +{ + uint64_t o = 0; + int b; + + for (b = 0; b < 4 * 4; b += 4) { + int i0, i4, i8, ic, t0, t1, t2, t3; + + i0 = extract64(i, b, 4); + i4 = extract64(i, b + 4 * 4, 4); + i8 = extract64(i, b + 8 * 4, 4); + ic = extract64(i, b + 12 * 4, 4); + + t0 = rot_cell(i8, 1) ^ rot_cell(i4, 2) ^ rot_cell(i0, 1); + t1 = rot_cell(ic, 1) ^ rot_cell(i4, 1) ^ rot_cell(i0, 2); + t2 = rot_cell(ic, 2) ^ rot_cell(i8, 1) ^ rot_cell(i0, 1); + t3 = rot_cell(ic, 2) ^ rot_cell(i8, 2) ^ rot_cell(i4, 1); + + o |= (uint64_t)t3 << b; + o |= (uint64_t)t2 << (b + 4 * 4); + o |= (uint64_t)t1 << (b + 8 * 4); + o |= (uint64_t)t0 << (b + 12 * 4); + } + return o; +} + +static uint64_t tweak_cell_rot(uint64_t cell) +{ + return (cell >> 1) | (((cell ^ (cell >> 1)) & 1) << 3); +} + +static uint64_t tweak_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= extract64(i, 16, 4) << 0; + o |= extract64(i, 20, 4) << 4; + o |= tweak_cell_rot(extract64(i, 24, 4)) << 8; + o |= extract64(i, 28, 4) << 12; + + o |= tweak_cell_rot(extract64(i, 44, 4)) << 16; + o |= extract64(i, 8, 4) << 20; + o |= extract64(i, 12, 4) << 24; + o |= tweak_cell_rot(extract64(i, 32, 4)) << 28; + + o |= extract64(i, 48, 4) << 32; + o |= extract64(i, 52, 4) << 36; + o |= extract64(i, 56, 4) << 40; + o |= tweak_cell_rot(extract64(i, 60, 4)) << 44; + + o |= tweak_cell_rot(extract64(i, 0, 4)) << 48; + o |= extract64(i, 4, 4) << 52; + o |= tweak_cell_rot(extract64(i, 40, 4)) << 56; + o |= tweak_cell_rot(extract64(i, 36, 4)) << 60; + + return o; +} + +static uint64_t tweak_cell_inv_rot(uint64_t cell) +{ + return ((cell << 1) & 0xf) | ((cell & 1) ^ (cell >> 3)); +} + +static uint64_t tweak_inv_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= tweak_cell_inv_rot(extract64(i, 48, 4)); + o |= extract64(i, 52, 4) << 4; + o |= extract64(i, 20, 4) << 8; + o |= extract64(i, 24, 4) << 12; + + o |= extract64(i, 0, 4) << 16; + o |= extract64(i, 4, 4) << 20; + o |= tweak_cell_inv_rot(extract64(i, 8, 4)) << 24; + o |= extract64(i, 12, 4) << 28; + + o |= tweak_cell_inv_rot(extract64(i, 28, 4)) << 32; + o |= tweak_cell_inv_rot(extract64(i, 60, 4)) << 36; + o |= tweak_cell_inv_rot(extract64(i, 56, 4)) << 40; + o |= tweak_cell_inv_rot(extract64(i, 16, 4)) << 44; + + o |= extract64(i, 32, 4) << 48; + o |= extract64(i, 36, 4) << 52; + o |= extract64(i, 40, 4) << 56; + o |= tweak_cell_inv_rot(extract64(i, 44, 4)) << 60; + + return o; +} + static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, ARMPACKey key) { - g_assert_not_reached(); /* FIXME */ + static const uint64_t RC[5] = { + 0x0000000000000000ull, + 0x13198A2E03707344ull, + 0xA4093822299F31D0ull, + 0x082EFA98EC4E6C89ull, + 0x452821E638D01377ull, + }; + const uint64_t alpha = 0xC0AC29B7C97C50DDull; + /* Note that in the ARM pseudocode, key0 contains bits <127:64> + * and key1 contains bits <63:0> of the 128-bit key. + */ + uint64_t key0 = key.hi, key1 = key.lo; + uint64_t workingval, runningmod, roundkey, modk0; + int i; + + modk0 = (key0 << 63) | ((key0 >> 1) ^ (key0 >> 63)); + runningmod = modifier; + workingval = data ^ key0; + + for (i = 0; i <= 4; ++i) { + roundkey = key1 ^ runningmod; + workingval ^= roundkey; + workingval ^= RC[i]; + if (i > 0) { + workingval = pac_cell_shuffle(workingval); + workingval = pac_mult(workingval); + } + workingval = pac_sub(workingval); + runningmod = tweak_shuffle(runningmod); + } + roundkey = modk0 ^ runningmod; + workingval ^= roundkey; + workingval = pac_cell_shuffle(workingval); + workingval = pac_mult(workingval); + workingval = pac_sub(workingval); + workingval = pac_cell_shuffle(workingval); + workingval = pac_mult(workingval); + workingval ^= key1; + workingval = pac_cell_inv_shuffle(workingval); + workingval = pac_inv_sub(workingval); + workingval = pac_mult(workingval); + workingval = pac_cell_inv_shuffle(workingval); + workingval ^= key0; + workingval ^= runningmod; + for (i = 0; i <= 4; ++i) { + workingval = pac_inv_sub(workingval); + if (i < 4) { + workingval = pac_mult(workingval); + workingval = pac_cell_inv_shuffle(workingval); + } + runningmod = tweak_inv_shuffle(runningmod); + roundkey = key1 ^ runningmod; + workingval ^= RC[4-i]; + workingval ^= roundkey; + workingval ^= alpha; + } + workingval ^= modk0; + + return workingval; } static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, From patchwork Fri Dec 14 05:24:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153758 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1679876ljp; Thu, 13 Dec 2018 21:39:35 -0800 (PST) X-Google-Smtp-Source: AFSGD/XyBAaSAgGW1vVnjAGM9nVOtygIvh2FfUcHlnE1sDcmgB5WT5GNZMx6z5bHznGI3t9Y2rh+ X-Received: by 2002:aed:20ca:: with SMTP id 68mr1520946qtb.296.1544765975249; Thu, 13 Dec 2018 21:39:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765975; cv=none; d=google.com; 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X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v2 24/27] target/arm: Add PAuth system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index b9ffc07fbc..f1e9254c9a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5061,6 +5061,70 @@ static CPAccessResult access_lor_other(CPUARMState *env, return access_lor_ns(env); } +#ifdef TARGET_AARCH64 +static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el < 2 && + arm_feature(env, ARM_FEATURE_EL2) && + !(arm_hcr_el2_eff(env) & HCR_APK)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_APK)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo pauth_reginfo[] = { + { .name = "APDAKEYLOW_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apda_key.lo) }, + { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apda_key.hi) }, + { .name = "APDBKEYLOW_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apdb_key.lo) }, + { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apdb_key.hi) }, + { .name = "APGAKEYLOW_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apia_key.lo) }, + { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apia_key.hi) }, + { .name = "APIAKEYLOW_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apia_key.lo) }, + { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apia_key.hi) }, + { .name = "APIBKEYLOW_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apib_key.lo) }, + { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apib_key.hi) }, + REGINFO_SENTINEL +}; +#endif + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -5845,6 +5909,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); } } + +#ifdef TARGET_AARCH64 + if (cpu_isar_feature(aa64_pauth, cpu)) { + define_arm_cp_regs(cpu, pauth_reginfo); + } +#endif } void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) From patchwork Fri Dec 14 05:24:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153752 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1676561ljp; Thu, 13 Dec 2018 21:33:51 -0800 (PST) X-Google-Smtp-Source: AFSGD/W7kFUxH6tVDYWrN5hIb6IskZzLK+5KV8K/YgweOlfzWJZ/h34L3lnM9OItAWtw4MWlZ+5C X-Received: by 2002:a0c:9359:: with SMTP id e25mr1476302qve.203.1544765631538; Thu, 13 Dec 2018 21:33:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v2 25/27] target/arm: Enable PAuth for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1d57be0c91..84f70b2a24 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -316,6 +316,10 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64isar1; t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ + t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); + t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); cpu->isar.id_aa64isar1 = t; t = cpu->isar.id_aa64pfr0; From patchwork Fri Dec 14 05:24:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153754 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1676871ljp; Thu, 13 Dec 2018 21:34:25 -0800 (PST) X-Google-Smtp-Source: AFSGD/Wgy9Txk4IurLms2OcgBVLyRcMBp5ixDwDhxkaAll3NzXOEAWdzUm4n0Gr2lU02ysmYdc8K X-Received: by 2002:a37:9c57:: with SMTP id f84mr1387117qke.176.1544765665404; Thu, 13 Dec 2018 21:34:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765665; cv=none; d=google.com; s=arc-20160816; b=nPm5gL4zIBa29/Inql9hRwd3XgmbTrfTWzODzs6YivGqmc6lvfAGbYNQfHRFIQ1/sb 0pSloz8s487aHzErhfnDiLUCobCvIFPcfgLdJHm1LNqn+2y+XxzagXeYXUEzxvCJPLls QM2Ba/rtMMdZ+dd5rxL5m/Pbzt1OtkH6iAgt8Yn610JOpOWw9EoZHMHlkozljBZwt+RN mBvV828cFq88qUARRwQ+nD7OvKof7Sg/JSVBgfecJsKrNKe8jXuqMsWStUO8lp4Hx0P7 NckmSX2d+dCZU2Ca2Q48iezl41/3xxizMaYePOXeN6/m2YWq2MDe2VtBmsx5bmCwsaDd tMsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5lV189kkOB6fne0CCcwUJT1P8TEOV3BpZfvcoTnPXCM=; b=cKfPmeBACjvXiKs8ZaJxJe8MyqmbC6LOp6iMyOL7Cxt7L2GXYOcMU+oY4MW6ki3nrO R6AZbnzvqD18NpIlSFNgBrokuytI/EWRZl3lkro2IS9hCGeqVGmy7w54cdqzcLWTARa0 eR5SmLtBtEFH37Tz9e7Z4EpEFlZzoQUz4ueytGQZK12h6VnCRGiw7bIdVyXqk0pQlHP1 T49eYkCCqEln0Iellx8+qRJpC5faalvb9Za+GOf+5UUnSRGEthStc0akc2QleYlFpdpi hKKIyaHgDMj6UidQd1yI7u2YIruo7/cn1TpJfOTm35CfOoPi3b4HLMblsLp1KytoeaMJ 2MDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fWyx79si; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n189si77534qkc.170.2018.12.13.21.34.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:34:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fWyx79si; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59480 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXg7E-0004sI-Qa for patch@linaro.org; Fri, 14 Dec 2018 00:34:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55880) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxu-0004md-64 for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxs-0005Vv-EO for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:46 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:41376) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxs-0005VX-3P for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:44 -0500 Received: by mail-ot1-x343.google.com with SMTP id u16so4301790otk.8 for ; Thu, 13 Dec 2018 21:24:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5lV189kkOB6fne0CCcwUJT1P8TEOV3BpZfvcoTnPXCM=; b=fWyx79siYq7SkTSY1cduGbtIBdUNb8ZV09FhBtSnn2jKNJI7qdHtwKWnLgmd89FksO dHU8q6XmRI4feugX8OMGQn5ke0XNxdI+dylJevJKX/+KwL0EwIDnWy0w6uoEUJwQsfbR 0ciadTxqWcO6DM4816+G6cawhucVVtWeRDSVQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5lV189kkOB6fne0CCcwUJT1P8TEOV3BpZfvcoTnPXCM=; b=I0+1aiWvLfxAUoZ2TlPE6ZrYDXFQjM3MjVYmnU8E4Gwk3KD7b0GSsRLUMkT6jQDjOe 0CoLAuAo82XqN1vEvIsel4evWyL2wy8AnD/zqgObhicDh6SkdvS03WXPj3tqylDpJIsA FxFL6oTSLiLlHUXREhPj6q5XdZGxH/tgH7JNVNouhrxQsNMghnkTMUnNo6j2gtW6xQtc Uxxp8yVLcxWT0XSf/pms7phGrwxjlkxp2OziVIZaowNKNezNvLFX7B/OwmeR+eHdfm8N ONE5WYD1VyOQx8oxIPD63MPEE9A7H+bGwToBj9m+2JDVRRWkWxg9URp+YqZ2gc1kjHqf CuZw== X-Gm-Message-State: AA+aEWbwcKFwMO4Nu3dNJ5ny0V+iuk3rxymN5eNXigQ+dc1u4olSiC0T eLWVG4V1e3nBIYwho8wGeE6vnJIlbL0+hA== X-Received: by 2002:a9d:5183:: with SMTP id y3mr1068847otg.5.1544765082302; Thu, 13 Dec 2018 21:24:42 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:24:09 -0600 Message-Id: <20181214052410.11863-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v2 26/27] target/arm: Enable PAuth for user-only, part 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" FIXME: We should have an attribute that controls the EL1 enable bits. We may not always want to turn on pointer authentication with -cpu max. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0b185f8d30..bc2c9eb551 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -162,6 +162,12 @@ static void arm_cpu_reset(CPUState *s) env->pstate = PSTATE_MODE_EL0t; /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; + /* Enable all PAC keys. */ + env->cp15.sctlr_el[1] |= SCTLR_EnIA | SCTLR_EnIB; + env->cp15.sctlr_el[1] |= SCTLR_EnDA | SCTLR_EnDB; + /* Enable all PAC instructions */ + env->cp15.hcr_el2 |= HCR_API; + env->cp15.scr_el3 |= SCR_API; /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); /* and to the SVE instructions */ From patchwork Fri Dec 14 05:24:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153768 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1685990ljp; Thu, 13 Dec 2018 21:50:02 -0800 (PST) X-Google-Smtp-Source: AFSGD/Vax672J9t3Pd7lkpVd9GVfX4PkagUmTCckZOVc2Ln3xDusp+Z99IYOqYOB/FVxuUh/fXDb X-Received: by 2002:ac8:962:: with SMTP id z31mr1476627qth.305.1544766602379; Thu, 13 Dec 2018 21:50:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544766602; cv=none; d=google.com; s=arc-20160816; b=wAxkAA490gWM3Yt1OWDNasiLNN4X5lW7Bo3gmy4sAfRBJnH9a+sMidI0nzBeIbbTKX wAFecbWhX43DHAtbKtUJJ+Bo752l4yffOMed3wZAQ6Y8aSMdf4SIc39uFwXeQv3Pf08Q xe6hJIzOBNa3v/qCFadMsazx1r8aFO8EjdEFz5C/uN34RMYRRDnvav0UW0H5twnYyTXj YSD4Ck4lhI8PBBO2iaNrjnktEKMftFNmCduCe/TkNHQoO88K5E0i47qnYLgfeJbh6a3h 3TGWK5OoadZ6E31v7d/nhgsztDver7YgaQbBBm2CNQ9bqdHdbyCwT+BY3guYxAKO2BDR slyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=UXA8cM0cwjStQGcIey4x1Y3QYETvHjeC6zxF5/48Sfk=; b=vV0W+6lI1DVDbmFIx21pbhyxBW4hhyCs5TWBtD7i0uEwNKEE6PMmQU93+lGfrAQ31j W6Xd1WeBJtpqQfPwLnkIDrGRcPNhv9pbsYuU/wK8jcFcMjOwWTFTS07k1Q8s4ZIlQkTo vC+YQ7SpwU0CseqZfNA5jNv5CM1VbWSG3nvQoUKMH48uxMr4kDNPy8pgijZhKbixHP4k 8VNVwSFkuvHHwq8IMBlZN3SyMO82DIjOXSQmJE/CzsMu+iCeG0/FgwElXCSoom6ZYUvp 7RTO+cpdOC7XVtfFcYrVamqZo8RI3YczlQNRYEMcSo0ll5DziRuz/Q5pAM5SSNrQYosO 26/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IybUCLK+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id v7si2366560qkv.68.2018.12.13.21.50.02 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:50:02 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IybUCLK+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59554 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXgML-0000RR-Ux for patch@linaro.org; Fri, 14 Dec 2018 00:50:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55876) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxu-0004mZ-5u for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxs-0005W4-Iz for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:46 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:37728) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxs-0005Vj-DP for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:44 -0500 Received: by mail-oi1-x242.google.com with SMTP id y23so3631802oia.4 for ; Thu, 13 Dec 2018 21:24:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UXA8cM0cwjStQGcIey4x1Y3QYETvHjeC6zxF5/48Sfk=; b=IybUCLK+jzARGxmjVpzT3qdpcTflqMGwBXCFjd/2mu1NV1yCWmyv4k3ITixNAALHmq +LIxwzdR+OnJQyxhjCDyL0mKj2rYqmyKaodB9U4cpekrDZ9/Ydfu8uH3bT3d1B9/3H2s PHmnCCsL/Ei1RhE8C8/ybsd3njCkCcR/mnyOM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UXA8cM0cwjStQGcIey4x1Y3QYETvHjeC6zxF5/48Sfk=; b=YhBeYtj+qks2Rwjx+KbltRQGV13AURUAjYmp9cT4Aqn45E5dLzIyVXlnoDJ0q567uc pzKTREs5I7BIHUQQ//0iz56xeC+UWxRo7/tqjOaxFAUp6qyv5NSvxVeK25FaBeaOQcGX qyyKgCgBgLrE2qyEzTdrYg2ZSjnADIm8DxOPXu2goFxrkQFGV5GJ7ZMy/biyikO8xlbQ gSqF+my6BtNR/qUa5p7kfj5ArRVKtDDlp8LusmUMHiXDFfvelrkG0QapVCWcUSsIaLWo HmWx5C0saN+ZuJmhOrtD49jk1BpOnDiBYimYCOFhONqFBEqegHsbbOKbDBndGn5utCgP bd1w== X-Gm-Message-State: AA+aEWZc8J5WmeMWoSAKL48PyssVmH3reB0oYjKDiAe+4npSAjKx+3N6 hQihdoEg04RrzsE33o9WZ6MUoCyuPNBkEQ== X-Received: by 2002:aca:ec55:: with SMTP id k82mr920668oih.55.1544765083290; Thu, 13 Dec 2018 21:24:43 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:24:10 -0600 Message-Id: <20181214052410.11863-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v2 27/27] target/arm: Tidy TBI handling in gen_a64_set_pc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can perform this with fewer operations. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 65 ++++++++++++++------------------------ 1 file changed, 23 insertions(+), 42 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c57c89d98a..5c06e429d4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -261,7 +261,7 @@ void gen_a64_set_pc_im(uint64_t val) /* Load the PC from a generic TCG variable. * * If address tagging is enabled via the TCR TBI bits, then loading - * an address into the PC will clear out any tag in the it: + * an address into the PC will clear out any tag in it: * + for EL2 and EL3 there is only one TBI bit, and if it is set * then the address is zero-extended, clearing bits [63:56] * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 @@ -276,56 +276,37 @@ void gen_a64_set_pc_im(uint64_t val) */ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) { + bool tbi0 = s->tbi0, tbi1 = s->tbi1; if (s->current_el <= 1) { - /* Test if NEITHER or BOTH TBI values are set. If so, no need to - * examine bit 55 of address, can just generate code. - * If mixed, then test via generated code - */ - if (s->tbi0 && s->tbi1) { - TCGv_i64 tmp_reg = tcg_temp_new_i64(); - /* Both bits set, sign extension from bit 55 into [63:56] will - * cover both cases - */ - tcg_gen_shli_i64(tmp_reg, src, 8); - tcg_gen_sari_i64(cpu_pc, tmp_reg, 8); - tcg_temp_free_i64(tmp_reg); - } else if (!s->tbi0 && !s->tbi1) { - /* Neither bit set, just load it as-is */ - tcg_gen_mov_i64(cpu_pc, src); - } else { - TCGv_i64 tcg_tmpval = tcg_temp_new_i64(); - TCGv_i64 tcg_bit55 = tcg_temp_new_i64(); - TCGv_i64 tcg_zero = tcg_const_i64(0); + if (tbi0 || tbi1) { + /* Sign-extend from bit 55. */ + tcg_gen_sextract_i64(cpu_pc, src, 0, 56); - tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55)); + if (tbi0 != tbi1) { + TCGv_i64 tcg_zero = tcg_const_i64(0); - if (s->tbi0) { - /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */ - tcg_gen_andi_i64(tcg_tmpval, src, - 0x00FFFFFFFFFFFFFFull); - tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_zero, - tcg_tmpval, src); - } else { - /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */ - tcg_gen_ori_i64(tcg_tmpval, src, - 0xFF00000000000000ull); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_zero, - tcg_tmpval, src); + /* + * The two TBI bits differ. + * If tbi0, then !tbi1: only use the extension if positive. + * if !tbi0, then tbi1: only use the extension if negative. + */ + tcg_gen_movcond_i64(tbi0 ? TCG_COND_GE : TCG_COND_LT, + cpu_pc, cpu_pc, tcg_zero, cpu_pc, src); + tcg_temp_free_i64(tcg_zero); } - tcg_temp_free_i64(tcg_zero); - tcg_temp_free_i64(tcg_bit55); - tcg_temp_free_i64(tcg_tmpval); + return; } - } else { /* EL > 1 */ - if (s->tbi0) { + } else { + if (tbi0) { /* Force tag byte to all zero */ - tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull); - } else { - /* Load unmodified address */ - tcg_gen_mov_i64(cpu_pc, src); + tcg_gen_extract_i64(cpu_pc, src, 0, 56); + return; } } + + /* Load unmodified address */ + tcg_gen_mov_i64(cpu_pc, src); } typedef struct DisasCompare64 {