From patchwork Thu Apr 14 17:39:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 561296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34DD0C433EF for ; Thu, 14 Apr 2022 17:40:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343490AbiDNRmy (ORCPT ); Thu, 14 Apr 2022 13:42:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343614AbiDNRmq (ORCPT ); Thu, 14 Apr 2022 13:42:46 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 135CCD4C8C; Thu, 14 Apr 2022 10:40:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649957983; cv=none; d=zohomail.com; s=zohoarc; b=ZiOpzMWO9hjhHMY5nGJBPot082I/+QieyM/+iyIEUDfqrEdCD2F6JIfFW+DI5eK+V57s3IWhzzAY4X+BaB/SdCWYx8yS1WVo0PxdbdtVKod2RfDED5SzrsvgEqXPMM2sLvnfD1ci1v/1ecVXJIZ1UVFpYnoErlGTggvqkoeYp0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649957983; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=4frekDtBEqArrjelj1qY9f+heZVVCvsElXQVAZOYy5k=; b=XUfIyS64fN6Sp43XA7Snlu8eQwIcRhikRH9G8+Pp3qUgmnJ2PnwFgFuY5ys1NOMCZ9Wx/1dZHJU55JrvWPsXUzmuigPwpzZZnJa7RVq8FMEGHnGeX3+4nWCudIx8FIzFVuJfS0+3ESEWmF+wgA/+l+zYsr+HAVBliB0LPGxyDFM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649957983; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=4frekDtBEqArrjelj1qY9f+heZVVCvsElXQVAZOYy5k=; b=W3poNdndHiXXyP0aWjrZo8sYHWunMiP4ToLCXGetqG9CCQoMcScJJahlgbpwDiZg +sgDdHzQ3DO+s9FTD2yspCZCiknAvlA+cPJ7iVyXqVif64MS3Dbtvx95CnO7Kqx/6+2 ZJwcjH9MCW0xjVX6hh8PrQKKhG1N8Rcl/hFBsG5k= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649957982913725.4761330643432; Thu, 14 Apr 2022 10:39:42 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 01/14] pinctrl: ralink: rename MT7628(an) functions to MT76X8 Date: Thu, 14 Apr 2022 20:39:03 +0300 Message-Id: <20220414173916.5552-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The functions that include "MT7628(an)" are for MT7628 and MT7688 SoCs. Rename them to MT76X8 to refer to both of the SoCs. Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 218 ++++++++++++------------ 1 file changed, 109 insertions(+), 109 deletions(-) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index 6853b5b8b0fe..d3f9feec1f74 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -112,260 +112,260 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = { { 0 } }; -static struct rt2880_pmx_func pwm1_grp_mt7628[] = { +static struct rt2880_pmx_func pwm1_grp_mt76x8[] = { FUNC("sdxc d6", 3, 19, 1), FUNC("utif", 2, 19, 1), FUNC("gpio", 1, 19, 1), FUNC("pwm1", 0, 19, 1), }; -static struct rt2880_pmx_func pwm0_grp_mt7628[] = { +static struct rt2880_pmx_func pwm0_grp_mt76x8[] = { FUNC("sdxc d7", 3, 18, 1), FUNC("utif", 2, 18, 1), FUNC("gpio", 1, 18, 1), FUNC("pwm0", 0, 18, 1), }; -static struct rt2880_pmx_func uart2_grp_mt7628[] = { +static struct rt2880_pmx_func uart2_grp_mt76x8[] = { FUNC("sdxc d5 d4", 3, 20, 2), FUNC("pwm", 2, 20, 2), FUNC("gpio", 1, 20, 2), FUNC("uart2", 0, 20, 2), }; -static struct rt2880_pmx_func uart1_grp_mt7628[] = { +static struct rt2880_pmx_func uart1_grp_mt76x8[] = { FUNC("sw_r", 3, 45, 2), FUNC("pwm", 2, 45, 2), FUNC("gpio", 1, 45, 2), FUNC("uart1", 0, 45, 2), }; -static struct rt2880_pmx_func i2c_grp_mt7628[] = { +static struct rt2880_pmx_func i2c_grp_mt76x8[] = { FUNC("-", 3, 4, 2), FUNC("debug", 2, 4, 2), FUNC("gpio", 1, 4, 2), FUNC("i2c", 0, 4, 2), }; -static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("refclk", 0, 37, 1) }; -static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 36, 1) }; -static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) }; -static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) }; +static struct rt2880_pmx_func refclk_grp_mt76x8[] = { FUNC("refclk", 0, 37, 1) }; +static struct rt2880_pmx_func perst_grp_mt76x8[] = { FUNC("perst", 0, 36, 1) }; +static struct rt2880_pmx_func wdt_grp_mt76x8[] = { FUNC("wdt", 0, 38, 1) }; +static struct rt2880_pmx_func spi_grp_mt76x8[] = { FUNC("spi", 0, 7, 4) }; -static struct rt2880_pmx_func sd_mode_grp_mt7628[] = { +static struct rt2880_pmx_func sd_mode_grp_mt76x8[] = { FUNC("jtag", 3, 22, 8), FUNC("utif", 2, 22, 8), FUNC("gpio", 1, 22, 8), FUNC("sdxc", 0, 22, 8), }; -static struct rt2880_pmx_func uart0_grp_mt7628[] = { +static struct rt2880_pmx_func uart0_grp_mt76x8[] = { FUNC("-", 3, 12, 2), FUNC("-", 2, 12, 2), FUNC("gpio", 1, 12, 2), FUNC("uart0", 0, 12, 2), }; -static struct rt2880_pmx_func i2s_grp_mt7628[] = { +static struct rt2880_pmx_func i2s_grp_mt76x8[] = { FUNC("antenna", 3, 0, 4), FUNC("pcm", 2, 0, 4), FUNC("gpio", 1, 0, 4), FUNC("i2s", 0, 0, 4), }; -static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = { +static struct rt2880_pmx_func spi_cs1_grp_mt76x8[] = { FUNC("-", 3, 6, 1), FUNC("refclk", 2, 6, 1), FUNC("gpio", 1, 6, 1), FUNC("spi cs1", 0, 6, 1), }; -static struct rt2880_pmx_func spis_grp_mt7628[] = { +static struct rt2880_pmx_func spis_grp_mt76x8[] = { FUNC("pwm_uart2", 3, 14, 4), FUNC("utif", 2, 14, 4), FUNC("gpio", 1, 14, 4), FUNC("spis", 0, 14, 4), }; -static struct rt2880_pmx_func gpio_grp_mt7628[] = { +static struct rt2880_pmx_func gpio_grp_mt76x8[] = { FUNC("pcie", 3, 11, 1), FUNC("refclk", 2, 11, 1), FUNC("gpio", 1, 11, 1), FUNC("gpio", 0, 11, 1), }; -static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = { +static struct rt2880_pmx_func p4led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 30, 1), FUNC("utif", 2, 30, 1), FUNC("gpio", 1, 30, 1), FUNC("p4led_kn", 0, 30, 1), }; -static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = { +static struct rt2880_pmx_func p3led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 31, 1), FUNC("utif", 2, 31, 1), FUNC("gpio", 1, 31, 1), FUNC("p3led_kn", 0, 31, 1), }; -static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = { +static struct rt2880_pmx_func p2led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 32, 1), FUNC("utif", 2, 32, 1), FUNC("gpio", 1, 32, 1), FUNC("p2led_kn", 0, 32, 1), }; -static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = { +static struct rt2880_pmx_func p1led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 33, 1), FUNC("utif", 2, 33, 1), FUNC("gpio", 1, 33, 1), FUNC("p1led_kn", 0, 33, 1), }; -static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = { +static struct rt2880_pmx_func p0led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 34, 1), FUNC("rsvd", 2, 34, 1), FUNC("gpio", 1, 34, 1), FUNC("p0led_kn", 0, 34, 1), }; -static struct rt2880_pmx_func wled_kn_grp_mt7628[] = { +static struct rt2880_pmx_func wled_kn_grp_mt76x8[] = { FUNC("rsvd", 3, 35, 1), FUNC("rsvd", 2, 35, 1), FUNC("gpio", 1, 35, 1), FUNC("wled_kn", 0, 35, 1), }; -static struct rt2880_pmx_func p4led_an_grp_mt7628[] = { +static struct rt2880_pmx_func p4led_an_grp_mt76x8[] = { FUNC("jtag", 3, 39, 1), FUNC("utif", 2, 39, 1), FUNC("gpio", 1, 39, 1), FUNC("p4led_an", 0, 39, 1), }; -static struct rt2880_pmx_func p3led_an_grp_mt7628[] = { +static struct rt2880_pmx_func p3led_an_grp_mt76x8[] = { FUNC("jtag", 3, 40, 1), FUNC("utif", 2, 40, 1), FUNC("gpio", 1, 40, 1), FUNC("p3led_an", 0, 40, 1), }; -static struct rt2880_pmx_func p2led_an_grp_mt7628[] = { +static struct rt2880_pmx_func p2led_an_grp_mt76x8[] = { FUNC("jtag", 3, 41, 1), FUNC("utif", 2, 41, 1), FUNC("gpio", 1, 41, 1), FUNC("p2led_an", 0, 41, 1), }; -static struct rt2880_pmx_func p1led_an_grp_mt7628[] = { +static struct rt2880_pmx_func p1led_an_grp_mt76x8[] = { FUNC("jtag", 3, 42, 1), FUNC("utif", 2, 42, 1), FUNC("gpio", 1, 42, 1), FUNC("p1led_an", 0, 42, 1), }; -static struct rt2880_pmx_func p0led_an_grp_mt7628[] = { +static struct rt2880_pmx_func p0led_an_grp_mt76x8[] = { FUNC("jtag", 3, 43, 1), FUNC("rsvd", 2, 43, 1), FUNC("gpio", 1, 43, 1), FUNC("p0led_an", 0, 43, 1), }; -static struct rt2880_pmx_func wled_an_grp_mt7628[] = { +static struct rt2880_pmx_func wled_an_grp_mt76x8[] = { FUNC("rsvd", 3, 44, 1), FUNC("rsvd", 2, 44, 1), FUNC("gpio", 1, 44, 1), FUNC("wled_an", 0, 44, 1), }; -#define MT7628_GPIO_MODE_MASK 0x3 - -#define MT7628_GPIO_MODE_P4LED_KN 58 -#define MT7628_GPIO_MODE_P3LED_KN 56 -#define MT7628_GPIO_MODE_P2LED_KN 54 -#define MT7628_GPIO_MODE_P1LED_KN 52 -#define MT7628_GPIO_MODE_P0LED_KN 50 -#define MT7628_GPIO_MODE_WLED_KN 48 -#define MT7628_GPIO_MODE_P4LED_AN 42 -#define MT7628_GPIO_MODE_P3LED_AN 40 -#define MT7628_GPIO_MODE_P2LED_AN 38 -#define MT7628_GPIO_MODE_P1LED_AN 36 -#define MT7628_GPIO_MODE_P0LED_AN 34 -#define MT7628_GPIO_MODE_WLED_AN 32 -#define MT7628_GPIO_MODE_PWM1 30 -#define MT7628_GPIO_MODE_PWM0 28 -#define MT7628_GPIO_MODE_UART2 26 -#define MT7628_GPIO_MODE_UART1 24 -#define MT7628_GPIO_MODE_I2C 20 -#define MT7628_GPIO_MODE_REFCLK 18 -#define MT7628_GPIO_MODE_PERST 16 -#define MT7628_GPIO_MODE_WDT 14 -#define MT7628_GPIO_MODE_SPI 12 -#define MT7628_GPIO_MODE_SDMODE 10 -#define MT7628_GPIO_MODE_UART0 8 -#define MT7628_GPIO_MODE_I2S 6 -#define MT7628_GPIO_MODE_CS1 4 -#define MT7628_GPIO_MODE_SPIS 2 -#define MT7628_GPIO_MODE_GPIO 0 - -static struct rt2880_pmx_group mt7628an_pinmux_data[] = { - GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_PWM1), - GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_PWM0), - GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_UART2), - GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_UART1), - GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_I2C), - GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK), - GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST), - GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT), - GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI), - GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_SDMODE), - GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_UART0), - GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_I2S), - GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_CS1), - GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_SPIS), - GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_GPIO), - GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_WLED_AN), - GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P0LED_AN), - GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P1LED_AN), - GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P2LED_AN), - GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P3LED_AN), - GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P4LED_AN), - GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_WLED_KN), - GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P0LED_KN), - GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P1LED_KN), - GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P2LED_KN), - GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P3LED_KN), - GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P4LED_KN), +#define MT76X8_GPIO_MODE_MASK 0x3 + +#define MT76X8_GPIO_MODE_P4LED_KN 58 +#define MT76X8_GPIO_MODE_P3LED_KN 56 +#define MT76X8_GPIO_MODE_P2LED_KN 54 +#define MT76X8_GPIO_MODE_P1LED_KN 52 +#define MT76X8_GPIO_MODE_P0LED_KN 50 +#define MT76X8_GPIO_MODE_WLED_KN 48 +#define MT76X8_GPIO_MODE_P4LED_AN 42 +#define MT76X8_GPIO_MODE_P3LED_AN 40 +#define MT76X8_GPIO_MODE_P2LED_AN 38 +#define MT76X8_GPIO_MODE_P1LED_AN 36 +#define MT76X8_GPIO_MODE_P0LED_AN 34 +#define MT76X8_GPIO_MODE_WLED_AN 32 +#define MT76X8_GPIO_MODE_PWM1 30 +#define MT76X8_GPIO_MODE_PWM0 28 +#define MT76X8_GPIO_MODE_UART2 26 +#define MT76X8_GPIO_MODE_UART1 24 +#define MT76X8_GPIO_MODE_I2C 20 +#define MT76X8_GPIO_MODE_REFCLK 18 +#define MT76X8_GPIO_MODE_PERST 16 +#define MT76X8_GPIO_MODE_WDT 14 +#define MT76X8_GPIO_MODE_SPI 12 +#define MT76X8_GPIO_MODE_SDMODE 10 +#define MT76X8_GPIO_MODE_UART0 8 +#define MT76X8_GPIO_MODE_I2S 6 +#define MT76X8_GPIO_MODE_CS1 4 +#define MT76X8_GPIO_MODE_SPIS 2 +#define MT76X8_GPIO_MODE_GPIO 0 + +static struct rt2880_pmx_group mt76x8_pinmux_data[] = { + GRP_G("pwm1", pwm1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_PWM1), + GRP_G("pwm0", pwm0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_PWM0), + GRP_G("uart2", uart2_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART2), + GRP_G("uart1", uart1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART1), + GRP_G("i2c", i2c_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_I2C), + GRP("refclk", refclk_grp_mt76x8, 1, MT76X8_GPIO_MODE_REFCLK), + GRP("perst", perst_grp_mt76x8, 1, MT76X8_GPIO_MODE_PERST), + GRP("wdt", wdt_grp_mt76x8, 1, MT76X8_GPIO_MODE_WDT), + GRP("spi", spi_grp_mt76x8, 1, MT76X8_GPIO_MODE_SPI), + GRP_G("sdmode", sd_mode_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_SDMODE), + GRP_G("uart0", uart0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART0), + GRP_G("i2s", i2s_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_I2S), + GRP_G("spi cs1", spi_cs1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_CS1), + GRP_G("spis", spis_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_SPIS), + GRP_G("gpio", gpio_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_GPIO), + GRP_G("wled_an", wled_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_WLED_AN), + GRP_G("p0led_an", p0led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P0LED_AN), + GRP_G("p1led_an", p1led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P1LED_AN), + GRP_G("p2led_an", p2led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P2LED_AN), + GRP_G("p3led_an", p3led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P3LED_AN), + GRP_G("p4led_an", p4led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P4LED_AN), + GRP_G("wled_kn", wled_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_WLED_KN), + GRP_G("p0led_kn", p0led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P0LED_KN), + GRP_G("p1led_kn", p1led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P1LED_KN), + GRP_G("p2led_kn", p2led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P2LED_KN), + GRP_G("p3led_kn", p3led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P3LED_KN), + GRP_G("p4led_kn", p4led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P4LED_KN), { 0 } }; static int mt7620_pinmux_probe(struct platform_device *pdev) { if (is_mt76x8()) - return rt2880_pinmux_init(pdev, mt7628an_pinmux_data); + return rt2880_pinmux_init(pdev, mt76x8_pinmux_data); else return rt2880_pinmux_init(pdev, mt7620a_pinmux_data); } From patchwork Thu Apr 14 17:39:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 561294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48D17C4321E for ; Thu, 14 Apr 2022 17:40:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343557AbiDNRm5 (ORCPT ); Thu, 14 Apr 2022 13:42:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230060AbiDNRmt (ORCPT ); Thu, 14 Apr 2022 13:42:49 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B064E2F6E; Thu, 14 Apr 2022 10:40:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649957989; cv=none; d=zohomail.com; s=zohoarc; b=EjljMtItKSJaWrg9fZxDK0sCIwHfqqqG7AXCOmWXmnjk/hAOhcjzNxWAjGPHEz8c4AIe+WI7c79FeEiqlYBsDgF+F8zOrW+h4zegE4daTFRK9EXHw+pWZ1XN0ROjZqF2QzByPeEn3+CBe7pSvWxfGFhLx2qD48y5uklIB3BaTEg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649957989; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=yuCyr1035FY3Fe9CfiQYy4Nc47tiOuiQaSE3O4Xz2rI=; b=j6/c5rBrMjmvfhhRw3mYxIGik2YcVAwxr+wgMxtSEeqDAJc2K2Cb4MLq/uia4zLbOdXe5QMzggbWhYADnfJ+0SMT5kSBLs1Vb59boxDbc3cxy9tF4ea/CnTkhsYIlct3mn4g7MQVDquoRo+JkeNLCOYOIfdebYfpCm+bDna4XN8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649957989; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=yuCyr1035FY3Fe9CfiQYy4Nc47tiOuiQaSE3O4Xz2rI=; b=MDaDd8XwDaKCquJDuAyjtg1KNPb0dHUaw8PsWVgHTg9IlP17667ph5r3jQZoxlxC OwutEGTXkL+fcTq2kbX/cfEWwWX2qSL151VIl3sERzchMgHqUf/VTYpbo6B09LSyd8w REGFG3Dt3ElHo22byMNphZi85BOMJAntfVswfjHM= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649957987182480.089884301271; Thu, 14 Apr 2022 10:39:47 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 02/14] pinctrl: ralink: rename pinctrl-rt2880 to pinctrl-ralink Date: Thu, 14 Apr 2022 20:39:04 +0300 Message-Id: <20220414173916.5552-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org pinctrl-rt2880.c and pinmux.h make up the Ralink pinctrl driver. Rename pinctrl-rt2880.c to pinctrl-ralink.c. Rename pinmux.h to pinctrl-ralink.h. Fix references to it. Rename functions that include "rt2880" to "ralink". Remove PINCTRL_RT2880 symbol and make the existing PINCTRL_RALINK symbol compile pinctrl-ralink.c. Change the bool to "Ralink pinctrl driver". Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/Kconfig | 16 ++-- drivers/pinctrl/ralink/Makefile | 2 +- drivers/pinctrl/ralink/pinctrl-mt7620.c | 92 +++++++++---------- drivers/pinctrl/ralink/pinctrl-mt7621.c | 30 +++--- .../{pinctrl-rt2880.c => pinctrl-ralink.c} | 90 +++++++++--------- .../ralink/{pinmux.h => pinctrl-ralink.h} | 16 ++-- drivers/pinctrl/ralink/pinctrl-rt288x.c | 20 ++-- drivers/pinctrl/ralink/pinctrl-rt305x.c | 44 ++++----- drivers/pinctrl/ralink/pinctrl-rt3883.c | 28 +++--- 9 files changed, 167 insertions(+), 171 deletions(-) rename drivers/pinctrl/ralink/{pinctrl-rt2880.c => pinctrl-ralink.c} (73%) rename drivers/pinctrl/ralink/{pinmux.h => pinctrl-ralink.h} (75%) diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index a76ee3deb8c3..d0f0a8f2b9b7 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -3,37 +3,33 @@ menu "Ralink pinctrl drivers" depends on RALINK config PINCTRL_RALINK - bool "Ralink pin control support" - default y if RALINK - -config PINCTRL_RT2880 - bool "RT2880 pinctrl driver for RALINK/Mediatek SOCs" + bool "Ralink pinctrl driver" select PINMUX select GENERIC_PINCONF config PINCTRL_MT7620 bool "mt7620 pinctrl driver for RALINK/Mediatek SOCs" depends on RALINK && SOC_MT7620 - select PINCTRL_RT2880 + select PINCTRL_RALINK config PINCTRL_MT7621 bool "mt7621 pinctrl driver for RALINK/Mediatek SOCs" depends on RALINK && SOC_MT7621 - select PINCTRL_RT2880 + select PINCTRL_RALINK config PINCTRL_RT288X bool "RT288X pinctrl driver for RALINK/Mediatek SOCs" depends on RALINK && SOC_RT288X - select PINCTRL_RT2880 + select PINCTRL_RALINK config PINCTRL_RT305X bool "RT305X pinctrl driver for RALINK/Mediatek SOCs" depends on RALINK && SOC_RT305X - select PINCTRL_RT2880 + select PINCTRL_RALINK config PINCTRL_RT3883 bool "RT3883 pinctrl driver for RALINK/Mediatek SOCs" depends on RALINK && SOC_RT3883 - select PINCTRL_RT2880 + select PINCTRL_RALINK endmenu diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile index a15610206ced..2c1323b74e96 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o +obj-$(CONFIG_PINCTRL_RALINK) += pinctrl-ralink.o obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index d3f9feec1f74..51b863d85c51 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -5,7 +5,7 @@ #include #include #include -#include "pinmux.h" +#include "pinctrl-ralink.h" #define MT7620_GPIO_MODE_UART0_SHIFT 2 #define MT7620_GPIO_MODE_UART0_MASK 0x7 @@ -54,20 +54,20 @@ #define MT7620_GPIO_MODE_EPHY 15 #define MT7620_GPIO_MODE_PA 20 -static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct rt2880_pmx_func mdio_grp[] = { +static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), }; -static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; -static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; -static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; -static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; -static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; -static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; -static struct rt2880_pmx_func uartf_grp[] = { +static struct ralink_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; +static struct ralink_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; +static struct ralink_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; +static struct ralink_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; +static struct ralink_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; +static struct ralink_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; +static struct ralink_pmx_func uartf_grp[] = { FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), @@ -76,20 +76,20 @@ static struct rt2880_pmx_func uartf_grp[] = { FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct rt2880_pmx_func wdt_grp[] = { +static struct ralink_pmx_func wdt_grp[] = { FUNC("wdt rst", 0, 17, 1), FUNC("wdt refclk", 0, 17, 1), }; -static struct rt2880_pmx_func pcie_rst_grp[] = { +static struct ralink_pmx_func pcie_rst_grp[] = { FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) }; -static struct rt2880_pmx_func nd_sd_grp[] = { +static struct ralink_pmx_func nd_sd_grp[] = { FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) }; -static struct rt2880_pmx_group mt7620a_pinmux_data[] = { +static struct ralink_pmx_group mt7620a_pinmux_data[] = { GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, MT7620_GPIO_MODE_UART0_SHIFT), @@ -112,166 +112,166 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = { { 0 } }; -static struct rt2880_pmx_func pwm1_grp_mt76x8[] = { +static struct ralink_pmx_func pwm1_grp_mt76x8[] = { FUNC("sdxc d6", 3, 19, 1), FUNC("utif", 2, 19, 1), FUNC("gpio", 1, 19, 1), FUNC("pwm1", 0, 19, 1), }; -static struct rt2880_pmx_func pwm0_grp_mt76x8[] = { +static struct ralink_pmx_func pwm0_grp_mt76x8[] = { FUNC("sdxc d7", 3, 18, 1), FUNC("utif", 2, 18, 1), FUNC("gpio", 1, 18, 1), FUNC("pwm0", 0, 18, 1), }; -static struct rt2880_pmx_func uart2_grp_mt76x8[] = { +static struct ralink_pmx_func uart2_grp_mt76x8[] = { FUNC("sdxc d5 d4", 3, 20, 2), FUNC("pwm", 2, 20, 2), FUNC("gpio", 1, 20, 2), FUNC("uart2", 0, 20, 2), }; -static struct rt2880_pmx_func uart1_grp_mt76x8[] = { +static struct ralink_pmx_func uart1_grp_mt76x8[] = { FUNC("sw_r", 3, 45, 2), FUNC("pwm", 2, 45, 2), FUNC("gpio", 1, 45, 2), FUNC("uart1", 0, 45, 2), }; -static struct rt2880_pmx_func i2c_grp_mt76x8[] = { +static struct ralink_pmx_func i2c_grp_mt76x8[] = { FUNC("-", 3, 4, 2), FUNC("debug", 2, 4, 2), FUNC("gpio", 1, 4, 2), FUNC("i2c", 0, 4, 2), }; -static struct rt2880_pmx_func refclk_grp_mt76x8[] = { FUNC("refclk", 0, 37, 1) }; -static struct rt2880_pmx_func perst_grp_mt76x8[] = { FUNC("perst", 0, 36, 1) }; -static struct rt2880_pmx_func wdt_grp_mt76x8[] = { FUNC("wdt", 0, 38, 1) }; -static struct rt2880_pmx_func spi_grp_mt76x8[] = { FUNC("spi", 0, 7, 4) }; +static struct ralink_pmx_func refclk_grp_mt76x8[] = { FUNC("refclk", 0, 37, 1) }; +static struct ralink_pmx_func perst_grp_mt76x8[] = { FUNC("perst", 0, 36, 1) }; +static struct ralink_pmx_func wdt_grp_mt76x8[] = { FUNC("wdt", 0, 38, 1) }; +static struct ralink_pmx_func spi_grp_mt76x8[] = { FUNC("spi", 0, 7, 4) }; -static struct rt2880_pmx_func sd_mode_grp_mt76x8[] = { +static struct ralink_pmx_func sd_mode_grp_mt76x8[] = { FUNC("jtag", 3, 22, 8), FUNC("utif", 2, 22, 8), FUNC("gpio", 1, 22, 8), FUNC("sdxc", 0, 22, 8), }; -static struct rt2880_pmx_func uart0_grp_mt76x8[] = { +static struct ralink_pmx_func uart0_grp_mt76x8[] = { FUNC("-", 3, 12, 2), FUNC("-", 2, 12, 2), FUNC("gpio", 1, 12, 2), FUNC("uart0", 0, 12, 2), }; -static struct rt2880_pmx_func i2s_grp_mt76x8[] = { +static struct ralink_pmx_func i2s_grp_mt76x8[] = { FUNC("antenna", 3, 0, 4), FUNC("pcm", 2, 0, 4), FUNC("gpio", 1, 0, 4), FUNC("i2s", 0, 0, 4), }; -static struct rt2880_pmx_func spi_cs1_grp_mt76x8[] = { +static struct ralink_pmx_func spi_cs1_grp_mt76x8[] = { FUNC("-", 3, 6, 1), FUNC("refclk", 2, 6, 1), FUNC("gpio", 1, 6, 1), FUNC("spi cs1", 0, 6, 1), }; -static struct rt2880_pmx_func spis_grp_mt76x8[] = { +static struct ralink_pmx_func spis_grp_mt76x8[] = { FUNC("pwm_uart2", 3, 14, 4), FUNC("utif", 2, 14, 4), FUNC("gpio", 1, 14, 4), FUNC("spis", 0, 14, 4), }; -static struct rt2880_pmx_func gpio_grp_mt76x8[] = { +static struct ralink_pmx_func gpio_grp_mt76x8[] = { FUNC("pcie", 3, 11, 1), FUNC("refclk", 2, 11, 1), FUNC("gpio", 1, 11, 1), FUNC("gpio", 0, 11, 1), }; -static struct rt2880_pmx_func p4led_kn_grp_mt76x8[] = { +static struct ralink_pmx_func p4led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 30, 1), FUNC("utif", 2, 30, 1), FUNC("gpio", 1, 30, 1), FUNC("p4led_kn", 0, 30, 1), }; -static struct rt2880_pmx_func p3led_kn_grp_mt76x8[] = { +static struct ralink_pmx_func p3led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 31, 1), FUNC("utif", 2, 31, 1), FUNC("gpio", 1, 31, 1), FUNC("p3led_kn", 0, 31, 1), }; -static struct rt2880_pmx_func p2led_kn_grp_mt76x8[] = { +static struct ralink_pmx_func p2led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 32, 1), FUNC("utif", 2, 32, 1), FUNC("gpio", 1, 32, 1), FUNC("p2led_kn", 0, 32, 1), }; -static struct rt2880_pmx_func p1led_kn_grp_mt76x8[] = { +static struct ralink_pmx_func p1led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 33, 1), FUNC("utif", 2, 33, 1), FUNC("gpio", 1, 33, 1), FUNC("p1led_kn", 0, 33, 1), }; -static struct rt2880_pmx_func p0led_kn_grp_mt76x8[] = { +static struct ralink_pmx_func p0led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 34, 1), FUNC("rsvd", 2, 34, 1), FUNC("gpio", 1, 34, 1), FUNC("p0led_kn", 0, 34, 1), }; -static struct rt2880_pmx_func wled_kn_grp_mt76x8[] = { +static struct ralink_pmx_func wled_kn_grp_mt76x8[] = { FUNC("rsvd", 3, 35, 1), FUNC("rsvd", 2, 35, 1), FUNC("gpio", 1, 35, 1), FUNC("wled_kn", 0, 35, 1), }; -static struct rt2880_pmx_func p4led_an_grp_mt76x8[] = { +static struct ralink_pmx_func p4led_an_grp_mt76x8[] = { FUNC("jtag", 3, 39, 1), FUNC("utif", 2, 39, 1), FUNC("gpio", 1, 39, 1), FUNC("p4led_an", 0, 39, 1), }; -static struct rt2880_pmx_func p3led_an_grp_mt76x8[] = { +static struct ralink_pmx_func p3led_an_grp_mt76x8[] = { FUNC("jtag", 3, 40, 1), FUNC("utif", 2, 40, 1), FUNC("gpio", 1, 40, 1), FUNC("p3led_an", 0, 40, 1), }; -static struct rt2880_pmx_func p2led_an_grp_mt76x8[] = { +static struct ralink_pmx_func p2led_an_grp_mt76x8[] = { FUNC("jtag", 3, 41, 1), FUNC("utif", 2, 41, 1), FUNC("gpio", 1, 41, 1), FUNC("p2led_an", 0, 41, 1), }; -static struct rt2880_pmx_func p1led_an_grp_mt76x8[] = { +static struct ralink_pmx_func p1led_an_grp_mt76x8[] = { FUNC("jtag", 3, 42, 1), FUNC("utif", 2, 42, 1), FUNC("gpio", 1, 42, 1), FUNC("p1led_an", 0, 42, 1), }; -static struct rt2880_pmx_func p0led_an_grp_mt76x8[] = { +static struct ralink_pmx_func p0led_an_grp_mt76x8[] = { FUNC("jtag", 3, 43, 1), FUNC("rsvd", 2, 43, 1), FUNC("gpio", 1, 43, 1), FUNC("p0led_an", 0, 43, 1), }; -static struct rt2880_pmx_func wled_an_grp_mt76x8[] = { +static struct ralink_pmx_func wled_an_grp_mt76x8[] = { FUNC("rsvd", 3, 44, 1), FUNC("rsvd", 2, 44, 1), FUNC("gpio", 1, 44, 1), @@ -308,7 +308,7 @@ static struct rt2880_pmx_func wled_an_grp_mt76x8[] = { #define MT76X8_GPIO_MODE_SPIS 2 #define MT76X8_GPIO_MODE_GPIO 0 -static struct rt2880_pmx_group mt76x8_pinmux_data[] = { +static struct ralink_pmx_group mt76x8_pinmux_data[] = { GRP_G("pwm1", pwm1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_PWM1), GRP_G("pwm0", pwm0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, @@ -365,9 +365,9 @@ static struct rt2880_pmx_group mt76x8_pinmux_data[] = { static int mt7620_pinmux_probe(struct platform_device *pdev) { if (is_mt76x8()) - return rt2880_pinmux_init(pdev, mt76x8_pinmux_data); + return ralink_pinmux_init(pdev, mt76x8_pinmux_data); else - return rt2880_pinmux_init(pdev, mt7620a_pinmux_data); + return ralink_pinmux_init(pdev, mt7620a_pinmux_data); } static const struct of_device_id mt7620_pinmux_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/ralink/pinctrl-mt7621.c index 7d96144c474e..14b89cb43d4c 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinmux.h" +#include "pinctrl-ralink.h" #define MT7621_GPIO_MODE_UART1 1 #define MT7621_GPIO_MODE_I2C 2 @@ -34,40 +34,40 @@ #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 #define MT7621_GPIO_MODE_SDHCI_GPIO 1 -static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; -static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; -static struct rt2880_pmx_func uart3_grp[] = { +static struct ralink_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; +static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; +static struct ralink_pmx_func uart3_grp[] = { FUNC("uart3", 0, 5, 4), FUNC("i2s", 2, 5, 4), FUNC("spdif3", 3, 5, 4), }; -static struct rt2880_pmx_func uart2_grp[] = { +static struct ralink_pmx_func uart2_grp[] = { FUNC("uart2", 0, 9, 4), FUNC("pcm", 2, 9, 4), FUNC("spdif2", 3, 9, 4), }; -static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; -static struct rt2880_pmx_func wdt_grp[] = { +static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; +static struct ralink_pmx_func wdt_grp[] = { FUNC("wdt rst", 0, 18, 1), FUNC("wdt refclk", 2, 18, 1), }; -static struct rt2880_pmx_func pcie_rst_grp[] = { +static struct ralink_pmx_func pcie_rst_grp[] = { FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) }; -static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; -static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; -static struct rt2880_pmx_func spi_grp[] = { +static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; +static struct ralink_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; +static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 34, 7), FUNC("nand1", 2, 34, 7), }; -static struct rt2880_pmx_func sdhci_grp[] = { +static struct ralink_pmx_func sdhci_grp[] = { FUNC("sdhci", 0, 41, 8), FUNC("nand2", 2, 41, 8), }; -static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; +static struct ralink_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; -static struct rt2880_pmx_group mt7621_pinmux_data[] = { +static struct ralink_pmx_group mt7621_pinmux_data[] = { GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, @@ -92,7 +92,7 @@ static struct rt2880_pmx_group mt7621_pinmux_data[] = { static int mt7621_pinmux_probe(struct platform_device *pdev) { - return rt2880_pinmux_init(pdev, mt7621_pinmux_data); + return ralink_pinmux_init(pdev, mt7621_pinmux_data); } static const struct of_device_id mt7621_pinmux_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/ralink/pinctrl-ralink.c similarity index 73% rename from drivers/pinctrl/ralink/pinctrl-rt2880.c rename to drivers/pinctrl/ralink/pinctrl-ralink.c index 96fc06d1b8b9..841f23f55c95 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/ralink/pinctrl-ralink.c @@ -19,23 +19,23 @@ #include #include -#include "pinmux.h" +#include "pinctrl-ralink.h" #include "../core.h" #include "../pinctrl-utils.h" #define SYSC_REG_GPIO_MODE 0x60 #define SYSC_REG_GPIO_MODE2 0x64 -struct rt2880_priv { +struct ralink_priv { struct device *dev; struct pinctrl_pin_desc *pads; struct pinctrl_desc *desc; - struct rt2880_pmx_func **func; + struct ralink_pmx_func **func; int func_count; - struct rt2880_pmx_group *groups; + struct ralink_pmx_group *groups; const char **group_names; int group_count; @@ -43,27 +43,27 @@ struct rt2880_priv { int max_pins; }; -static int rt2880_get_group_count(struct pinctrl_dev *pctrldev) +static int ralink_get_group_count(struct pinctrl_dev *pctrldev) { - struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); return p->group_count; } -static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev, +static const char *ralink_get_group_name(struct pinctrl_dev *pctrldev, unsigned int group) { - struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); return (group >= p->group_count) ? NULL : p->group_names[group]; } -static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev, +static int ralink_get_group_pins(struct pinctrl_dev *pctrldev, unsigned int group, const unsigned int **pins, unsigned int *num_pins) { - struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); if (group >= p->group_count) return -EINVAL; @@ -74,35 +74,35 @@ static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev, return 0; } -static const struct pinctrl_ops rt2880_pctrl_ops = { - .get_groups_count = rt2880_get_group_count, - .get_group_name = rt2880_get_group_name, - .get_group_pins = rt2880_get_group_pins, +static const struct pinctrl_ops ralink_pctrl_ops = { + .get_groups_count = ralink_get_group_count, + .get_group_name = ralink_get_group_name, + .get_group_pins = ralink_get_group_pins, .dt_node_to_map = pinconf_generic_dt_node_to_map_all, .dt_free_map = pinconf_generic_dt_free_map, }; -static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev) +static int ralink_pmx_func_count(struct pinctrl_dev *pctrldev) { - struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); return p->func_count; } -static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev, +static const char *ralink_pmx_func_name(struct pinctrl_dev *pctrldev, unsigned int func) { - struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); return p->func[func]->name; } -static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev, +static int ralink_pmx_group_get_groups(struct pinctrl_dev *pctrldev, unsigned int func, const char * const **groups, unsigned int * const num_groups) { - struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); if (p->func[func]->group_count == 1) *groups = &p->group_names[p->func[func]->groups[0]]; @@ -114,10 +114,10 @@ static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev, return 0; } -static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev, +static int ralink_pmx_group_enable(struct pinctrl_dev *pctrldev, unsigned int func, unsigned int group) { - struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); u32 mode = 0; u32 reg = SYSC_REG_GPIO_MODE; int i; @@ -158,11 +158,11 @@ static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev, return 0; } -static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, +static int ralink_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, struct pinctrl_gpio_range *range, unsigned int pin) { - struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); if (!p->gpio[pin]) { dev_err(p->dev, "pin %d is not set to gpio mux\n", pin); @@ -172,28 +172,28 @@ static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, return 0; } -static const struct pinmux_ops rt2880_pmx_group_ops = { - .get_functions_count = rt2880_pmx_func_count, - .get_function_name = rt2880_pmx_func_name, - .get_function_groups = rt2880_pmx_group_get_groups, - .set_mux = rt2880_pmx_group_enable, - .gpio_request_enable = rt2880_pmx_group_gpio_request_enable, +static const struct pinmux_ops ralink_pmx_group_ops = { + .get_functions_count = ralink_pmx_func_count, + .get_function_name = ralink_pmx_func_name, + .get_function_groups = ralink_pmx_group_get_groups, + .set_mux = ralink_pmx_group_enable, + .gpio_request_enable = ralink_pmx_group_gpio_request_enable, }; -static struct pinctrl_desc rt2880_pctrl_desc = { +static struct pinctrl_desc ralink_pctrl_desc = { .owner = THIS_MODULE, - .name = "rt2880-pinmux", - .pctlops = &rt2880_pctrl_ops, - .pmxops = &rt2880_pmx_group_ops, + .name = "ralink-pinmux", + .pctlops = &ralink_pctrl_ops, + .pmxops = &ralink_pmx_group_ops, }; -static struct rt2880_pmx_func gpio_func = { +static struct ralink_pmx_func gpio_func = { .name = "gpio", }; -static int rt2880_pinmux_index(struct rt2880_priv *p) +static int ralink_pinmux_index(struct ralink_priv *p) { - struct rt2880_pmx_group *mux = p->groups; + struct ralink_pmx_group *mux = p->groups; int i, j, c = 0; /* count the mux functions */ @@ -248,7 +248,7 @@ static int rt2880_pinmux_index(struct rt2880_priv *p) return 0; } -static int rt2880_pinmux_pins(struct rt2880_priv *p) +static int ralink_pinmux_pins(struct ralink_priv *p) { int i, j; @@ -311,10 +311,10 @@ static int rt2880_pinmux_pins(struct rt2880_priv *p) return 0; } -int rt2880_pinmux_init(struct platform_device *pdev, - struct rt2880_pmx_group *data) +int ralink_pinmux_init(struct platform_device *pdev, + struct ralink_pmx_group *data) { - struct rt2880_priv *p; + struct ralink_priv *p; struct pinctrl_dev *dev; int err; @@ -322,23 +322,23 @@ int rt2880_pinmux_init(struct platform_device *pdev, return -ENOTSUPP; /* setup the private data */ - p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL); + p = devm_kzalloc(&pdev->dev, sizeof(struct ralink_priv), GFP_KERNEL); if (!p) return -ENOMEM; p->dev = &pdev->dev; - p->desc = &rt2880_pctrl_desc; + p->desc = &ralink_pctrl_desc; p->groups = data; platform_set_drvdata(pdev, p); /* init the device */ - err = rt2880_pinmux_index(p); + err = ralink_pinmux_index(p); if (err) { dev_err(&pdev->dev, "failed to load index\n"); return err; } - err = rt2880_pinmux_pins(p); + err = ralink_pinmux_pins(p); if (err) { dev_err(&pdev->dev, "failed to load pins\n"); return err; diff --git a/drivers/pinctrl/ralink/pinmux.h b/drivers/pinctrl/ralink/pinctrl-ralink.h similarity index 75% rename from drivers/pinctrl/ralink/pinmux.h rename to drivers/pinctrl/ralink/pinctrl-ralink.h index 0046abe3bcc7..134969409585 100644 --- a/drivers/pinctrl/ralink/pinmux.h +++ b/drivers/pinctrl/ralink/pinctrl-ralink.h @@ -3,8 +3,8 @@ * Copyright (C) 2012 John Crispin */ -#ifndef _RT288X_PINMUX_H__ -#define _RT288X_PINMUX_H__ +#ifndef _PINCTRL_RALINK_H__ +#define _PINCTRL_RALINK_H__ #define FUNC(name, value, pin_first, pin_count) \ { name, value, pin_first, pin_count } @@ -19,9 +19,9 @@ .func = _func, .gpio = _gpio, \ .func_count = ARRAY_SIZE(_func) } -struct rt2880_pmx_group; +struct ralink_pmx_group; -struct rt2880_pmx_func { +struct ralink_pmx_func { const char *name; const char value; @@ -35,7 +35,7 @@ struct rt2880_pmx_func { int enabled; }; -struct rt2880_pmx_group { +struct ralink_pmx_group { const char *name; int enabled; @@ -43,11 +43,11 @@ struct rt2880_pmx_group { const char mask; const char gpio; - struct rt2880_pmx_func *func; + struct ralink_pmx_func *func; int func_count; }; -int rt2880_pinmux_init(struct platform_device *pdev, - struct rt2880_pmx_group *data); +int ralink_pinmux_init(struct platform_device *pdev, + struct ralink_pmx_group *data); #endif diff --git a/drivers/pinctrl/ralink/pinctrl-rt288x.c b/drivers/pinctrl/ralink/pinctrl-rt288x.c index 0744aebbace5..40c45140ff8a 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt288x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt288x.c @@ -4,7 +4,7 @@ #include #include #include -#include "pinmux.h" +#include "pinctrl-ralink.h" #define RT2880_GPIO_MODE_I2C BIT(0) #define RT2880_GPIO_MODE_UART0 BIT(1) @@ -15,15 +15,15 @@ #define RT2880_GPIO_MODE_SDRAM BIT(6) #define RT2880_GPIO_MODE_PCI BIT(7) -static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) }; -static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; -static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) }; +static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; +static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; +static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) }; +static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; +static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; +static struct ralink_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; +static struct ralink_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) }; -static struct rt2880_pmx_group rt2880_pinmux_data_act[] = { +static struct ralink_pmx_group rt2880_pinmux_data_act[] = { GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C), GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI), GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0), @@ -36,7 +36,7 @@ static struct rt2880_pmx_group rt2880_pinmux_data_act[] = { static int rt288x_pinmux_probe(struct platform_device *pdev) { - return rt2880_pinmux_init(pdev, rt2880_pinmux_data_act); + return ralink_pinmux_init(pdev, rt2880_pinmux_data_act); } static const struct of_device_id rt288x_pinmux_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c index 5d8fa156c003..25527ca1ccaa 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -5,7 +5,7 @@ #include #include #include -#include "pinmux.h" +#include "pinctrl-ralink.h" #define RT305X_GPIO_MODE_UART0_SHIFT 2 #define RT305X_GPIO_MODE_UART0_MASK 0x7 @@ -31,9 +31,9 @@ #define RT3352_GPIO_MODE_LNA 18 #define RT3352_GPIO_MODE_PA 20 -static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartf_func[] = { +static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; +static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; +static struct ralink_pmx_func uartf_func[] = { FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), @@ -42,28 +42,28 @@ static struct rt2880_pmx_func uartf_func[] = { FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) }; -static struct rt2880_pmx_func rt5350_cs1_func[] = { +static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; +static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; +static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; +static struct ralink_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) }; +static struct ralink_pmx_func rt5350_cs1_func[] = { FUNC("spi_cs1", 0, 27, 1), FUNC("wdg_cs1", 1, 27, 1), }; -static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; -static struct rt2880_pmx_func rt3352_rgmii_func[] = { +static struct ralink_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; +static struct ralink_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) }; -static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) }; -static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) }; -static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) }; -static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) }; -static struct rt2880_pmx_func rt3352_cs1_func[] = { +static struct ralink_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) }; +static struct ralink_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) }; +static struct ralink_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) }; +static struct ralink_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) }; +static struct ralink_pmx_func rt3352_cs1_func[] = { FUNC("spi_cs1", 0, 45, 1), FUNC("wdg_cs1", 1, 45, 1), }; -static struct rt2880_pmx_group rt3050_pinmux_data[] = { +static struct ralink_pmx_group rt3050_pinmux_data[] = { GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, @@ -76,7 +76,7 @@ static struct rt2880_pmx_group rt3050_pinmux_data[] = { { 0 } }; -static struct rt2880_pmx_group rt3352_pinmux_data[] = { +static struct ralink_pmx_group rt3352_pinmux_data[] = { GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, @@ -92,7 +92,7 @@ static struct rt2880_pmx_group rt3352_pinmux_data[] = { { 0 } }; -static struct rt2880_pmx_group rt5350_pinmux_data[] = { +static struct ralink_pmx_group rt5350_pinmux_data[] = { GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, @@ -107,11 +107,11 @@ static struct rt2880_pmx_group rt5350_pinmux_data[] = { static int rt305x_pinmux_probe(struct platform_device *pdev) { if (soc_is_rt5350()) - return rt2880_pinmux_init(pdev, rt5350_pinmux_data); + return ralink_pinmux_init(pdev, rt5350_pinmux_data); else if (soc_is_rt305x() || soc_is_rt3350()) - return rt2880_pinmux_init(pdev, rt3050_pinmux_data); + return ralink_pinmux_init(pdev, rt3050_pinmux_data); else if (soc_is_rt3352()) - return rt2880_pinmux_init(pdev, rt3352_pinmux_data); + return ralink_pinmux_init(pdev, rt3352_pinmux_data); else return -EINVAL; } diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/ralink/pinctrl-rt3883.c index 3e0e1b4caa64..0b8674dbe188 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinmux.h" +#include "pinctrl-ralink.h" #define RT3883_GPIO_MODE_UART0_SHIFT 2 #define RT3883_GPIO_MODE_UART0_MASK 0x7 @@ -39,9 +39,9 @@ #define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 #define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK) -static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartf_func[] = { +static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; +static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; +static struct ralink_pmx_func uartf_func[] = { FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8), @@ -50,21 +50,21 @@ static struct rt2880_pmx_func uartf_func[] = { FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) }; -static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) }; -static struct rt2880_pmx_func pci_func[] = { +static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; +static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; +static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; +static struct ralink_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) }; +static struct ralink_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) }; +static struct ralink_pmx_func pci_func[] = { FUNC("pci-dev", 0, 40, 32), FUNC("pci-host2", 1, 40, 32), FUNC("pci-host1", 2, 40, 32), FUNC("pci-fnc", 3, 40, 32) }; -static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) }; -static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) }; +static struct ralink_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) }; +static struct ralink_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) }; -static struct rt2880_pmx_group rt3883_pinmux_data[] = { +static struct ralink_pmx_group rt3883_pinmux_data[] = { GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C), GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI), GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK, @@ -83,7 +83,7 @@ static struct rt2880_pmx_group rt3883_pinmux_data[] = { static int rt3883_pinmux_probe(struct platform_device *pdev) { - return rt2880_pinmux_init(pdev, rt3883_pinmux_data); + return ralink_pinmux_init(pdev, rt3883_pinmux_data); } static const struct of_device_id rt3883_pinmux_match[] = { From patchwork Thu Apr 14 17:39:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 561298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A474C433F5 for ; Thu, 14 Apr 2022 17:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245286AbiDNRmt (ORCPT ); Thu, 14 Apr 2022 13:42:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343611AbiDNRmp (ORCPT ); Thu, 14 Apr 2022 13:42:45 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8AB7C6829; Thu, 14 Apr 2022 10:40:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649957993; cv=none; d=zohomail.com; s=zohoarc; b=SnHs9kqn+cC05uft/R9ElsEx7TdlePwsczIgteeT4q0fDdiUyfP5ZDpUTYD/pyu5fjM5FozIO3U4q+0EigbEfnY+z4xX5xcTOQNgKmvKHTNl8JHwVNw4tcyLm60Oky3HSqR89MPCDbXzHbk8LQAS/ufLOlESmXeJTGyaRQgOisY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649957993; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=cs1Rj7B0YCCL7XyUOed90CMuONsGpR5YbMUHqZpLxEo=; b=RKXTbzJIxhZdVR+337z4VS7f1yE0pLYUFl4yKKoQ04Kfy8Ku9Ua3N4ejfqQh787vE34qWMyXhFjQ0IlMIFA1JWvoFQlo0efxmWq1GtM+R3Ykt6/mk6eMALh4L7FhazoH33tf6faahADUczQdLmqIAGGDRKBjkR0v2OU9Dpplcuc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649957993; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=cs1Rj7B0YCCL7XyUOed90CMuONsGpR5YbMUHqZpLxEo=; b=UAvffek+M6eGU0tE0RGDyzICLk4eHOOKG1WJ5eUQ6mj4i3v5I+O6lFNdKL4EiPxf gXOlzgzCn85PcBHtu7T9eTSzfHGNgvUy/mBiKMCX/26w1ZMTN2YXy9MnFnX4M0XASNS BoCDyzzg6b+plyS5qy8/jWIPonJgTSyEx/0AmrtA= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649957991371587.6404861710015; Thu, 14 Apr 2022 10:39:51 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 03/14] pinctrl: ralink: rename pinmux functions to pinctrl Date: Thu, 14 Apr 2022 20:39:05 +0300 Message-Id: <20220414173916.5552-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Rename pinctrl related functions from "pinmux" to "pinctrl". Change driver name from "ralink-pinmux" to "ralink-pinctrl". Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 22 +++++++++++----------- drivers/pinctrl/ralink/pinctrl-mt7621.c | 20 ++++++++++---------- drivers/pinctrl/ralink/pinctrl-ralink.c | 14 +++++++------- drivers/pinctrl/ralink/pinctrl-ralink.h | 4 ++-- drivers/pinctrl/ralink/pinctrl-rt288x.c | 20 ++++++++++---------- drivers/pinctrl/ralink/pinctrl-rt305x.c | 24 ++++++++++++------------ drivers/pinctrl/ralink/pinctrl-rt3883.c | 20 ++++++++++---------- 7 files changed, 62 insertions(+), 62 deletions(-) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index 51b863d85c51..a790f3944314 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -362,30 +362,30 @@ static struct ralink_pmx_group mt76x8_pinmux_data[] = { { 0 } }; -static int mt7620_pinmux_probe(struct platform_device *pdev) +static int mt7620_pinctrl_probe(struct platform_device *pdev) { if (is_mt76x8()) - return ralink_pinmux_init(pdev, mt76x8_pinmux_data); + return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); else - return ralink_pinmux_init(pdev, mt7620a_pinmux_data); + return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); } -static const struct of_device_id mt7620_pinmux_match[] = { +static const struct of_device_id mt7620_pinctrl_match[] = { { .compatible = "ralink,rt2880-pinmux" }, {} }; -MODULE_DEVICE_TABLE(of, mt7620_pinmux_match); +MODULE_DEVICE_TABLE(of, mt7620_pinctrl_match); -static struct platform_driver mt7620_pinmux_driver = { - .probe = mt7620_pinmux_probe, +static struct platform_driver mt7620_pinctrl_driver = { + .probe = mt7620_pinctrl_probe, .driver = { .name = "rt2880-pinmux", - .of_match_table = mt7620_pinmux_match, + .of_match_table = mt7620_pinctrl_match, }, }; -static int __init mt7620_pinmux_init(void) +static int __init mt7620_pinctrl_init(void) { - return platform_driver_register(&mt7620_pinmux_driver); + return platform_driver_register(&mt7620_pinctrl_driver); } -core_initcall_sync(mt7620_pinmux_init); +core_initcall_sync(mt7620_pinctrl_init); diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/ralink/pinctrl-mt7621.c index 14b89cb43d4c..bad4f1a8cf3f 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -90,27 +90,27 @@ static struct ralink_pmx_group mt7621_pinmux_data[] = { { 0 } }; -static int mt7621_pinmux_probe(struct platform_device *pdev) +static int mt7621_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinmux_init(pdev, mt7621_pinmux_data); + return ralink_pinctrl_init(pdev, mt7621_pinmux_data); } -static const struct of_device_id mt7621_pinmux_match[] = { +static const struct of_device_id mt7621_pinctrl_match[] = { { .compatible = "ralink,rt2880-pinmux" }, {} }; -MODULE_DEVICE_TABLE(of, mt7621_pinmux_match); +MODULE_DEVICE_TABLE(of, mt7621_pinctrl_match); -static struct platform_driver mt7621_pinmux_driver = { - .probe = mt7621_pinmux_probe, +static struct platform_driver mt7621_pinctrl_driver = { + .probe = mt7621_pinctrl_probe, .driver = { .name = "rt2880-pinmux", - .of_match_table = mt7621_pinmux_match, + .of_match_table = mt7621_pinctrl_match, }, }; -static int __init mt7621_pinmux_init(void) +static int __init mt7621_pinctrl_init(void) { - return platform_driver_register(&mt7621_pinmux_driver); + return platform_driver_register(&mt7621_pinctrl_driver); } -core_initcall_sync(mt7621_pinmux_init); +core_initcall_sync(mt7621_pinctrl_init); diff --git a/drivers/pinctrl/ralink/pinctrl-ralink.c b/drivers/pinctrl/ralink/pinctrl-ralink.c index 841f23f55c95..63429a287434 100644 --- a/drivers/pinctrl/ralink/pinctrl-ralink.c +++ b/drivers/pinctrl/ralink/pinctrl-ralink.c @@ -182,7 +182,7 @@ static const struct pinmux_ops ralink_pmx_group_ops = { static struct pinctrl_desc ralink_pctrl_desc = { .owner = THIS_MODULE, - .name = "ralink-pinmux", + .name = "ralink-pinctrl", .pctlops = &ralink_pctrl_ops, .pmxops = &ralink_pmx_group_ops, }; @@ -191,7 +191,7 @@ static struct ralink_pmx_func gpio_func = { .name = "gpio", }; -static int ralink_pinmux_index(struct ralink_priv *p) +static int ralink_pinctrl_index(struct ralink_priv *p) { struct ralink_pmx_group *mux = p->groups; int i, j, c = 0; @@ -248,7 +248,7 @@ static int ralink_pinmux_index(struct ralink_priv *p) return 0; } -static int ralink_pinmux_pins(struct ralink_priv *p) +static int ralink_pinctrl_pins(struct ralink_priv *p) { int i, j; @@ -311,8 +311,8 @@ static int ralink_pinmux_pins(struct ralink_priv *p) return 0; } -int ralink_pinmux_init(struct platform_device *pdev, - struct ralink_pmx_group *data) +int ralink_pinctrl_init(struct platform_device *pdev, + struct ralink_pmx_group *data) { struct ralink_priv *p; struct pinctrl_dev *dev; @@ -332,13 +332,13 @@ int ralink_pinmux_init(struct platform_device *pdev, platform_set_drvdata(pdev, p); /* init the device */ - err = ralink_pinmux_index(p); + err = ralink_pinctrl_index(p); if (err) { dev_err(&pdev->dev, "failed to load index\n"); return err; } - err = ralink_pinmux_pins(p); + err = ralink_pinctrl_pins(p); if (err) { dev_err(&pdev->dev, "failed to load pins\n"); return err; diff --git a/drivers/pinctrl/ralink/pinctrl-ralink.h b/drivers/pinctrl/ralink/pinctrl-ralink.h index 134969409585..e6037be1e153 100644 --- a/drivers/pinctrl/ralink/pinctrl-ralink.h +++ b/drivers/pinctrl/ralink/pinctrl-ralink.h @@ -47,7 +47,7 @@ struct ralink_pmx_group { int func_count; }; -int ralink_pinmux_init(struct platform_device *pdev, - struct ralink_pmx_group *data); +int ralink_pinctrl_init(struct platform_device *pdev, + struct ralink_pmx_group *data); #endif diff --git a/drivers/pinctrl/ralink/pinctrl-rt288x.c b/drivers/pinctrl/ralink/pinctrl-rt288x.c index 40c45140ff8a..db5c09ed5601 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt288x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt288x.c @@ -34,27 +34,27 @@ static struct ralink_pmx_group rt2880_pinmux_data_act[] = { { 0 } }; -static int rt288x_pinmux_probe(struct platform_device *pdev) +static int rt288x_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinmux_init(pdev, rt2880_pinmux_data_act); + return ralink_pinctrl_init(pdev, rt2880_pinmux_data_act); } -static const struct of_device_id rt288x_pinmux_match[] = { +static const struct of_device_id rt288x_pinctrl_match[] = { { .compatible = "ralink,rt2880-pinmux" }, {} }; -MODULE_DEVICE_TABLE(of, rt288x_pinmux_match); +MODULE_DEVICE_TABLE(of, rt288x_pinctrl_match); -static struct platform_driver rt288x_pinmux_driver = { - .probe = rt288x_pinmux_probe, +static struct platform_driver rt288x_pinctrl_driver = { + .probe = rt288x_pinctrl_probe, .driver = { .name = "rt2880-pinmux", - .of_match_table = rt288x_pinmux_match, + .of_match_table = rt288x_pinctrl_match, }, }; -static int __init rt288x_pinmux_init(void) +static int __init rt288x_pinctrl_init(void) { - return platform_driver_register(&rt288x_pinmux_driver); + return platform_driver_register(&rt288x_pinctrl_driver); } -core_initcall_sync(rt288x_pinmux_init); +core_initcall_sync(rt288x_pinctrl_init); diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c index 25527ca1ccaa..b4765ca27cac 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -104,34 +104,34 @@ static struct ralink_pmx_group rt5350_pinmux_data[] = { { 0 } }; -static int rt305x_pinmux_probe(struct platform_device *pdev) +static int rt305x_pinctrl_probe(struct platform_device *pdev) { if (soc_is_rt5350()) - return ralink_pinmux_init(pdev, rt5350_pinmux_data); + return ralink_pinctrl_init(pdev, rt5350_pinmux_data); else if (soc_is_rt305x() || soc_is_rt3350()) - return ralink_pinmux_init(pdev, rt3050_pinmux_data); + return ralink_pinctrl_init(pdev, rt3050_pinmux_data); else if (soc_is_rt3352()) - return ralink_pinmux_init(pdev, rt3352_pinmux_data); + return ralink_pinctrl_init(pdev, rt3352_pinmux_data); else return -EINVAL; } -static const struct of_device_id rt305x_pinmux_match[] = { +static const struct of_device_id rt305x_pinctrl_match[] = { { .compatible = "ralink,rt2880-pinmux" }, {} }; -MODULE_DEVICE_TABLE(of, rt305x_pinmux_match); +MODULE_DEVICE_TABLE(of, rt305x_pinctrl_match); -static struct platform_driver rt305x_pinmux_driver = { - .probe = rt305x_pinmux_probe, +static struct platform_driver rt305x_pinctrl_driver = { + .probe = rt305x_pinctrl_probe, .driver = { .name = "rt2880-pinmux", - .of_match_table = rt305x_pinmux_match, + .of_match_table = rt305x_pinctrl_match, }, }; -static int __init rt305x_pinmux_init(void) +static int __init rt305x_pinctrl_init(void) { - return platform_driver_register(&rt305x_pinmux_driver); + return platform_driver_register(&rt305x_pinctrl_driver); } -core_initcall_sync(rt305x_pinmux_init); +core_initcall_sync(rt305x_pinctrl_init); diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/ralink/pinctrl-rt3883.c index 0b8674dbe188..b2e8151de226 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -81,27 +81,27 @@ static struct ralink_pmx_group rt3883_pinmux_data[] = { { 0 } }; -static int rt3883_pinmux_probe(struct platform_device *pdev) +static int rt3883_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinmux_init(pdev, rt3883_pinmux_data); + return ralink_pinctrl_init(pdev, rt3883_pinmux_data); } -static const struct of_device_id rt3883_pinmux_match[] = { +static const struct of_device_id rt3883_pinctrl_match[] = { { .compatible = "ralink,rt2880-pinmux" }, {} }; -MODULE_DEVICE_TABLE(of, rt3883_pinmux_match); +MODULE_DEVICE_TABLE(of, rt3883_pinctrl_match); -static struct platform_driver rt3883_pinmux_driver = { - .probe = rt3883_pinmux_probe, +static struct platform_driver rt3883_pinctrl_driver = { + .probe = rt3883_pinctrl_probe, .driver = { .name = "rt2880-pinmux", - .of_match_table = rt3883_pinmux_match, + .of_match_table = rt3883_pinctrl_match, }, }; -static int __init rt3883_pinmux_init(void) +static int __init rt3883_pinctrl_init(void) { - return platform_driver_register(&rt3883_pinmux_driver); + return platform_driver_register(&rt3883_pinctrl_driver); } -core_initcall_sync(rt3883_pinmux_init); +core_initcall_sync(rt3883_pinctrl_init); From patchwork Thu Apr 14 17:39:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 562693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D48BEC433FE for ; Thu, 14 Apr 2022 17:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245042AbiDNRmu (ORCPT ); Thu, 14 Apr 2022 13:42:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343561AbiDNRmn (ORCPT ); Thu, 14 Apr 2022 13:42:43 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FC16CBE65; Thu, 14 Apr 2022 10:40:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649957997; cv=none; d=zohomail.com; s=zohoarc; b=oIzejjUmH+pgkTOsabERwvBmbs3BGw89sc/ntUWoXz8EQHqw3wB+A/0xJoA/vCK2UumCnYEAcEbao3swgKDnHG2xhOrXIA5RHK+ZI2ORSeRd86JU/L0Ag3d1HnPzGF0fsqnEzuAiCpa6kqAm7evUKxo7aIH6Bc9xGJEe6/Ki4uc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649957997; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=8miZcTOH0rWiGd+6wcqTTPeMsb9x57xBzzuSkUegm3c=; b=f79w8zfBqO6/kTe//cMnyz+lzO4KluiRk5WvpHKQK7PxQ4se+tOPdw7tDyE1KAlJ0XsjUTVpQJh1YBFeY6PyJiDUs5qRE9lSKHZ9YAt7OROctDH/Qi+rYrVyPyaYWgbqT1BPcko/LSI/02GzWM3kKXgH5Sex/4694n5z3TDzSgc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649957997; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=8miZcTOH0rWiGd+6wcqTTPeMsb9x57xBzzuSkUegm3c=; b=WTi5pB8hmR93vNGwPpg59Oodh1g6+G1UJtC02v/QcxtfkxPcMW6EDTc8RGY1blxm bF6BRnuZW54/dn6HYom/HLyqpLvlHak3qs96RfDOkaBXxKpGPTaatR6adqEkbyM4FPD 2cnE3CHdO/m/Ht/DP8adhgEXu2H7+mKFJn3S2zu8= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649957995568600.5755065695765; Thu, 14 Apr 2022 10:39:55 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 04/14] pinctrl: ralink: rename pinctrl-rt288x to pinctrl-rt2880 Date: Thu, 14 Apr 2022 20:39:06 +0300 Message-Id: <20220414173916.5552-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Rename "pinctrl-rt288x.c" to "pinctrl-rt2880.c" as this is the Ralink RT2880 pinctrl subdriver. Rename PINCTRL_RT288X symbol to PINCTRL_RT2880. Rename functions that include "rt288x" to "rt2880". Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/Kconfig | 4 ++-- drivers/pinctrl/ralink/Makefile | 2 +- .../{pinctrl-rt288x.c => pinctrl-rt2880.c} | 18 +++++++++--------- 3 files changed, 12 insertions(+), 12 deletions(-) rename drivers/pinctrl/ralink/{pinctrl-rt288x.c => pinctrl-rt2880.c} (78%) diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index d0f0a8f2b9b7..aa82acfae827 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -17,8 +17,8 @@ config PINCTRL_MT7621 depends on RALINK && SOC_MT7621 select PINCTRL_RALINK -config PINCTRL_RT288X - bool "RT288X pinctrl driver for RALINK/Mediatek SOCs" +config PINCTRL_RT2880 + bool "RT2880 pinctrl driver for RALINK/Mediatek SOCs" depends on RALINK && SOC_RT288X select PINCTRL_RALINK diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile index 2c1323b74e96..0ebbe552526d 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -3,6 +3,6 @@ obj-$(CONFIG_PINCTRL_RALINK) += pinctrl-ralink.o obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o -obj-$(CONFIG_PINCTRL_RT288X) += pinctrl-rt288x.o +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o diff --git a/drivers/pinctrl/ralink/pinctrl-rt288x.c b/drivers/pinctrl/ralink/pinctrl-rt2880.c similarity index 78% rename from drivers/pinctrl/ralink/pinctrl-rt288x.c rename to drivers/pinctrl/ralink/pinctrl-rt2880.c index db5c09ed5601..9c5e828af43a 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt288x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c @@ -34,27 +34,27 @@ static struct ralink_pmx_group rt2880_pinmux_data_act[] = { { 0 } }; -static int rt288x_pinctrl_probe(struct platform_device *pdev) +static int rt2880_pinctrl_probe(struct platform_device *pdev) { return ralink_pinctrl_init(pdev, rt2880_pinmux_data_act); } -static const struct of_device_id rt288x_pinctrl_match[] = { +static const struct of_device_id rt2880_pinctrl_match[] = { { .compatible = "ralink,rt2880-pinmux" }, {} }; -MODULE_DEVICE_TABLE(of, rt288x_pinctrl_match); +MODULE_DEVICE_TABLE(of, rt2880_pinctrl_match); -static struct platform_driver rt288x_pinctrl_driver = { - .probe = rt288x_pinctrl_probe, +static struct platform_driver rt2880_pinctrl_driver = { + .probe = rt2880_pinctrl_probe, .driver = { .name = "rt2880-pinmux", - .of_match_table = rt288x_pinctrl_match, + .of_match_table = rt2880_pinctrl_match, }, }; -static int __init rt288x_pinctrl_init(void) +static int __init rt2880_pinctrl_init(void) { - return platform_driver_register(&rt288x_pinctrl_driver); + return platform_driver_register(&rt2880_pinctrl_driver); } -core_initcall_sync(rt288x_pinctrl_init); +core_initcall_sync(rt2880_pinctrl_init); From patchwork Thu Apr 14 17:39:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 561295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 883BCC43217 for ; Thu, 14 Apr 2022 17:40:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343514AbiDNRmz (ORCPT ); Thu, 14 Apr 2022 13:42:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343638AbiDNRmr (ORCPT ); Thu, 14 Apr 2022 13:42:47 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 566BAD4C98; Thu, 14 Apr 2022 10:40:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649958001; cv=none; d=zohomail.com; s=zohoarc; b=fow4K4nFieAcLysgAMq2CbHwVRdeVvC6YM4/2UMGpFuMYRWI5xOGrUv2EhQuP6o0EX4Uyk9KImJe993Mca0Ol2pc1y/yVdp69mqhoHTnTzdPAM/OfjLqSa/Bf3oMwz2I0z9EuiGy17FuF60SKvjvIdQqNqZ3SVE68xGV5adcchI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649958001; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=yeFRrDWWexujKMer0dgqXI9XuDnePR0CEQKx8LKK0zU=; b=LElQ+lhCajIyyCePEWKOGsotpaxqLiwyFopdSjXactQXXSeFGHdhlBwyzDbRqifUn6S0U+7+ULpk4fz8/8wQ1qAZT7DT5K/0PEGNA+s7Ol56mTlcD5USU9kf48idr3BVwmtNSypbSAhXbOm+/oYx1qMzXJP9PeyTWDcjWbF6iV8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649958001; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=yeFRrDWWexujKMer0dgqXI9XuDnePR0CEQKx8LKK0zU=; b=JXAYeJ8MCsGfZIZcbzFIJURuMZzjH6L3w8Vm5hT6QnjZYINs+qUoTl+I37E8zkRU uXK596tUlTmwAHLDlJdE33u8fxg7psZshkJ5UICZBl3W1rdD9zpbFjcQrldxaFXxFi8 bm10S9iWV8Yv1yoXxId/PoKa3SMIeT3/West1jrc= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649957999902450.1836611287223; Thu, 14 Apr 2022 10:39:59 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 05/14] pinctrl: ralink: rename variable names for functions on MT7620 and MT7621 Date: Thu, 14 Apr 2022 20:39:07 +0300 Message-Id: <20220414173916.5552-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Variables for functions include "grp" on the Ralink MT7620 and MT7621 subdrivers. Rename them to "func" instead as they define the functions for the pin groups. Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 164 ++++++++++++------------ drivers/pinctrl/ralink/pinctrl-mt7621.c | 48 +++---- 2 files changed, 106 insertions(+), 106 deletions(-) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index a790f3944314..fde269c68a7b 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -54,20 +54,20 @@ #define MT7620_GPIO_MODE_EPHY 15 #define MT7620_GPIO_MODE_PA 20 -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct ralink_pmx_func mdio_grp[] = { +static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; +static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; +static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; +static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), }; -static struct ralink_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; -static struct ralink_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; -static struct ralink_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; -static struct ralink_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; -static struct ralink_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; -static struct ralink_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; -static struct ralink_pmx_func uartf_grp[] = { +static struct ralink_pmx_func rgmii1_func[] = { FUNC("rgmii1", 0, 24, 12) }; +static struct ralink_pmx_func refclk_func[] = { FUNC("spi refclk", 0, 37, 3) }; +static struct ralink_pmx_func ephy_func[] = { FUNC("ephy", 0, 40, 5) }; +static struct ralink_pmx_func rgmii2_func[] = { FUNC("rgmii2", 0, 60, 12) }; +static struct ralink_pmx_func wled_func[] = { FUNC("wled", 0, 72, 1) }; +static struct ralink_pmx_func pa_func[] = { FUNC("pa", 0, 18, 4) }; +static struct ralink_pmx_func uartf_func[] = { FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), @@ -76,202 +76,202 @@ static struct ralink_pmx_func uartf_grp[] = { FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func wdt_grp[] = { +static struct ralink_pmx_func wdt_func[] = { FUNC("wdt rst", 0, 17, 1), FUNC("wdt refclk", 0, 17, 1), }; -static struct ralink_pmx_func pcie_rst_grp[] = { +static struct ralink_pmx_func pcie_rst_func[] = { FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) }; -static struct ralink_pmx_func nd_sd_grp[] = { +static struct ralink_pmx_func nd_sd_func[] = { FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) }; static struct ralink_pmx_group mt7620a_pinmux_data[] = { - GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), - GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, + GRP("i2c", i2c_func, 1, MT7620_GPIO_MODE_I2C), + GRP("uartf", uartf_func, MT7620_GPIO_MODE_UART0_MASK, MT7620_GPIO_MODE_UART0_SHIFT), - GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI), - GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), - GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, + GRP("spi", spi_func, 1, MT7620_GPIO_MODE_SPI), + GRP("uartlite", uartlite_func, 1, MT7620_GPIO_MODE_UART1), + GRP_G("wdt", wdt_func, MT7620_GPIO_MODE_WDT_MASK, MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), - GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK, + GRP_G("mdio", mdio_func, MT7620_GPIO_MODE_MDIO_MASK, MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT), - GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), - GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), - GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, + GRP("rgmii1", rgmii1_func, 1, MT7620_GPIO_MODE_RGMII1), + GRP("spi refclk", refclk_func, 1, MT7620_GPIO_MODE_SPI_REF_CLK), + GRP_G("pcie", pcie_rst_func, MT7620_GPIO_MODE_PCIE_MASK, MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT), - GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK, + GRP_G("nd_sd", nd_sd_func, MT7620_GPIO_MODE_ND_SD_MASK, MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT), - GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2), - GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED), - GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY), - GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA), + GRP("rgmii2", rgmii2_func, 1, MT7620_GPIO_MODE_RGMII2), + GRP("wled", wled_func, 1, MT7620_GPIO_MODE_WLED), + GRP("ephy", ephy_func, 1, MT7620_GPIO_MODE_EPHY), + GRP("pa", pa_func, 1, MT7620_GPIO_MODE_PA), { 0 } }; -static struct ralink_pmx_func pwm1_grp_mt76x8[] = { +static struct ralink_pmx_func pwm1_func_mt76x8[] = { FUNC("sdxc d6", 3, 19, 1), FUNC("utif", 2, 19, 1), FUNC("gpio", 1, 19, 1), FUNC("pwm1", 0, 19, 1), }; -static struct ralink_pmx_func pwm0_grp_mt76x8[] = { +static struct ralink_pmx_func pwm0_func_mt76x8[] = { FUNC("sdxc d7", 3, 18, 1), FUNC("utif", 2, 18, 1), FUNC("gpio", 1, 18, 1), FUNC("pwm0", 0, 18, 1), }; -static struct ralink_pmx_func uart2_grp_mt76x8[] = { +static struct ralink_pmx_func uart2_func_mt76x8[] = { FUNC("sdxc d5 d4", 3, 20, 2), FUNC("pwm", 2, 20, 2), FUNC("gpio", 1, 20, 2), FUNC("uart2", 0, 20, 2), }; -static struct ralink_pmx_func uart1_grp_mt76x8[] = { +static struct ralink_pmx_func uart1_func_mt76x8[] = { FUNC("sw_r", 3, 45, 2), FUNC("pwm", 2, 45, 2), FUNC("gpio", 1, 45, 2), FUNC("uart1", 0, 45, 2), }; -static struct ralink_pmx_func i2c_grp_mt76x8[] = { +static struct ralink_pmx_func i2c_func_mt76x8[] = { FUNC("-", 3, 4, 2), FUNC("debug", 2, 4, 2), FUNC("gpio", 1, 4, 2), FUNC("i2c", 0, 4, 2), }; -static struct ralink_pmx_func refclk_grp_mt76x8[] = { FUNC("refclk", 0, 37, 1) }; -static struct ralink_pmx_func perst_grp_mt76x8[] = { FUNC("perst", 0, 36, 1) }; -static struct ralink_pmx_func wdt_grp_mt76x8[] = { FUNC("wdt", 0, 38, 1) }; -static struct ralink_pmx_func spi_grp_mt76x8[] = { FUNC("spi", 0, 7, 4) }; +static struct ralink_pmx_func refclk_func_mt76x8[] = { FUNC("refclk", 0, 37, 1) }; +static struct ralink_pmx_func perst_func_mt76x8[] = { FUNC("perst", 0, 36, 1) }; +static struct ralink_pmx_func wdt_func_mt76x8[] = { FUNC("wdt", 0, 38, 1) }; +static struct ralink_pmx_func spi_func_mt76x8[] = { FUNC("spi", 0, 7, 4) }; -static struct ralink_pmx_func sd_mode_grp_mt76x8[] = { +static struct ralink_pmx_func sd_mode_func_mt76x8[] = { FUNC("jtag", 3, 22, 8), FUNC("utif", 2, 22, 8), FUNC("gpio", 1, 22, 8), FUNC("sdxc", 0, 22, 8), }; -static struct ralink_pmx_func uart0_grp_mt76x8[] = { +static struct ralink_pmx_func uart0_func_mt76x8[] = { FUNC("-", 3, 12, 2), FUNC("-", 2, 12, 2), FUNC("gpio", 1, 12, 2), FUNC("uart0", 0, 12, 2), }; -static struct ralink_pmx_func i2s_grp_mt76x8[] = { +static struct ralink_pmx_func i2s_func_mt76x8[] = { FUNC("antenna", 3, 0, 4), FUNC("pcm", 2, 0, 4), FUNC("gpio", 1, 0, 4), FUNC("i2s", 0, 0, 4), }; -static struct ralink_pmx_func spi_cs1_grp_mt76x8[] = { +static struct ralink_pmx_func spi_cs1_func_mt76x8[] = { FUNC("-", 3, 6, 1), FUNC("refclk", 2, 6, 1), FUNC("gpio", 1, 6, 1), FUNC("spi cs1", 0, 6, 1), }; -static struct ralink_pmx_func spis_grp_mt76x8[] = { +static struct ralink_pmx_func spis_func_mt76x8[] = { FUNC("pwm_uart2", 3, 14, 4), FUNC("utif", 2, 14, 4), FUNC("gpio", 1, 14, 4), FUNC("spis", 0, 14, 4), }; -static struct ralink_pmx_func gpio_grp_mt76x8[] = { +static struct ralink_pmx_func gpio_func_mt76x8[] = { FUNC("pcie", 3, 11, 1), FUNC("refclk", 2, 11, 1), FUNC("gpio", 1, 11, 1), FUNC("gpio", 0, 11, 1), }; -static struct ralink_pmx_func p4led_kn_grp_mt76x8[] = { +static struct ralink_pmx_func p4led_kn_func_mt76x8[] = { FUNC("jtag", 3, 30, 1), FUNC("utif", 2, 30, 1), FUNC("gpio", 1, 30, 1), FUNC("p4led_kn", 0, 30, 1), }; -static struct ralink_pmx_func p3led_kn_grp_mt76x8[] = { +static struct ralink_pmx_func p3led_kn_func_mt76x8[] = { FUNC("jtag", 3, 31, 1), FUNC("utif", 2, 31, 1), FUNC("gpio", 1, 31, 1), FUNC("p3led_kn", 0, 31, 1), }; -static struct ralink_pmx_func p2led_kn_grp_mt76x8[] = { +static struct ralink_pmx_func p2led_kn_func_mt76x8[] = { FUNC("jtag", 3, 32, 1), FUNC("utif", 2, 32, 1), FUNC("gpio", 1, 32, 1), FUNC("p2led_kn", 0, 32, 1), }; -static struct ralink_pmx_func p1led_kn_grp_mt76x8[] = { +static struct ralink_pmx_func p1led_kn_func_mt76x8[] = { FUNC("jtag", 3, 33, 1), FUNC("utif", 2, 33, 1), FUNC("gpio", 1, 33, 1), FUNC("p1led_kn", 0, 33, 1), }; -static struct ralink_pmx_func p0led_kn_grp_mt76x8[] = { +static struct ralink_pmx_func p0led_kn_func_mt76x8[] = { FUNC("jtag", 3, 34, 1), FUNC("rsvd", 2, 34, 1), FUNC("gpio", 1, 34, 1), FUNC("p0led_kn", 0, 34, 1), }; -static struct ralink_pmx_func wled_kn_grp_mt76x8[] = { +static struct ralink_pmx_func wled_kn_func_mt76x8[] = { FUNC("rsvd", 3, 35, 1), FUNC("rsvd", 2, 35, 1), FUNC("gpio", 1, 35, 1), FUNC("wled_kn", 0, 35, 1), }; -static struct ralink_pmx_func p4led_an_grp_mt76x8[] = { +static struct ralink_pmx_func p4led_an_func_mt76x8[] = { FUNC("jtag", 3, 39, 1), FUNC("utif", 2, 39, 1), FUNC("gpio", 1, 39, 1), FUNC("p4led_an", 0, 39, 1), }; -static struct ralink_pmx_func p3led_an_grp_mt76x8[] = { +static struct ralink_pmx_func p3led_an_func_mt76x8[] = { FUNC("jtag", 3, 40, 1), FUNC("utif", 2, 40, 1), FUNC("gpio", 1, 40, 1), FUNC("p3led_an", 0, 40, 1), }; -static struct ralink_pmx_func p2led_an_grp_mt76x8[] = { +static struct ralink_pmx_func p2led_an_func_mt76x8[] = { FUNC("jtag", 3, 41, 1), FUNC("utif", 2, 41, 1), FUNC("gpio", 1, 41, 1), FUNC("p2led_an", 0, 41, 1), }; -static struct ralink_pmx_func p1led_an_grp_mt76x8[] = { +static struct ralink_pmx_func p1led_an_func_mt76x8[] = { FUNC("jtag", 3, 42, 1), FUNC("utif", 2, 42, 1), FUNC("gpio", 1, 42, 1), FUNC("p1led_an", 0, 42, 1), }; -static struct ralink_pmx_func p0led_an_grp_mt76x8[] = { +static struct ralink_pmx_func p0led_an_func_mt76x8[] = { FUNC("jtag", 3, 43, 1), FUNC("rsvd", 2, 43, 1), FUNC("gpio", 1, 43, 1), FUNC("p0led_an", 0, 43, 1), }; -static struct ralink_pmx_func wled_an_grp_mt76x8[] = { +static struct ralink_pmx_func wled_an_func_mt76x8[] = { FUNC("rsvd", 3, 44, 1), FUNC("rsvd", 2, 44, 1), FUNC("gpio", 1, 44, 1), @@ -309,55 +309,55 @@ static struct ralink_pmx_func wled_an_grp_mt76x8[] = { #define MT76X8_GPIO_MODE_GPIO 0 static struct ralink_pmx_group mt76x8_pinmux_data[] = { - GRP_G("pwm1", pwm1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("pwm1", pwm1_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_PWM1), - GRP_G("pwm0", pwm0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("pwm0", pwm0_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_PWM0), - GRP_G("uart2", uart2_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("uart2", uart2_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_UART2), - GRP_G("uart1", uart1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("uart1", uart1_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_UART1), - GRP_G("i2c", i2c_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("i2c", i2c_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_I2C), - GRP("refclk", refclk_grp_mt76x8, 1, MT76X8_GPIO_MODE_REFCLK), - GRP("perst", perst_grp_mt76x8, 1, MT76X8_GPIO_MODE_PERST), - GRP("wdt", wdt_grp_mt76x8, 1, MT76X8_GPIO_MODE_WDT), - GRP("spi", spi_grp_mt76x8, 1, MT76X8_GPIO_MODE_SPI), - GRP_G("sdmode", sd_mode_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP("refclk", refclk_func_mt76x8, 1, MT76X8_GPIO_MODE_REFCLK), + GRP("perst", perst_func_mt76x8, 1, MT76X8_GPIO_MODE_PERST), + GRP("wdt", wdt_func_mt76x8, 1, MT76X8_GPIO_MODE_WDT), + GRP("spi", spi_func_mt76x8, 1, MT76X8_GPIO_MODE_SPI), + GRP_G("sdmode", sd_mode_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_SDMODE), - GRP_G("uart0", uart0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("uart0", uart0_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_UART0), - GRP_G("i2s", i2s_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("i2s", i2s_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_I2S), - GRP_G("spi cs1", spi_cs1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("spi cs1", spi_cs1_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_CS1), - GRP_G("spis", spis_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("spis", spis_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_SPIS), - GRP_G("gpio", gpio_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("gpio", gpio_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_GPIO), - GRP_G("wled_an", wled_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("wled_an", wled_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_WLED_AN), - GRP_G("p0led_an", p0led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p0led_an", p0led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P0LED_AN), - GRP_G("p1led_an", p1led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p1led_an", p1led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P1LED_AN), - GRP_G("p2led_an", p2led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p2led_an", p2led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P2LED_AN), - GRP_G("p3led_an", p3led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p3led_an", p3led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P3LED_AN), - GRP_G("p4led_an", p4led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p4led_an", p4led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P4LED_AN), - GRP_G("wled_kn", wled_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("wled_kn", wled_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_WLED_KN), - GRP_G("p0led_kn", p0led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p0led_kn", p0led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P0LED_KN), - GRP_G("p1led_kn", p1led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p1led_kn", p1led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P1LED_KN), - GRP_G("p2led_kn", p2led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p2led_kn", p2led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P2LED_KN), - GRP_G("p3led_kn", p3led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p3led_kn", p3led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P3LED_KN), - GRP_G("p4led_kn", p4led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p4led_kn", p4led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P4LED_KN), { 0 } }; diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/ralink/pinctrl-mt7621.c index bad4f1a8cf3f..1470250ca3b7 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -34,59 +34,59 @@ #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 #define MT7621_GPIO_MODE_SDHCI_GPIO 1 -static struct ralink_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; -static struct ralink_pmx_func uart3_grp[] = { +static struct ralink_pmx_func uart1_func[] = { FUNC("uart1", 0, 1, 2) }; +static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 3, 2) }; +static struct ralink_pmx_func uart3_func[] = { FUNC("uart3", 0, 5, 4), FUNC("i2s", 2, 5, 4), FUNC("spdif3", 3, 5, 4), }; -static struct ralink_pmx_func uart2_grp[] = { +static struct ralink_pmx_func uart2_func[] = { FUNC("uart2", 0, 9, 4), FUNC("pcm", 2, 9, 4), FUNC("spdif2", 3, 9, 4), }; -static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; -static struct ralink_pmx_func wdt_grp[] = { +static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 13, 5) }; +static struct ralink_pmx_func wdt_func[] = { FUNC("wdt rst", 0, 18, 1), FUNC("wdt refclk", 2, 18, 1), }; -static struct ralink_pmx_func pcie_rst_grp[] = { +static struct ralink_pmx_func pcie_rst_func[] = { FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) }; -static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; -static struct ralink_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; -static struct ralink_pmx_func spi_grp[] = { +static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 20, 2) }; +static struct ralink_pmx_func rgmii2_func[] = { FUNC("rgmii2", 0, 22, 12) }; +static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 34, 7), FUNC("nand1", 2, 34, 7), }; -static struct ralink_pmx_func sdhci_grp[] = { +static struct ralink_pmx_func sdhci_func[] = { FUNC("sdhci", 0, 41, 8), FUNC("nand2", 2, 41, 8), }; -static struct ralink_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; +static struct ralink_pmx_func rgmii1_func[] = { FUNC("rgmii1", 0, 49, 12) }; static struct ralink_pmx_group mt7621_pinmux_data[] = { - GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), - GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), - GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, + GRP("uart1", uart1_func, 1, MT7621_GPIO_MODE_UART1), + GRP("i2c", i2c_func, 1, MT7621_GPIO_MODE_I2C), + GRP_G("uart3", uart3_func, MT7621_GPIO_MODE_UART3_MASK, MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT), - GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK, + GRP_G("uart2", uart2_func, MT7621_GPIO_MODE_UART2_MASK, MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT), - GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG), - GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK, + GRP("jtag", jtag_func, 1, MT7621_GPIO_MODE_JTAG), + GRP_G("wdt", wdt_func, MT7621_GPIO_MODE_WDT_MASK, MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT), - GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK, + GRP_G("pcie", pcie_rst_func, MT7621_GPIO_MODE_PCIE_MASK, MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT), - GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK, + GRP_G("mdio", mdio_func, MT7621_GPIO_MODE_MDIO_MASK, MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT), - GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2), - GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK, + GRP("rgmii2", rgmii2_func, 1, MT7621_GPIO_MODE_RGMII2), + GRP_G("spi", spi_func, MT7621_GPIO_MODE_SPI_MASK, MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT), - GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK, + GRP_G("sdhci", sdhci_func, MT7621_GPIO_MODE_SDHCI_MASK, MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT), - GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1), + GRP("rgmii1", rgmii1_func, 1, MT7621_GPIO_MODE_RGMII1), { 0 } }; From patchwork Thu Apr 14 17:39:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 561297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D61FEC4167B for ; Thu, 14 Apr 2022 17:40:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242953AbiDNRmw (ORCPT ); Thu, 14 Apr 2022 13:42:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343591AbiDNRmo (ORCPT ); Thu, 14 Apr 2022 13:42:44 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A75AE2F5C; Thu, 14 Apr 2022 10:40:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649958005; cv=none; d=zohomail.com; s=zohoarc; b=BM15ImIYlN3d8CHSWmYH8cPVwojD283p5be1s3TSPyyHhKnRVacFahwucqiJhXvM9sellc8nKwOCd1qextffBnW56TuGAS7wcWnel3BfhPXgPh8alChRyfGPVsdZDAi24f6P3kjslhT0lr9XtVRxAQ8k5MCVECWRa0k4RIIzF9Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649958005; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=s1LmDSijsmBE7FvhkLWY0uay9Ozv4AzabDKN3IG8EHc=; b=ksnfp6GJNp0G1CBpZ3MVlIv9XhJMGhOQxQwdKVGlslnEUjUBj2K6tYot6s6BcK2Iz8NkfLKX4kSJqqA35ijWMVUDzAyOW2I8PYXTYBiv7SRrIG63/CAe4GPWS4LS3zqocotOEhY9b+DAyhphyIxZrNZu6gVoWkQsSun6cfb83Po= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649958005; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=s1LmDSijsmBE7FvhkLWY0uay9Ozv4AzabDKN3IG8EHc=; b=LQR735vDndLpERduTO7MJi8Y+pixpSVoEVk9jcT6yz8AZjY2bzwcmMvWHKMHjJ2y SF3mn5WybNPXnfJdBh5ttVpwyllR9MkUZB7SsUYTN9Z5fPP/45MoSVe7i0HR785TM8R gQeKIQWaJ3JJwL+l6JGvDHPN+a0l2IkarnUEdh9Q= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649958003995788.4239165981783; Thu, 14 Apr 2022 10:40:03 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 06/14] pinctrl: ralink: rename driver names to subdrivers Date: Thu, 14 Apr 2022 20:39:08 +0300 Message-Id: <20220414173916.5552-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org MT7620, MT7621, RT2880, RT305X and RT3883 pinctrl are subdrivers of the Ralink pinctrl driver. Change the bool for these subdrivers accordingly. Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index aa82acfae827..1e4c5e43d69b 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -8,27 +8,27 @@ config PINCTRL_RALINK select GENERIC_PINCONF config PINCTRL_MT7620 - bool "mt7620 pinctrl driver for RALINK/Mediatek SOCs" + bool "MT7620 pinctrl subdriver" depends on RALINK && SOC_MT7620 select PINCTRL_RALINK config PINCTRL_MT7621 - bool "mt7621 pinctrl driver for RALINK/Mediatek SOCs" + bool "MT7621 pinctrl subdriver" depends on RALINK && SOC_MT7621 select PINCTRL_RALINK config PINCTRL_RT2880 - bool "RT2880 pinctrl driver for RALINK/Mediatek SOCs" + bool "RT2880 pinctrl subdriver" depends on RALINK && SOC_RT288X select PINCTRL_RALINK config PINCTRL_RT305X - bool "RT305X pinctrl driver for RALINK/Mediatek SOCs" + bool "RT305X pinctrl subdriver" depends on RALINK && SOC_RT305X select PINCTRL_RALINK config PINCTRL_RT3883 - bool "RT3883 pinctrl driver for RALINK/Mediatek SOCs" + bool "RT3883 pinctrl subdriver" depends on RALINK && SOC_RT3883 select PINCTRL_RALINK From patchwork Thu Apr 14 17:39:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 562691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81AA0C3527D for ; Thu, 14 Apr 2022 17:40:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343531AbiDNRm4 (ORCPT ); Thu, 14 Apr 2022 13:42:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343641AbiDNRmr (ORCPT ); Thu, 14 Apr 2022 13:42:47 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC96ECBE65; Thu, 14 Apr 2022 10:40:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649958009; cv=none; d=zohomail.com; s=zohoarc; b=QiN4AHvK3KnwMN+9cGg1O8lMD4IKOfm1I0x32BBlTfSm0y0umWI95aSaQydzX6o9dWPtzeFd2ctYtnkiP3B3xppjSI75OJhKVxaKtP9j+uIVIq0bHZHJHBCpC/4yOEYLRzC1n3F2PpYGouQV1Fs5smRauHzfsoR+I8Qc9a6LHsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649958009; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=0k+Tj9WfzOG3POKIY+KWQEOeUrgIztHXTMPJcor8xWs=; b=O4s71R3Rt+r+wQ9UU7Zzna4m3jMo1P+AoVTGkXOpRyZgOyQbYR1+2PQLcURFzyjHXbnpPUIAA5RfYd0qAea0FT1tLxoL9n9FuY9Kzd19xpZp0gK+FwSK4hSI9w7DSwyzUBNLapoM50k5uOjX70VCiahm/wXylgbcDExJo/bgHR0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649958009; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=0k+Tj9WfzOG3POKIY+KWQEOeUrgIztHXTMPJcor8xWs=; b=AnRM8nWTwRlK9nCFNwVUNi/ecZuaMZIHArAs0aEQlpwy0/Hkx/s2hAIjAyjU3FWg h4orxiXBJCsScMhF1ZuYY9IdGKhrXo6+icAs+HHr572whf346kUVhcJOrTkcHlNavn3 yeTrlqiPx1fZkGretDJqWVS5wGPyJtBIG8SnXbrc= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649958008198477.80974111231285; Thu, 14 Apr 2022 10:40:08 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 07/14] pinctrl: ralink: add new compatible strings for each pinctrl subdriver Date: Thu, 14 Apr 2022 20:39:09 +0300 Message-Id: <20220414173916.5552-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org As seen on any other pinctrl subdriver that calls code from a main driver, each subdriver needs to have a different compatible string. We don't want the same compatible string to match a different subdriver's pinmux data as it's not for our SoC. Therefore, add new compatible strings for each pinctrl subdriver. Change driver name on all subdrivers accordingly. Signed-off-by: Arınç ÜNAL --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 4 ++-- drivers/pinctrl/ralink/pinctrl-mt7621.c | 4 ++-- drivers/pinctrl/ralink/pinctrl-rt2880.c | 4 ++-- drivers/pinctrl/ralink/pinctrl-rt305x.c | 4 ++-- drivers/pinctrl/ralink/pinctrl-rt3883.c | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index fde269c68a7b..22ff16eff02f 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -371,7 +371,7 @@ static int mt7620_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id mt7620_pinctrl_match[] = { - { .compatible = "ralink,rt2880-pinmux" }, + { .compatible = "ralink,mt7620-pinctrl" }, {} }; MODULE_DEVICE_TABLE(of, mt7620_pinctrl_match); @@ -379,7 +379,7 @@ MODULE_DEVICE_TABLE(of, mt7620_pinctrl_match); static struct platform_driver mt7620_pinctrl_driver = { .probe = mt7620_pinctrl_probe, .driver = { - .name = "rt2880-pinmux", + .name = "mt7620-pinctrl", .of_match_table = mt7620_pinctrl_match, }, }; diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/ralink/pinctrl-mt7621.c index 1470250ca3b7..b47968f40e0c 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -96,7 +96,7 @@ static int mt7621_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id mt7621_pinctrl_match[] = { - { .compatible = "ralink,rt2880-pinmux" }, + { .compatible = "ralink,mt7621-pinctrl" }, {} }; MODULE_DEVICE_TABLE(of, mt7621_pinctrl_match); @@ -104,7 +104,7 @@ MODULE_DEVICE_TABLE(of, mt7621_pinctrl_match); static struct platform_driver mt7621_pinctrl_driver = { .probe = mt7621_pinctrl_probe, .driver = { - .name = "rt2880-pinmux", + .name = "mt7621-pinctrl", .of_match_table = mt7621_pinctrl_match, }, }; diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/ralink/pinctrl-rt2880.c index 9c5e828af43a..811e12df1133 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c @@ -40,7 +40,7 @@ static int rt2880_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id rt2880_pinctrl_match[] = { - { .compatible = "ralink,rt2880-pinmux" }, + { .compatible = "ralink,rt2880-pinctrl" }, {} }; MODULE_DEVICE_TABLE(of, rt2880_pinctrl_match); @@ -48,7 +48,7 @@ MODULE_DEVICE_TABLE(of, rt2880_pinctrl_match); static struct platform_driver rt2880_pinctrl_driver = { .probe = rt2880_pinctrl_probe, .driver = { - .name = "rt2880-pinmux", + .name = "rt2880-pinctrl", .of_match_table = rt2880_pinctrl_match, }, }; diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c index b4765ca27cac..5b204b7ca1f3 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -117,7 +117,7 @@ static int rt305x_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id rt305x_pinctrl_match[] = { - { .compatible = "ralink,rt2880-pinmux" }, + { .compatible = "ralink,rt305x-pinctrl" }, {} }; MODULE_DEVICE_TABLE(of, rt305x_pinctrl_match); @@ -125,7 +125,7 @@ MODULE_DEVICE_TABLE(of, rt305x_pinctrl_match); static struct platform_driver rt305x_pinctrl_driver = { .probe = rt305x_pinctrl_probe, .driver = { - .name = "rt2880-pinmux", + .name = "rt305x-pinctrl", .of_match_table = rt305x_pinctrl_match, }, }; diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/ralink/pinctrl-rt3883.c index b2e8151de226..44a66c3d2d2a 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -87,7 +87,7 @@ static int rt3883_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id rt3883_pinctrl_match[] = { - { .compatible = "ralink,rt2880-pinmux" }, + { .compatible = "ralink,rt3883-pinctrl" }, {} }; MODULE_DEVICE_TABLE(of, rt3883_pinctrl_match); @@ -95,7 +95,7 @@ MODULE_DEVICE_TABLE(of, rt3883_pinctrl_match); static struct platform_driver rt3883_pinctrl_driver = { .probe = rt3883_pinctrl_probe, .driver = { - .name = "rt2880-pinmux", + .name = "rt3883-pinctrl", .of_match_table = rt3883_pinctrl_match, }, }; From patchwork Thu Apr 14 17:39:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 562690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DC37C4167B for ; Thu, 14 Apr 2022 17:40:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343576AbiDNRm6 (ORCPT ); Thu, 14 Apr 2022 13:42:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245382AbiDNRmu (ORCPT ); Thu, 14 Apr 2022 13:42:50 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEA0DCBE65; Thu, 14 Apr 2022 10:40:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649958013; cv=none; d=zohomail.com; s=zohoarc; b=SxT+YysqHldEASIpwf+tgvOGcVdWDRXovqqKgD0hLrA7ET3Oszn2HcnWPrDDe36kh6ikPi1NC7YXD9lS70UP0mXHRAUkjyhiU6wzX/3nVgJVsxo6UMrSUGxdbZcwTqfebE1IgPu0OHiKfwsf/ScaxLbzD+FwrgmjIK9nTyB8jBs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649958013; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=NG1xjMeRvySQG6QrVBIRKQOBl6ROVJFrGcd25yzx2/k=; b=AH52jsCC0XdOv8tm5kgTUdB3ZP1WbXMQZFDpd8o1pyZgks4dLwctGI8R3kcpbD0kx6V9a6Vla2wVVxqU+deD8Q/D9gfGLfX23V/GYfmak/Notx65PyBhivvGApxKEheHts3cY/ThNBOg0eLYfmidKti9wzhhQhoLSvOTCz2oYI4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649958013; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=NG1xjMeRvySQG6QrVBIRKQOBl6ROVJFrGcd25yzx2/k=; b=JrskM3nhTEfYpOqLfbJH0NzrxUmKDl2KP50GspS53tmUJE8rLQkZabkOwgyycfyc khDvq4C7yyETDQtvOOrEYkIynQJ5R0ivD4lDbfA4/R8ib9z1YG1vdINhkVD1edFvZfr SXGmjBQT46aVmQEYbcR8V6OCjnIG6NXTr0NHy0XM= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649958012254748.8245005807139; Thu, 14 Apr 2022 10:40:12 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 08/14] MAINTAINERS: add Ralink pinctrl driver Date: Thu, 14 Apr 2022 20:39:10 +0300 Message-Id: <20220414173916.5552-9-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a new section for the Ralink pinctrl driver and add me and Sergio as the maintainers. Signed-off-by: Arınç ÜNAL Reviewed-by: Sergio Paracuellos --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fd768d43e048..27bfecaa00ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16502,6 +16502,13 @@ L: linux-mips@vger.kernel.org S: Maintained F: arch/mips/boot/dts/ralink/mt7621* +RALINK PINCTRL DRIVER +M: Arınç ÜNAL +M: Sergio Paracuellos +L: linux-mips@vger.kernel.org +S: Maintained +F: drivers/pinctrl/ralink/ + RALINK RT2X00 WIRELESS LAN DRIVER M: Stanislaw Gruszka M: Helmut Schaa From patchwork Thu Apr 14 17:39:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 562689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87E3DC4332F for ; Thu, 14 Apr 2022 17:40:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343687AbiDNRnF (ORCPT ); Thu, 14 Apr 2022 13:43:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343599AbiDNRnC (ORCPT ); Thu, 14 Apr 2022 13:43:02 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12905E2F5C; Thu, 14 Apr 2022 10:40:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649958017; cv=none; d=zohomail.com; s=zohoarc; b=U+BOK0yxGmhzsUrcSNrdl8S9x/AIthHTs84EHPilgjRUcemeuyVKL7l72czvLAiCnREv3BbNI+s3Q3nvNdKzYymN84kzxCTK2TTFHXtTVQejHUZYjS+ETbCwIhmA6NQO8apoY09E733FzkjXx94LtMB+t9IUVJ2kMnLzpjlsNy0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649958017; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=MB5zzWcylEqjeE5qy26s0JEc3WbeD8CfHOfbrOz2uqg=; b=LaUhHkZaOcKqsul/1EEsbvJi12DxU9iy+qBpGaCMCe7gLHE/WB4zWyXaQhj6pFnMMaDeuEkARslw9gqn7576DiNogzZhoKxU/XJerJ5anx3/CAqzspiYEtJaWnpxJmpfzgOMnR9Vmjl5hzuQUheZoa28hXxwEWaZTsGITxssbEw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649958017; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=MB5zzWcylEqjeE5qy26s0JEc3WbeD8CfHOfbrOz2uqg=; b=YgK/x8W5mq8eWD0Eieec2lIx0O75cEFl+70SeV2AFXeIKp85fPGtf36M4GGLnjIK Grv805/J9goufe4gdKXvynUSsOK6p/nHKNvqabbMqnAC99nvl0EfKvPFbk261pxX97p fYJ4XKqRIqtIBO1CH82DBM7WscUHh+nTHSGeDUts= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 164995801641693.13202580357915; Thu, 14 Apr 2022 10:40:16 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 09/14] mips: dts: ralink: mt7621: use the new compatible string for MT7621 pinctrl Date: Thu, 14 Apr 2022 20:39:11 +0300 Message-Id: <20220414173916.5552-10-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Use the new compatible string "ralink,mt7621-pinctrl" for the Ralink MT7621 pinctrl subdriver on mt7621.dtsi. Each subdriver needs to have a different compatible string. We don't want the same compatible string to match a different subdriver's pinmux data as it's not for our SoC. Signed-off-by: Arınç ÜNAL --- arch/mips/boot/dts/ralink/mt7621.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 3222684915ac..ee2ec78c8952 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -151,7 +151,7 @@ spi0: spi@b00 { }; pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; + compatible = "ralink,mt7621-pinctrl"; i2c_pins: i2c0-pins { pinmux { From patchwork Thu Apr 14 17:39:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 561293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18A42C433EF for ; Thu, 14 Apr 2022 17:41:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343764AbiDNRnc (ORCPT ); Thu, 14 Apr 2022 13:43:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343653AbiDNRnC (ORCPT ); Thu, 14 Apr 2022 13:43:02 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E5A3E438E; Thu, 14 Apr 2022 10:40:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649958021; cv=none; d=zohomail.com; s=zohoarc; b=g32l+8hgqG2jlHAkGyf2aftxPyygZoQr+oeoLg/pkbWQS1CTnab0pmTIsscpR/uHPd+i0ifVVmeWxnIkMzSjhNkgHzWkQYNsjZTj6kZH6bRWegI+BeYycIb2g9V6GeoAp730suSfvM9GHArRv7Gy6bHO2/l66pHn/d66e5Eh9ok= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649958021; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=IMNM5MdolEKAJtDmJ2L/PHlHBjhgQ3P7ALeEsPMkcPE=; b=RH3tKHeYfIOaAblCTyjShRpiqA89T3oU8ZQ9fjZdiUy34EyMUJ8LE6dFyMBEFaMqTin8BALWr8pePQyu9K4hyVHR+WZKahh0+WPBYELf5i9Lu43aN1l4zkDGFdlqyXR70sXZ7PWeYyfCHZ83e0Ws0zBvkH4R+V/cC+qHAAJea1Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649958021; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=IMNM5MdolEKAJtDmJ2L/PHlHBjhgQ3P7ALeEsPMkcPE=; b=ZNY/n5JCYx3TQwbAbGTHA3bN5nnjYchtA/08g6NTTxK2q9wmWaQeETBY1bNC6sPZ 2e0OoIVfM6FVXbwewDL+fz69UCFLjzXq4hkULiB5heMKwVX6hLwrtAL2poiyrhW5rNi W6PuhSndgYzURR4bcsmbi4/ckvsVT94cpqwr0UgE= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649958020478365.7778123721878; Thu, 14 Apr 2022 10:40:20 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 10/14] dt-bindings: pinctrl: rt2880: fix binding name, pin groups and functions Date: Thu, 14 Apr 2022 20:39:12 +0300 Message-Id: <20220414173916.5552-11-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Deprecate the old property "ralink,rt2880-pinmux". Add the new property "ralink,rt2880-pinctrl". The old property name was inaccurate as the hardware block is called pinctrl across the Mediatek/Ralink architecture. Current pin group and function bindings are for MT7621. Put bindings for RT2880 instead. Add me as a maintainer. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- ...pinmux.yaml => ralink,rt2880-pinctrl.yaml} | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) rename Documentation/devicetree/bindings/pinctrl/{ralink,rt2880-pinmux.yaml => ralink,rt2880-pinctrl.yaml} (53%) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml similarity index 53% rename from Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml rename to Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml index 9de8b0c075e2..56e5becabcfd 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -1,21 +1,23 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinmux.yaml# +$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink rt2880 pinmux controller +title: Ralink RT2880 Pin Controller maintainers: + - Arınç ÜNAL - Sergio Paracuellos description: - The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins - is not supported. There is no pinconf support. + Ralink RT2880 pin controller for RT2880 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. properties: compatible: - const: ralink,rt2880-pinmux + const: ralink,rt2880-pinctrl patternProperties: '-pins$': @@ -28,14 +30,12 @@ patternProperties: properties: groups: - description: Name of the pin group to use for the functions. - enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, - uart1, uart2, uart3, wdt] + description: The pin group to select. + enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci] + function: - description: The mux function to select - enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk, - pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, - spi, uart1, uart2, uart3, wdt refclk, wdt rst] + description: The mux function to select. + enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci] required: - groups @@ -57,7 +57,7 @@ examples: # Pinmux controller node - | pinctrl { - compatible = "ralink,rt2880-pinmux"; + compatible = "ralink,rt2880-pinctrl"; i2c_pins: i2c0-pins { pinmux { From patchwork Thu Apr 14 17:39:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 562688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2925C433EF for ; Thu, 14 Apr 2022 17:41:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343841AbiDNRnl (ORCPT ); Thu, 14 Apr 2022 13:43:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343670AbiDNRnE (ORCPT ); Thu, 14 Apr 2022 13:43:04 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8397E540D; Thu, 14 Apr 2022 10:40:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649958025; cv=none; d=zohomail.com; s=zohoarc; b=k/q9eXTFM3bj6T0VYQGFHBQF39Z4kjz/0P9AuilBKrcxelVvHddFmuFr5Fp89kh+KwxXptvpan3miGrwRaC6PhCVvHlDecaV0P4ofmGFhRa2QCLKXLRFcKQrMvsTyvSbBOib5sFtC3SIuNMCiizkmp8L+5J3yX+o1U8GuV+pVBY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649958025; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=ThSA3OlMdtKDRied4vhuun5OS9ubpkDQSHM9sks5C/8=; b=QW9gLR7WsLMzbijBz7E1p+B9Qn4KjJ8hRzd+Z7mcRj1M70V5unUNT+GVOE8HEMqDDA6bTTMyq6My8c/ddiguz0sRYNfCRVzg9xkXAgbpgMZylNdXMTa3mch1l9aoyX/nrkVYPvx4q+/Mofw7xPoiGVN7TeZctG+UUGRW7J4WXTs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649958025; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=ThSA3OlMdtKDRied4vhuun5OS9ubpkDQSHM9sks5C/8=; b=A3yymyo7nniDqwgMIYRccuIexWf6yNALaHsCG/mMt1/DAZaZM3zpBQ9WO3Xfmw9m 5HLrji1uXscRN4n47I4kdyAbAo0PV9HGWdBMkpfHzenCk3OZjfShmahy0D/4MHV1Knt 6R/+cExkdmZBfZh6FVZ8yueRByY1clcH71Ibc9Ug= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649958024558393.88923947858166; Thu, 14 Apr 2022 10:40:24 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 11/14] dt-bindings: pinctrl: add binding for Ralink MT7620 pinctrl Date: Thu, 14 Apr 2022 20:39:13 +0300 Message-Id: <20220414173916.5552-12-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add binding for the Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../pinctrl/ralink,mt7620-pinctrl.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml new file mode 100644 index 000000000000..4d820df24b89 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink MT7620 Pin Controller + +maintainers: + - Arınç ÜNAL + - Sergio Paracuellos + +description: + Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,mt7620-pinctrl + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + groups: + description: The pin group to select. + enum: [ + # For MT7620 SoC + ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi, spi refclk, + uartf, uartlite, wdt, wled, + + # For MT7628 and MT7688 SoCs + gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, + p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, perst, pwm0, + pwm1, refclk, sdmode, spi, spi cs1, spis, uart0, uart1, uart2, + wdt, wled_an, wled_kn, + ] + + function: + description: The mux function to select. + enum: [ + # For MT7620 SoC + ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, pa, + pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, refclk, + rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, wdt refclk, + wdt rst, wled, + + # For MT7628 and MT7688 SoCs + antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn, + p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, + p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2, + refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi, spi cs1, + spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -, + ] + + required: + - groups + - function + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl { + compatible = "ralink,mt7620-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; From patchwork Thu Apr 14 17:39:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 561292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6212CC4332F for ; Thu, 14 Apr 2022 17:41:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343807AbiDNRoU (ORCPT ); Thu, 14 Apr 2022 13:44:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343812AbiDNRnk (ORCPT ); Thu, 14 Apr 2022 13:43:40 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20FC1E5E06; Thu, 14 Apr 2022 10:40:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649958029; cv=none; d=zohomail.com; s=zohoarc; b=KVeMzSgeDpo4GcXnQH3o4fRt/ep537h8o9yZbvlijzmMaiwXL0jElXwHJYMMUgQayMCPeYDgio39SWuB5My+hEEzRoU0bZewOxAse7zkJJBGLI9M+K7Y0qJnsQfT0L/bCmXivhDUA14O7LMD8NJczYPyl8DngTPJiBwQGzoiRoc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649958029; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=ibmv8AUMMdSWzgOCsWD+VVMc5Jm5c8uINz1Zok6MZAc=; b=dFl666zh9FnLkvypFpBGshhWsxpqoVM9pLfKnLi7bImdpRAtnu76dK5kwTDQo6eXp4ASy0GDkRAD0jrvomwQJR4LuNq8Cg7WJrGx8VwUQbhKUNzWpKZdVtWS18HXDnvEqic5+azePt2MfujspzJEHDcKELvHPjqAutZz2CAO0vc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649958029; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=ibmv8AUMMdSWzgOCsWD+VVMc5Jm5c8uINz1Zok6MZAc=; b=AM3xkdTZEDBXNJgBRUoIkqC80c74W+ZEG4Oy4DzkuyuRrT1LXe8nULvZ7McrlJ5x pr+c9mb2BtX8aJeX9dT783qwvMPC1ZTrIkfrsxb7xrV1rZPwmvpjyHwGv52TcYJNGwF aVqrwVFhXgOYrTohpamQap3w6kYfrXZTnkeTdI98= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649958028615793.6488409177414; Thu, 14 Apr 2022 10:40:28 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 12/14] dt-bindings: pinctrl: add binding for Ralink MT7621 pinctrl Date: Thu, 14 Apr 2022 20:39:14 +0300 Message-Id: <20220414173916.5552-13-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add binding for the Ralink MT7621 pin controller for MT7621 SoC. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../pinctrl/ralink,mt7621-pinctrl.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml new file mode 100644 index 000000000000..61e5c847e8c8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,mt7621-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink MT7621 Pin Controller + +maintainers: + - Arınç ÜNAL + - Sergio Paracuellos + +description: + Ralink MT7621 pin controller for MT7621 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,mt7621-pinctrl + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + groups: + description: The pin group to select. + enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, uart1, + uart2, uart3, wdt] + + function: + description: The mux function to select. + enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk, + pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, spi, + uart1, uart2, uart3, wdt refclk, wdt rst] + + required: + - groups + - function + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl { + compatible = "ralink,mt7621-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; From patchwork Thu Apr 14 17:39:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 562687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 157A6C43217 for ; Thu, 14 Apr 2022 17:41:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343597AbiDNRoW (ORCPT ); Thu, 14 Apr 2022 13:44:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343870AbiDNRnl (ORCPT ); Thu, 14 Apr 2022 13:43:41 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80D47E6C77; Thu, 14 Apr 2022 10:40:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649958033; cv=none; d=zohomail.com; s=zohoarc; b=HmBlFh49I5d+3fOI1GKxvLytOXmNgP1fBtydOZs8BNrN8me3t1ryRdFPFHLrLVmfb5iQxqKRXGpUJf1Ct/2/5nsknrW9AxoHKJXcIc3UBaKPF6I0OyQZ26yWhSpuS5ipKmJpM11IyWest+q5bg9ycX6RlsGNI5gtnq48Z9RwnII= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649958033; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=6WorpwNzRGvitFn8B8dTme9JwnssgeQFz9v0cURTiC8=; b=C6fADviAfg4UclzJnIwrrgchvrT1Rn2gzuUzcE8WdZUzWVlvJ7cwEyu36FxDtJ9T22pPG+y+vkloBNxzvV4YNBDQ+1sycRhE2SXPw+TLKcHmzzhpOkaYB0y3UkpTLabYEe7sZCN3giSQOpYSnIZ8LXkB5A3wrG0dvQSPqMTNDPE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649958033; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=6WorpwNzRGvitFn8B8dTme9JwnssgeQFz9v0cURTiC8=; b=Bh6yL6OHatcspOpXw2TZiHB0ITqcWhOFQoqPzeb4fixH1Abz+48ChkV15yQVbhR0 Ubt2hMWV2bPDrY854+YQrXqDx+2N91LEBtlTjOVXrLCUnHSNKSVcCr/02RiHTKrljNi epawh+Ch135EdrAAdWxEV7iYCB5roms9sUd5FZzg= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649958032683220.010621040307; Thu, 14 Apr 2022 10:40:32 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 13/14] dt-bindings: pinctrl: add binding for Ralink RT305X pinctrl Date: Thu, 14 Apr 2022 20:39:15 +0300 Message-Id: <20220414173916.5552-14-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add binding for the Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 SoCs. Signed-off-by: Arınç ÜNAL --- .../pinctrl/ralink,rt305x-pinctrl.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml new file mode 100644 index 000000000000..425401c54269 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT305X Pin Controller + +maintainers: + - Arınç ÜNAL + - Sergio Paracuellos + +description: + Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 + SoCs. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt305x-pinctrl + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + groups: + description: The pin group to select. + enum: [ + # For RT3050, RT3052 and RT3350 SoCs + i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite, + + # For RT3352 SoC + i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, uartf, + uartlite, + + # For RT5350 SoC + i2c, jtag, led, spi, spi_cs1, uartf, uartlite, + ] + + function: + description: The mux function to select. + enum: [ + # For RT3050, RT3052 and RT3350 SoCs + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, pcm gpio, + pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, uartlite, + + # For RT3352 SoC + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna, mdio, + pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf, + uartlite, wdg_cs1, + + # For RT5350 SoC + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, pcm gpio, + pcm i2s, pcm uartf, spi, spi_cs1, uartf, uartlite, wdg_cs1, + ] + + required: + - groups + - function + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl { + compatible = "ralink,rt305x-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; From patchwork Thu Apr 14 17:39:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 561291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5D0DC4332F for ; Thu, 14 Apr 2022 17:42:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343915AbiDNRo0 (ORCPT ); Thu, 14 Apr 2022 13:44:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233574AbiDNRoR (ORCPT ); Thu, 14 Apr 2022 13:44:17 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71F1BE886E; Thu, 14 Apr 2022 10:40:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649958037; cv=none; d=zohomail.com; s=zohoarc; b=joc2zAh9PnYoF6a3Fpj18fCOK4TGDnIhxildQ4C1cnbiq7AGRMfWP9qkuOdCwnImjqS7nCuC/3bz/wCrtTZd4dJiIXAskG2SNlTjtGXR6jY+02xHHwVUXxaAYVukvydl4R3uN7XS/fypsYRkVyTvu4+YPRS6zAGCNySC+Qu5jRo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649958037; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=rffJtQeH1wfjiUy7isMajL4hWPrAoIiKaMOQgFEbJNU=; b=M/zCJuaOGJN1Vm8m1yts/WAOpd+Jq1+O0TIoD9LBNBhwW/DWVazpA8gVrYBtiMJNN/bpiJ6/Gw1MyNrDqbSrV6DclvSGp9/jwcu8Cl7VwXn/QOxK/NM+dkhe+ZZhJ3gjm1TYv+7lBT+f0ENomHyVUqRfU39XeQtdbSA1HnHGAw4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1649958037; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=rffJtQeH1wfjiUy7isMajL4hWPrAoIiKaMOQgFEbJNU=; b=caHMaWu3G8Ofzf70Fdijp0G0038JQoum2KD4GkZKn5sG1ZsvGPvdan402XdMvFsu GPAt5ZC0uLV9MEZZ9X87/9rXNjER43/EhRVJ8iz7dhTdlRjy1s9FZmEV8Y8dZQy54rt RveQgWTQru6PxpGuVA0PLA8aN9mYj35fbzKY8bE0= Received: from arinc9-PC.localdomain (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1649958036757805.531660630592; Thu, 14 Apr 2022 10:40:36 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Sergio Paracuellos , Luiz Angelo Daros de Luca , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Matthias Brugger , Joe Perches Cc: erkin.bozoglu@xeront.com, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 14/14] dt-bindings: pinctrl: add binding for Ralink RT3883 pinctrl Date: Thu, 14 Apr 2022 20:39:16 +0300 Message-Id: <20220414173916.5552-15-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414173916.5552-1-arinc.unal@arinc9.com> References: <20220414173916.5552-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add binding for the Ralink RT3883 pin controller for RT3883 SoC. Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../pinctrl/ralink,rt3883-pinctrl.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml new file mode 100644 index 000000000000..feb6e66dcb61 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt3883-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT3883 Pin Controller + +maintainers: + - Arınç ÜNAL + - Sergio Paracuellos + +description: + Ralink RT3883 pin controller for RT3883 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt3883-pinctrl + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + groups: + description: The pin group to select. + enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, uartf, + uartlite] + + function: + description: The mux function to select. + enum: [ge1, ge2, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, + lna a, lna g, mdio, pci-dev, pci-fnc, pci-host1, pci-host2, + pcm gpio, pcm i2s, pcm uartf, spi, uartf, uartlite] + + required: + - groups + - function + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl { + compatible = "ralink,rt3883-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + };