From patchwork Fri Apr 15 16:46:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 562011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 119A8C433F5 for ; Fri, 15 Apr 2022 16:47:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354392AbiDOQtc (ORCPT ); Fri, 15 Apr 2022 12:49:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244570AbiDOQta (ORCPT ); Fri, 15 Apr 2022 12:49:30 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2656CDD96C for ; Fri, 15 Apr 2022 09:47:01 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id x18so3408723wrc.0 for ; Fri, 15 Apr 2022 09:47:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vB6otgN6KYMTsyvfy8Rm2UY11rcsammOuJhzDpIaLBk=; b=U5ttExxfGAO73CicJ6gCH58uzFTGudxUSjM0u+LuSZcVFWwiVVf5SvGzcwNn29Ozbe O+4Yb4NTWj39cX38QcbH3iRjuNOH7GWoWwJT+14PYiYBD19dd0adrg7tFYfC3SJigK15 G+fUsaCqyVS9BRcOSGv3mWf8Msxhdd0CjAy4PUXvMgq6g5SWGcmuOe/GKhJ8q+kcja+z fkI0PgAILmVGAI6Qg96PM6+IFsusf8cm6PqwZLiRQMfsXxiPb2y+h9ygNpz0MGyB3c2W RJpVM/nJzcptU3qg0bzTj/LtI9OWBndWh4MfBpnL7IA8trh6DEWlDY42Z+C51VDEizvV JexA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vB6otgN6KYMTsyvfy8Rm2UY11rcsammOuJhzDpIaLBk=; b=OmC+BK/jASmmkeu+mBdk/YKtC5YIDnxsFHQLBYtOerRObaSpXpRhihLdbXU7V1/ogp hFr7DXRpkuU0I30bKiXwrSiNjw0rUZBvx07Vt2nbMswrF1uNInEtP7hQ7tX4RXxQf3by k5ASfy0WnPTLCxf4fI6xnHQeHdkprYpF61rWY9LVx8HDWWHk8m2PboJTcE2kPbXAfGK1 vGvKdQ3XrBN8YrWxnDs3rOhCt3fxyFjJTYKj9uYuKKW4SgGT0ZXShQa8sykrghtLdYSb rn5xfbky1RY3j60uRcCJ5znp3wI95BJXPQauafVYFenT0xMxuS5SEwFnbEO5EZLy3rbq F5jQ== X-Gm-Message-State: AOAM5324OcnhBNjY5eCF+YmamEYFfZKxSRb0h172uJVLvYDy792lWeeM XdfztluA3PTbWVcTXH4uwr+OWw== X-Google-Smtp-Source: ABdhPJxU0icA1dSMc5GujYLgmolhkVIGWOUgzZPV55JrRNVHvBfJLVaAz9OOR1gmfms9h3+rfagH+g== X-Received: by 2002:adf:f9c6:0:b0:207:b63c:77a3 with SMTP id w6-20020adff9c6000000b00207b63c77a3mr42584wrr.665.1650041219672; Fri, 15 Apr 2022 09:46:59 -0700 (PDT) Received: from sagittarius-a.chello.ie (188-141-3-169.dynamic.upc.ie. [188.141.3.169]) by smtp.gmail.com with ESMTPSA id t9-20020a05600c198900b0038cb8b38f9fsm9180041wmq.21.2022.04.15.09.46.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 09:46:59 -0700 (PDT) From: Bryan O'Donoghue To: vladimir.zapolskiy@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: dmitry.baryshkov@linaro.org, jonathan@marek.ca, hfink@snap.com, jgrahsl@snap.com, bryan.odonoghue@linaro.org Subject: [PATCH v3 1/3] arm64: dts: qcom: sm8250: Add camcc DT node Date: Fri, 15 Apr 2022 17:46:53 +0100 Message-Id: <20220415164655.1679628-2-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220415164655.1679628-1-bryan.odonoghue@linaro.org> References: <20220415164655.1679628-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the camcc DT node for the Camera Clock Controller on sm8250. Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index af8f22636436..401e17f849f3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include / { @@ -3149,6 +3150,21 @@ videocc: clock-controller@abf0000 { #power-domain-cells = <1>; }; + camcc: clock-controller@ad00000 { + compatible = "qcom,sm8250-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sm8250-mdss"; reg = <0 0x0ae00000 0 0x1000>; From patchwork Fri Apr 15 16:46:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 562010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91CA1C43217 for ; Fri, 15 Apr 2022 16:47:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349200AbiDOQtd (ORCPT ); Fri, 15 Apr 2022 12:49:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355361AbiDOQtc (ORCPT ); Fri, 15 Apr 2022 12:49:32 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF603DD963 for ; Fri, 15 Apr 2022 09:47:03 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id k22so11253945wrd.2 for ; Fri, 15 Apr 2022 09:47:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hABzIMEOhhM37fzkgMVGRIotHTAtLjUxj+/0GDBlE3w=; b=cB1IdQMFOmuNR8Xl8nfA3mgiLjaRAcwAVlJ8IzQxLk9Q3sBsXQMoTnX7FR1G9Akpof bqRjntapA/zXCw86pFGQgRrIummmIESWjbP1jhOpTCVNmLw2nU35EPuEhnlrRYYbG0XU kASAe4K2vsSXzt6ebLzI3bW6QOGhmHuMRuaSnLzbWrJUQ+tZYd9nEWRbWcNyDxvcfQcT 2EyP20Ye5GRYTraVnMQUfPTOOy87wtm6IsTS5PDj3884aW6ZLxsoWPew6LOlW+jzOLwJ DtGwc2E6lO5Dyj2aXOYvbF4CWHGTaHqYMKcqtTIFEhvK+8NeigbI8A6vM0OqmtJPzBUK SWfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hABzIMEOhhM37fzkgMVGRIotHTAtLjUxj+/0GDBlE3w=; b=ifGDCS1YLZsc0Qb1eOxpDZQn6ulJ41AeML+FN3TsLcLodKykmlEIgnNkv5MpkHOemI n0rLJ64P20XQSZfzHNxq2PCZkYywwPrAtADkDtyIQlGAU7XYCsvewGhCtOgzUxeBe4M9 RyVLVv8jYZAAb9MDKsPNmwrkJp/pYSE/06za/FbvuzuBQEx58i3P6fA74jh60fK5mmuH GoTFn52zUdVZedbJDLOSMVw0GiKeCXxVzo4xV2r6t1FwIQo9RmLQtXndrYeNvo3Ztb4I adBXYsOzMpVCJugtTatlF1DwR5I/2I2IQuJt2vMy9t+/2enS11WKvwW2EY5bfyFewaxK Nt8Q== X-Gm-Message-State: AOAM531Gl91c4rpJsK6RhGc82kLaVFhb+YS6ZLVQoDlpbrUyJEKyJD6x 9UJdOlLWF4MtyB+4F+NMQnbmGA== X-Google-Smtp-Source: ABdhPJyW3+ymC3ml/wW3Etuj/tKGoqmmYj75nWYTYO5+sH2iIvkbchIEbxxkShXcwenJyZ7GqRoZQw== X-Received: by 2002:a05:6000:1869:b0:20a:78e2:522e with SMTP id d9-20020a056000186900b0020a78e2522emr73269wri.340.1650041222495; Fri, 15 Apr 2022 09:47:02 -0700 (PDT) Received: from sagittarius-a.chello.ie (188-141-3-169.dynamic.upc.ie. [188.141.3.169]) by smtp.gmail.com with ESMTPSA id t9-20020a05600c198900b0038cb8b38f9fsm9180041wmq.21.2022.04.15.09.47.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 09:47:01 -0700 (PDT) From: Bryan O'Donoghue To: vladimir.zapolskiy@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: dmitry.baryshkov@linaro.org, jonathan@marek.ca, hfink@snap.com, jgrahsl@snap.com, bryan.odonoghue@linaro.org Subject: [PATCH v3 3/3] arm64: dts: qcom: sm8250: camss: Add CCI definitions Date: Fri, 15 Apr 2022 17:46:55 +0100 Message-Id: <20220415164655.1679628-4-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220415164655.1679628-1-bryan.odonoghue@linaro.org> References: <20220415164655.1679628-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org sm8250 has two CCI busses with two I2C busses apiece. Co-developed-by: Julian Grahsl Signed-off-by: Julian Grahsl Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 162 +++++++++++++++++++++++++++ 1 file changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 2ec9adeb2e66..b08143ba096d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3150,6 +3150,88 @@ videocc: clock-controller@abf0000 { #power-domain-cells = <1>; }; + cci0: cci@ac4f000 { + compatible = "qcom,sm8250-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4f000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac50000 { + compatible = "qcom,sm8250-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac50000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: camss@ac6a000 { compatible = "qcom,sm8250-camss"; status = "disabled"; @@ -3688,6 +3770,86 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 181>; wakeup-parent = <&pdc>; + cci0_default: cci0-default { + cci0_i2c0_default: cci0-i2c0-default { + /* SDA, SCL */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci0_i2c1_default: cci0-i2c1-default { + /* SDA, SCL */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + }; + + cci0_sleep: cci0-sleep { + cci0_i2c0_sleep: cci0-i2c0-sleep { + /* SDA, SCL */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep { + /* SDA, SCL */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + }; + + cci1_default: cci1-default { + cci1_i2c0_default: cci1-i2c0-default { + /* SDA, SCL */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_i2c1_default: cci1-i2c1-default { + /* SDA, SCL */ + pins = "gpio107","gpio108"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + }; + + cci1_sleep: cci1-sleep { + cci1_i2c0_sleep: cci1-i2c0-sleep { + /* SDA, SCL */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + + bias-pull-down; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep { + /* SDA, SCL */ + pins = "gpio107","gpio108"; + function = "cci_i2c"; + + bias-pull-down; + drive-strength = <2>; /* 2 mA */ + }; + }; + pri_mi2s_active: pri-mi2s-active { sclk { pins = "gpio138";