From patchwork Sat Apr 16 00:33:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chia-I Wu X-Patchwork-Id: 562655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61E9DC433F5 for ; Sat, 16 Apr 2022 00:36:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229553AbiDPAjK (ORCPT ); Fri, 15 Apr 2022 20:39:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229445AbiDPAjK (ORCPT ); Fri, 15 Apr 2022 20:39:10 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56792AE43 for ; Fri, 15 Apr 2022 17:36:35 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id q12so9063252pgj.13 for ; Fri, 15 Apr 2022 17:36:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=FSpeGI+AKCEsOeI+kpzi6mqwOR7Zmm4NjdrpPLaO+uk=; b=Xkeb/eK0YajPaB1EbwGsYvDPvezCBkZvGOWMof9W3sVXS+yjF/c/+BEHBuHJh0uiEc 4mICmkMIxiVdXFcvEu/NVcApQsUh7LCOeMRx2Ranap89omih6ev1lFALLY2PJ7WNK4US Fzk9K20aHoTqVUzsmgX0711c5+pVhjiADrmuqH4Znq68D4fc/6KnxeYywreXPeUtYq1U oDhxcC5hcdbXGt/WiOUq997iXEIenMTo37VaOrlAqCGUu2uapa3MyTRDTN1ofnMA+//3 XK8RJsxoftuui9aSBKyS8vCI2x6TcC0gCl4BorIr7kQsFaiu+Xs3YAopGdXBZxvpXY4W 7JeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=FSpeGI+AKCEsOeI+kpzi6mqwOR7Zmm4NjdrpPLaO+uk=; b=1ngDYYaaX3xWrCNOp24XbMdnNScYycQluc+P5L4vAldBcmcT+I3KaQhFvPNnR689vL OTBAbWV9fx9ImuX8v+Crbeu0+G1FH3IC5Ju12U7rsEEdQ1rUpWisi4DK8J10VYt0p2aL Q86w17UUnuL5IqXV7zIgI83MOiAp5kkYtuxuQiEf3u/O/7gt1oHZXwlxZ9xuHXS6fLx5 OlptW16pI6GIx5vSKk29YjhS40jvokcov45tGPXy+TC/qAtKqmfwuruL1i5VWQ53gEzL IjosrrVNu4N2aol1vXPPCsA2qLZD1Cd1VMqDFpGdwYzNi82ShY+TFaQ4nrUEHfN/bti3 ooiQ== X-Gm-Message-State: AOAM5319w0RFdmj2bqNEnRFhJQbUDJ1HSUnGGMCSN37yjoyyeotg/tD/ 56Wb6umlY6y5sov3sArlIJQ= X-Google-Smtp-Source: ABdhPJx0PBJyIcjSuMZcCKzSpC48ofRcK+Nd4E9AAl/1wQ1BLVEe4QrKJXsxg1zib5CJXZufx45ISA== X-Received: by 2002:a05:6a00:856:b0:50a:431b:c298 with SMTP id q22-20020a056a00085600b0050a431bc298mr1521546pfk.75.1650069204901; Fri, 15 Apr 2022 17:33:24 -0700 (PDT) Received: from olv-glaptop3.lan ([2601:647:4400:452:4301:d32e:a8ad:adbf]) by smtp.gmail.com with ESMTPSA id oo17-20020a17090b1c9100b001bf0ccc59c2sm9900249pjb.16.2022.04.15.17.33.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 17:33:24 -0700 (PDT) From: Chia-I Wu To: freedreno@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Sean Paul , Abhinav Kumar , David Airlie , linux-arm-msm@vger.kernel.org, Daniel Vetter , Rob Clark Subject: [PATCH 1/3] drm/msm: remove explicit devfreq status reset Date: Fri, 15 Apr 2022 17:33:12 -0700 Message-Id: <20220416003314.59211-1-olvaffe@gmail.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It is redundant since commit 7c0ffcd40b16 ("drm/msm/gpu: Respect PM QoS constraints") because dev_pm_qos_update_request triggers get_dev_status. Signed-off-by: Chia-I Wu Cc: Rob Clark --- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index 12641616acd3..317a95d42922 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -224,7 +224,6 @@ void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor) void msm_devfreq_active(struct msm_gpu *gpu) { struct msm_gpu_devfreq *df = &gpu->devfreq; - struct devfreq_dev_status status; unsigned int idle_time; if (!has_devfreq(gpu)) @@ -248,12 +247,6 @@ void msm_devfreq_active(struct msm_gpu *gpu) dev_pm_qos_update_request(&df->idle_freq, PM_QOS_MAX_FREQUENCY_DEFAULT_VALUE); - - /* - * Reset the polling interval so we aren't inconsistent - * about freq vs busy/total cycles - */ - msm_devfreq_get_dev_status(&gpu->pdev->dev, &status); } From patchwork Sat Apr 16 00:33:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chia-I Wu X-Patchwork-Id: 562929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5D61C433EF for ; Sat, 16 Apr 2022 00:36:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229445AbiDPAjL (ORCPT ); Fri, 15 Apr 2022 20:39:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229630AbiDPAjL (ORCPT ); Fri, 15 Apr 2022 20:39:11 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 125E9EE4FA for ; Fri, 15 Apr 2022 17:36:36 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id u5-20020a17090a6a8500b001d0b95031ebso2498175pjj.3 for ; Fri, 15 Apr 2022 17:36:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6AjOHVLmy++hjINXRHfH8cU0LeusCvQBspyIU/e7Ce0=; b=V6AbaaBfcxy6hGk0b1qQITAALp/O74mu0yqKHh9E0usgncipduK6ZimZFu/NKaizWR PmC1Qc2RAQDfBFy1Wo2nI5k2T5I8UkvjuwaHca8MgHf8RoqeZgq5aGRolU7vIJ+zPbG2 VSe840ftq8IFxDyWMMYHnfZekGmHolMArsU2Lg2lFz3YEHMH9mTHS7mMLFfuDLTLDnVP 81VQWMdzXKQnQmAJQ/xyDiycuqriaFKt50p2yjMANK6RiE4dLL5+1D/HbPYgYrW4cXyC H2skzngtvsM9Y3P5k9/FdV2PWM6VnR3tY0ppjiy9o8WA9dpGpfhX8B5JYwrAGwz53Mcu buYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6AjOHVLmy++hjINXRHfH8cU0LeusCvQBspyIU/e7Ce0=; b=pQPQ0nx7oNfVlTi1uEG0vc+9gPOfAuANkj6cwO2jT3AYBNOc0cvXtELFSaVX6JGlGk txjokVcCzm6Pt4cHIce+nhMIO+vFkAIqaoxha2dpkRfZxJnpDc9Gka6F12poZId8HVdP 0YIDn768x6jrvRo11Y7/87TafqFm9za/RempoEdy0fMMGdR6fMKrVMVpoWgZ8QKhqYHc bhBBEu2u57L+qE/6iIqrcRqT+3rbQ99LJZ+8L6H3BwphbGpIRuPJHtoj7E3Kk4zihaLt cY0Ao+FqwPfmgO9bgedm06Ftt3+FXGYAedsQPGkh33Z4PPAM6nxJFV9ziC7lznLYuuf3 chVA== X-Gm-Message-State: AOAM533eXcwRCJ/TVyYhURoHjZlZI8tOTVMew+EqXL58fgmXBU8/+1Nx 4ttWL6ADJGUfuLEsMvdIeOc= X-Google-Smtp-Source: ABdhPJyBrqZl5LOp0s0qaGDNrkbxcqh3vZYA7lMg4NOvJNi65Ee61pXXMUbe3iypkScV4FihsWN+PQ== X-Received: by 2002:a17:903:22d0:b0:158:9d42:6af6 with SMTP id y16-20020a17090322d000b001589d426af6mr1186928plg.159.1650069207513; Fri, 15 Apr 2022 17:33:27 -0700 (PDT) Received: from olv-glaptop3.lan ([2601:647:4400:452:4301:d32e:a8ad:adbf]) by smtp.gmail.com with ESMTPSA id oo17-20020a17090b1c9100b001bf0ccc59c2sm9900249pjb.16.2022.04.15.17.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 17:33:27 -0700 (PDT) From: Chia-I Wu To: freedreno@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Sean Paul , Abhinav Kumar , David Airlie , linux-arm-msm@vger.kernel.org, Daniel Vetter , Rob Clark Subject: [PATCH 2/3] drm/msm: simplify gpu_busy callback Date: Fri, 15 Apr 2022 17:33:13 -0700 Message-Id: <20220416003314.59211-2-olvaffe@gmail.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog In-Reply-To: <20220416003314.59211-1-olvaffe@gmail.com> References: <20220416003314.59211-1-olvaffe@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move tracking and busy time calculation to msm_devfreq_get_dev_status. Signed-off-by: Chia-I Wu Cc: Rob Clark --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 19 ++++++---------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++-------- drivers/gpu/drm/msm/msm_gpu.h | 9 +++----- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 32 ++++++++++++++++++++++----- 4 files changed, 41 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 407f50a15faa..217615e0e850 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1662,28 +1662,23 @@ static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu) return a5xx_gpu->cur_ring; } -static unsigned long a5xx_gpu_busy(struct msm_gpu *gpu) +static u64 a5xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) { - u64 busy_cycles, busy_time; + u64 busy_cycles; /* Only read the gpu busy if the hardware is already active */ - if (pm_runtime_get_if_in_use(&gpu->pdev->dev) == 0) + if (pm_runtime_get_if_in_use(&gpu->pdev->dev) == 0) { + *out_sample_rate = 1; return 0; + } busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO, REG_A5XX_RBBM_PERFCTR_RBBM_0_HI); - - busy_time = busy_cycles - gpu->devfreq.busy_cycles; - do_div(busy_time, clk_get_rate(gpu->core_clk) / 1000000); - - gpu->devfreq.busy_cycles = busy_cycles; + *out_sample_rate = clk_get_rate(gpu->core_clk); pm_runtime_put(&gpu->pdev->dev); - if (WARN_ON(busy_time > ~0LU)) - return ~0LU; - - return (unsigned long)busy_time; + return busy_cycles; } static uint32_t a5xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index ccc4fcf7a630..fba6259395dd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1649,12 +1649,14 @@ static void a6xx_destroy(struct msm_gpu *gpu) kfree(a6xx_gpu); } -static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) +static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - u64 busy_cycles, busy_time; + u64 busy_cycles; + /* 19.2MHz */ + *out_sample_rate = 19200000; /* Only read the gpu busy if the hardware is already active */ if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0) @@ -1664,17 +1666,10 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); - busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10; - do_div(busy_time, 192); - - gpu->devfreq.busy_cycles = busy_cycles; pm_runtime_put(a6xx_gpu->gmu.dev); - if (WARN_ON(busy_time > ~0LU)) - return ~0LU; - - return (unsigned long)busy_time; + return busy_cycles; } static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 02419f2ca2bc..389c6dab751b 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -62,7 +62,7 @@ struct msm_gpu_funcs { /* for generation specific debugfs: */ void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor); #endif - unsigned long (*gpu_busy)(struct msm_gpu *gpu); + u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate); struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu); int (*gpu_state_put)(struct msm_gpu_state *state); unsigned long (*gpu_get_freq)(struct msm_gpu *gpu); @@ -106,11 +106,8 @@ struct msm_gpu_devfreq { struct dev_pm_qos_request boost_freq; /** - * busy_cycles: - * - * Used by implementation of gpu->gpu_busy() to track the last - * busy counter value, for calculating elapsed busy cycles since - * last sampling period. + * busy_cycles: Last busy counter value, for calculating elapsed busy + * cycles since last sampling period. */ u64 busy_cycles; diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index 317a95d42922..f531015107c3 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -49,18 +49,38 @@ static unsigned long get_freq(struct msm_gpu *gpu) return clk_get_rate(gpu->core_clk); } -static int msm_devfreq_get_dev_status(struct device *dev, +static void get_raw_dev_status(struct msm_gpu *gpu, struct devfreq_dev_status *status) { - struct msm_gpu *gpu = dev_to_gpu(dev); + struct msm_gpu_devfreq *df = &gpu->devfreq; + u64 busy_cycles, busy_time; + unsigned long sample_rate; ktime_t time; status->current_frequency = get_freq(gpu); - status->busy_time = gpu->funcs->gpu_busy(gpu); - + busy_cycles = gpu->funcs->gpu_busy(gpu, &sample_rate); time = ktime_get(); - status->total_time = ktime_us_delta(time, gpu->devfreq.time); - gpu->devfreq.time = time; + + busy_time = busy_cycles - df->busy_cycles; + status->total_time = ktime_us_delta(time, df->time); + + df->busy_cycles = busy_cycles; + df->time = time; + + busy_time *= USEC_PER_SEC; + do_div(busy_time, sample_rate); + if (WARN_ON(busy_time > ~0LU)) + busy_time = ~0LU; + + status->busy_time = busy_time; +} + +static int msm_devfreq_get_dev_status(struct device *dev, + struct devfreq_dev_status *status) +{ + struct msm_gpu *gpu = dev_to_gpu(dev); + + get_raw_dev_status(gpu, status); return 0; } From patchwork Sat Apr 16 00:33:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chia-I Wu X-Patchwork-Id: 562654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 215BDC433F5 for ; Sat, 16 Apr 2022 00:36:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229664AbiDPAjS (ORCPT ); Fri, 15 Apr 2022 20:39:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229630AbiDPAjQ (ORCPT ); Fri, 15 Apr 2022 20:39:16 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1267FEF0B6 for ; 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Fri, 15 Apr 2022 17:33:32 -0700 (PDT) Received: from olv-glaptop3.lan ([2601:647:4400:452:4301:d32e:a8ad:adbf]) by smtp.gmail.com with ESMTPSA id oo17-20020a17090b1c9100b001bf0ccc59c2sm9900249pjb.16.2022.04.15.17.33.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 17:33:32 -0700 (PDT) From: Chia-I Wu To: freedreno@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Sean Paul , Abhinav Kumar , David Airlie , linux-arm-msm@vger.kernel.org, Daniel Vetter , Rob Clark Subject: [PATCH 3/3] drm/msm: return the average load over the polling period Date: Fri, 15 Apr 2022 17:33:14 -0700 Message-Id: <20220416003314.59211-3-olvaffe@gmail.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog In-Reply-To: <20220416003314.59211-1-olvaffe@gmail.com> References: <20220416003314.59211-1-olvaffe@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org simple_ondemand interacts poorly with clamp_to_idle. It only looks at the load since the last get_dev_status call, while it should really look at the load over polling_ms. When clamp_to_idle true, it almost always picks the lowest frequency on active because the gpu is idle between msm_devfreq_idle/msm_devfreq_active. This logic could potentially be moved into devfreq core. Fixes: 7c0ffcd40b16 ("drm/msm/gpu: Respect PM QoS constraints") Signed-off-by: Chia-I Wu Cc: Rob Clark --- drivers/gpu/drm/msm/msm_gpu.h | 3 ++ drivers/gpu/drm/msm/msm_gpu_devfreq.c | 60 ++++++++++++++++++++++++++- 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 389c6dab751b..143c56f5185b 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -117,6 +118,8 @@ struct msm_gpu_devfreq { /** idle_time: Time of last transition to idle: */ ktime_t idle_time; + struct devfreq_dev_status average_status; + /** * idle_work: * diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index f531015107c3..d2539ca78c29 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -9,6 +9,7 @@ #include #include +#include #include /* @@ -75,12 +76,69 @@ static void get_raw_dev_status(struct msm_gpu *gpu, status->busy_time = busy_time; } +static void update_average_dev_status(struct msm_gpu *gpu, + const struct devfreq_dev_status *raw) +{ + struct msm_gpu_devfreq *df = &gpu->devfreq; + const u32 polling_ms = df->devfreq->profile->polling_ms; + const u32 max_history_ms = polling_ms * 11 / 10; + struct devfreq_dev_status *avg = &df->average_status; + u64 avg_freq; + + /* simple_ondemand governor interacts poorly with gpu->clamp_to_idle. + * When we enforce the constraint on idle, it calls get_dev_status + * which would normally reset the stats. When we remove the + * constraint on active, it calls get_dev_status again where busy_time + * would be 0. + * + * To remedy this, we always return the average load over the past + * polling_ms. + */ + + /* raw is longer than polling_ms or avg has no history */ + if (div_u64(raw->total_time, USEC_PER_MSEC) >= polling_ms || + !avg->total_time) { + *avg = *raw; + return; + } + + /* Truncate the oldest history first. + * + * Because we keep the history with a single devfreq_dev_status, + * rather than a list of devfreq_dev_status, we have to assume freq + * and load are the same over avg->total_time. We can scale down + * avg->busy_time and avg->total_time by the same factor to drop + * history. + */ + if (div_u64(avg->total_time + raw->total_time, USEC_PER_MSEC) >= + max_history_ms) { + const u32 new_total_time = polling_ms * USEC_PER_MSEC - + raw->total_time; + avg->busy_time = div_u64( + mul_u32_u32(avg->busy_time, new_total_time), + avg->total_time); + avg->total_time = new_total_time; + } + + /* compute the average freq over avg->total_time + raw->total_time */ + avg_freq = mul_u32_u32(avg->current_frequency, avg->total_time); + avg_freq += mul_u32_u32(raw->current_frequency, raw->total_time); + do_div(avg_freq, avg->total_time + raw->total_time); + + avg->current_frequency = avg_freq; + avg->busy_time += raw->busy_time; + avg->total_time += raw->total_time; +} + static int msm_devfreq_get_dev_status(struct device *dev, struct devfreq_dev_status *status) { struct msm_gpu *gpu = dev_to_gpu(dev); + struct devfreq_dev_status raw; - get_raw_dev_status(gpu, status); + get_raw_dev_status(gpu, &raw); + update_average_dev_status(gpu, &raw); + *status = gpu->devfreq.average_status; return 0; }