From patchwork Mon Apr 18 10:20:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswath Govindraju X-Patchwork-Id: 563738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5048AC4332F for ; Mon, 18 Apr 2022 10:21:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237650AbiDRKXk (ORCPT ); Mon, 18 Apr 2022 06:23:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237653AbiDRKXj (ORCPT ); Mon, 18 Apr 2022 06:23:39 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37EFD192A2; Mon, 18 Apr 2022 03:21:01 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23IAKqsC036644; Mon, 18 Apr 2022 05:20:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650277252; bh=GETV6o1XWx9p5QEWsFgu7ckK5R4K843mHXCaKcojxGs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VBPl4xE7KE82wKBVYiUFXUjpK1BV36uf4AVwOeksL8+zEsZRtz/wjOiSks2I/RzUT PpdsOLyVo5FuP102pR38k5oZM4egBMegI4S95baNBxtrPsuXtQ4PW6kHKVas+MohfW 7ggirrvY2Po87NJ0+y19EGBFUErsmdIFYcOksy3w= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23IAKqDk070509 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 18 Apr 2022 05:20:52 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 18 Apr 2022 05:20:52 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 18 Apr 2022 05:20:52 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23IAKgTZ021324; Mon, 18 Apr 2022 05:20:49 -0500 From: Aswath Govindraju CC: Vignesh Raghavendra , Kishon Vijay Abraham I , Aswath Govindraju , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Adrian Hunter , , , Subject: [PATCH 1/2] dt-bindings: mmc: sdhci-am654: Add flag to force setting to TESTCD bit Date: Mon, 18 Apr 2022 15:50:39 +0530 Message-ID: <20220418102040.4993-2-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220418102040.4993-1-a-govindraju@ti.com> References: <20220418102040.4993-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The ARASAN MMC controller on Keystone 3 class of devices needs the SDCD line to be connected for proper functioning. Similar to the issue pointed out in sdhci-of-arasan.c driver, commit 3794c542641f ("mmc: sdhci-of-arasan: Set controller to test mode when no CD bit"). In cases where SDCD line is not connected, driver support has been added to force the controller into test mode and set the TESTCD bit. In order to implement this quirk the driver uses "ti,fails-without-test-cd" flag from the device tree node. Therefore, update the bindings to document the above. Signed-off-by: Aswath Govindraju --- Documentation/devicetree/bindings/mmc/sdhci-am654.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml index 0566493c4def..0ab07759b472 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml @@ -186,6 +186,13 @@ properties: description: Clock Delay Buffer Select $ref: "/schemas/types.yaml#/definitions/uint32" + ti,fails-without-test-cd: + $ref: /schemas/types.yaml#/definitions/flag + description: + When present, indicates that the CD line is not connected + and the controller is required to be forced into Test mode + to set the TESTCD bit. + required: - compatible - reg From patchwork Mon Apr 18 10:20:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswath Govindraju X-Patchwork-Id: 563249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38670C433FE for ; Mon, 18 Apr 2022 10:21:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237659AbiDRKXn (ORCPT ); Mon, 18 Apr 2022 06:23:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237660AbiDRKXm (ORCPT ); Mon, 18 Apr 2022 06:23:42 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F161913E2A; Mon, 18 Apr 2022 03:21:03 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23IAL01b036713; Mon, 18 Apr 2022 05:21:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650277260; bh=5vlzWnykhMTqczae+yu/fb/SoPEuuYZhc9mFRVH1Lro=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=u9tmqR2ke8Q9Od47uSx9YIuT8wGMdf7a2yIr6Z5TEIN+n/8V/TUEwAyAwmCyuBk+t xOVkUu0V5H4JpFXxfPdoDPUbzucvOl9Wc+CE17smusDEYK7V7H4oVTgk3UlC8/R+6e BqGvTAfCs9tLlL54/bOEtbQ+eSeIL4Wh4S/t4ZCI= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23IAL0Ol070574 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 18 Apr 2022 05:21:00 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Mon, 18 Apr 2022 05:21:00 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Mon, 18 Apr 2022 05:21:00 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23IAKgTa021324; Mon, 18 Apr 2022 05:20:57 -0500 From: Aswath Govindraju CC: Vignesh Raghavendra , Kishon Vijay Abraham I , Aswath Govindraju , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Adrian Hunter , , , Subject: [PATCH 2/2] drivers: mmc: sdhci_am654: Add the quirk to set TESTCD bit Date: Mon, 18 Apr 2022 15:50:40 +0530 Message-ID: <20220418102040.4993-3-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220418102040.4993-1-a-govindraju@ti.com> References: <20220418102040.4993-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Vignesh Raghavendra The ARASAN MMC controller on Keystone 3 class of devices need the SDCD line to be connected for proper functioning. Similar to the issue pointed out in sdhci-of-arasan.c driver, commit 3794c542641f ("mmc: sdhci-of-arasan: Set controller to test mode when no CD bit"). In cases where this can't be connected, add a quirk to force the controller into test mode and set the TESTCD bit. Use the flag "ti,fails-without-test-cd", to implement this above quirk when required. Signed-off-by: Vignesh Raghavendra Signed-off-by: Aswath Govindraju Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/mmc/host/sdhci_am654.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index e54fe24d47e7..c36b969ed1b6 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -147,6 +147,9 @@ struct sdhci_am654_data { int drv_strength; int strb_sel; u32 flags; + u32 quirks; + +#define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) }; struct sdhci_am654_driver_data { @@ -369,6 +372,21 @@ static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) } } +void sdhci_am654_reset(struct sdhci_host *host, u8 mask) +{ + u8 ctrl; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); + + sdhci_reset(host, mask); + + if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + } +} + static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) { struct sdhci_host *host = mmc_priv(mmc); @@ -500,7 +518,7 @@ static struct sdhci_ops sdhci_j721e_4bit_ops = { .set_clock = sdhci_j721e_4bit_set_clock, .write_b = sdhci_am654_write_b, .irq = sdhci_am654_cqhci_irq, - .reset = sdhci_reset, + .reset = sdhci_am654_reset, }; static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { @@ -719,6 +737,9 @@ static int sdhci_am654_get_of_property(struct platform_device *pdev, device_property_read_u32(dev, "ti,clkbuf-sel", &sdhci_am654->clkbuf_sel); + if (device_property_read_bool(dev, "ti,fails-without-test-cd")) + sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; + sdhci_get_of_property(pdev); return 0;