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[81.47.145.58]) by smtp.gmail.com with ESMTPSA id h12sm28878113wma.48.2018.12.17.01.46.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Dec 2018 01:46:42 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, sboyd@kernel.org, will.deacon@arm.com, mturquette@baylibre.com, jassisinghbrar@gmail.com Cc: bjorn.andersson@linaro.org, vkoul@kernel.org, niklas.cassel@linaro.org, sibis@codeaurora.org, georgi.djakov@linaro.org, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 04/13] dt-bindings: mailbox: qcom: Add clock-name optional property Date: Mon, 17 Dec 2018 10:46:21 +0100 Message-Id: <1545039990-19984-5-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When the APCS clock is registered (platform dependent), it retrieves its parent names from hardcoded values in the driver. The following commit allows the DT node to provide such clock names to the platform data based clock driver therefore avoiding having to explicitly embed those names in the clock driver source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- .../bindings/mailbox/qcom,apcs-kpss-global.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt index 1232fc9..f252439 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -23,6 +23,10 @@ platforms. Value type: Definition: phandle to the input PLL, which feeds the APCS mux/divider + Usage: required if #clock-names property is present + Value type: + Definition: phandles to the two parent clocks of the clock driver. + - #mbox-cells: Usage: required Value type: @@ -33,6 +37,12 @@ platforms. Value type: Definition: as described in clock.txt, must be 0 +- clock-names: + Usage: required if the platform data based clock driver needs to + retrieve the parent clock names from device tree. + This will requires two mandatory clocks to be defined. + Value type: + Definition: must be "aux" and "pll" = EXAMPLE The following example describes the APCS HMSS found in MSM8996 and part of the @@ -65,3 +75,14 @@ Below is another example of the APCS binding on MSM8916 platforms: clocks = <&a53pll>; #clock-cells = <0>; }; + +Below is another example of the APCS binding on QCS404 platforms: + + apcs_glb: mailbox@b011000 { + compatible = "qcom,qcs404-apcs-apps-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>; + clock-names = "aux", "pll"; + #clock-cells = <0>; + }; From patchwork Mon Dec 17 09:46:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 153963 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2265828ljp; Mon, 17 Dec 2018 01:46:49 -0800 (PST) X-Google-Smtp-Source: AFSGD/UsfdfEp14l03x8ldngab4wuOO3ymoAdnLMDsxpLt/Fj0PgnnofcgadGyzuJlEi4XQohoqN X-Received: by 2002:a63:8d44:: with SMTP id z65mr11640372pgd.57.1545040008939; Mon, 17 Dec 2018 01:46:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545040008; cv=none; d=google.com; s=arc-20160816; b=Udo1jMYVpRFLSvgHRzXyaKefUJH8uTmzDePclx1qaYI9rUKiabI8xsTMFiYdOpRx4p hMusQkL4KQiB3Ll6SGLyMfAfL5D+MSLm+bGj7FYbQ9pfBAtGDLLup3Pk4FfJXI8ZwhCP O0QzAnNSZq8/A8UJWlqtHZDjaUyevnUQyHLMZSHm/OYk05SWLgPX2OfTO/oC9x9jx/TJ YhZ/yWkoQeyQENNu3BtRz/0g2bH+Aw2oqxNJvb1L38Ogz/06QNQSNwGTv6i0AN4Krpg3 fb0qKglT4N5UPNOuWEIibdf9HgM+RJeG74WK6VbTCN6kdtdjK3YSdJGYwFF5DG+85hze vhhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=rPu/KTYynL2hZ7Udac90NfGfOmFb5CPU0go+pwum/Ko=; b=i8MBNLWRzc8YC4nX9WPaWv7BnIVmLiGOrnubwY01rP1I3AibmSgP+nfAVwPmJkHpQf eoHyRrpULj16/HCT2HFM7EB5oQHURpfhAH78P61AcxkufFTSdIGKXxWLIwWEPAcmIpfp HOSeuj78tLc1h4goiuW9BBAdsmQnPESapY/elrLL90g6qILI3FsTwfV+k2UmDDLMNI0q UxiCNZ6YE4DRkYdRGeSn+S90MxTtrff5L9fXYijkvuR57JC1pdSonPOTtNeRP4QXPJ1q /RJNzYW3aunC/8XAWI8hrDX6hXuylcmTLCGK5hwHU86BlTNvMJ40ygZeZV25ZLIpRYlo jGjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GJ94LMcb; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[81.47.145.58]) by smtp.gmail.com with ESMTPSA id h12sm28878113wma.48.2018.12.17.01.46.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Dec 2018 01:46:44 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, sboyd@kernel.org, will.deacon@arm.com, mturquette@baylibre.com, jassisinghbrar@gmail.com Cc: bjorn.andersson@linaro.org, vkoul@kernel.org, niklas.cassel@linaro.org, sibis@codeaurora.org, georgi.djakov@linaro.org, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 05/13] clk: qcom: apcs-msm8916: get parent clock names from DT Date: Mon, 17 Dec 2018 10:46:22 +0100 Message-Id: <1545039990-19984-6-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow accessing the parent clock names required for the driver operation by using the device tree node. This permits extending the driver to other platforms without having to modify its source code. For backwards compatibility leave previous values as default. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/apcs-msm8916.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) -- 2.7.4 diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c index a6c89a3..2453242 100644 --- a/drivers/clk/qcom/apcs-msm8916.c +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -19,7 +19,7 @@ static const u32 gpll0_a53cc_map[] = { 4, 5 }; -static const char * const gpll0_a53cc[] = { +static const char *gpll0_a53cc[] = { "gpll0_vote", "a53pll", }; @@ -50,17 +50,39 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) struct regmap *regmap; struct clk_init_data init = { }; int ret = -ENODEV; + struct clk_bulk_data pclks[] = { + [0] = { .id = "aux", .clk = NULL }, + [1] = { .id = "pll", .clk = NULL }, + }; regmap = dev_get_regmap(parent, NULL); if (!regmap) { dev_err(dev, "failed to get regmap: %d\n", ret); return ret; } - a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL); if (!a53cc) return -ENOMEM; + /* check if the parent names are present in the device tree */ + ret = devm_clk_bulk_get(parent, ARRAY_SIZE(pclks), pclks); + if (ret == -EPROBE_DEFER) + return ret; + + if (!ret) { + gpll0_a53cc[0] = __clk_get_name(pclks[0].clk); + gpll0_a53cc[1] = __clk_get_name(pclks[1].clk); + a53cc->pclk = pclks[1].clk; + } else { + /* support old binding where only pll was explicitily defined */ + a53cc->pclk = devm_clk_get(parent, NULL); + if (IS_ERR(a53cc->pclk)) { + ret = PTR_ERR(a53cc->pclk); + dev_err(dev, "failed to get clk: %d\n", ret); + return ret; + } + } + init.name = "a53mux"; init.parent_names = gpll0_a53cc; init.num_parents = ARRAY_SIZE(gpll0_a53cc); @@ -76,13 +98,6 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) a53cc->src_shift = 8; a53cc->parent_map = gpll0_a53cc_map; - a53cc->pclk = devm_clk_get(parent, NULL); - if (IS_ERR(a53cc->pclk)) { - ret = PTR_ERR(a53cc->pclk); - dev_err(dev, "failed to get clk: %d\n", ret); - return ret; - } - a53cc->clk_nb.notifier_call = a53cc_notifier_cb; ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb); if (ret) { From patchwork Mon Dec 17 09:46:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 153964 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2265857ljp; Mon, 17 Dec 2018 01:46:52 -0800 (PST) X-Google-Smtp-Source: AFSGD/UTFcjTyKP0WPRP67V7iKjWf1oqmzLbUxDaepdVkEPOnycC0ZjqG/QmiUgpTAOS9yjeRvXp X-Received: by 2002:a63:f109:: with SMTP id f9mr11469960pgi.286.1545040011917; Mon, 17 Dec 2018 01:46:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545040011; cv=none; d=google.com; s=arc-20160816; b=JWIgmXos+cEirG37d3uA3o5S/yJpTelqVJE9x3TtDgfCRCynGsP1OG8OU98HVO7W2E Ap4VUHzcVfTR4oR6/FGt1iZ4rPYYktVMW65ayNBn/bdU8BfACBrUD8zZVShP8W1FPbvi k2dJ2ivX43OwwuLSq2P+T0Xj27G2571vCmBJc03cnxKF5GkOvHFemVGZU0PRbQTh5rmI MsywJUidhhBYmMmBXIdU6dpox6PAK08T6yE1wc2CEe3vSzg7ZjsjUeZsAHEeqtEE4psk rkIsk15dK0GrUPwDKgx11zxysJpi8ICPL3rECVJVQKE0K36HnQuMth3N40WtDKBtIapC Xkyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=CrsB9vDQWUxmYDFtafFb8lMIaGmRCz/1Apw6ozfisK4=; b=aH+lO++2puv1G8LahiMd8LGg64C1PVXwq2zOQjyJKD7yRvKW8S4RFZNDAtm5Zt+zf1 tqkxUeXP5S+ZD+XKFCmHJXGBmX/Jouqv9DpMzxmIRwl78fwJR1ev32JQHeaM5MdSok7K uKHEK/5NeL/MQqJqgPhoWVfHTHcUsYjImp6ItUf2ufmuElX7PWVy4Ai6LCz+o8ZVsQYk IK4V0qpyLw5WtkaBSkaA4uUCAE6vAonkzlGtdJKayBx3Hh9lA3DqY9HKm/JufdDI5flC EjAUCUGbgEauaO/50GpMm/CdPd0vXq9rcbiLskfUDErnNxIzJ6g7YD45XO+s2vZIZfzR BWdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AnLMqzqw; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[81.47.145.58]) by smtp.gmail.com with ESMTPSA id h12sm28878113wma.48.2018.12.17.01.46.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Dec 2018 01:46:46 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, sboyd@kernel.org, will.deacon@arm.com, mturquette@baylibre.com, jassisinghbrar@gmail.com Cc: bjorn.andersson@linaro.org, vkoul@kernel.org, niklas.cassel@linaro.org, sibis@codeaurora.org, georgi.djakov@linaro.org, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 06/13] clk: qcom: hfpll: get parent clock names from DT Date: Mon, 17 Dec 2018 10:46:23 +0100 Message-Id: <1545039990-19984-7-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow accessing the parent clock name required for the driver operation using the device tree node. This permits extending the driver to other platforms without having to modify its source code. For backwards compatibility leave the previous value as default. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/hfpll.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.7.4 Reviewed-by: Bjorn Andersson diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c index a6de7101..87b7f46 100644 --- a/drivers/clk/qcom/hfpll.c +++ b/drivers/clk/qcom/hfpll.c @@ -52,6 +52,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev) void __iomem *base; struct regmap *regmap; struct clk_hfpll *h; + struct clk *pclk; struct clk_init_data init = { .parent_names = (const char *[]){ "xo" }, .num_parents = 1, @@ -75,6 +76,13 @@ static int qcom_hfpll_probe(struct platform_device *pdev) 0, &init.name)) return -ENODEV; + /* get parent clock from device tree (optional) */ + pclk = devm_clk_get(dev, "xo"); + if (!IS_ERR(pclk)) + init.parent_names = (const char *[]){ __clk_get_name(pclk) }; + else if (PTR_ERR(pclk) == -EPROBE_DEFER) + return -EPROBE_DEFER; + h->d = &hdata; h->clkr.hw.init = &init; spin_lock_init(&h->lock); From patchwork Mon Dec 17 09:46:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 153965 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2265864ljp; Mon, 17 Dec 2018 01:46:52 -0800 (PST) X-Google-Smtp-Source: AFSGD/UTZ2CGabV9NOML4AszU+514d0GCZph9vhOIF08zrBMe9+zcJGnR/9lRrndtJokajN+xnNm X-Received: by 2002:a17:902:6b83:: with SMTP id p3mr12042025plk.118.1545040012518; Mon, 17 Dec 2018 01:46:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545040012; cv=none; d=google.com; s=arc-20160816; b=Cv04/g831sj2JBJJCjcTziYDBrVGBWSh8z/0BtmeCfx3+h9b9aTD3Jjlq/007GnCw0 h1g1FnT2x+weaz2KOnijOQjfEQwaAf9HHhmdoNzzOHaGZYhw47i0a4ofCo8JgP948bwe +A/5KYpnX/3ws0zPadRmFZuBxJgU856ftKcZsox5ae+pjM3onJsTbNZUaQUnhhVh5HHi Y035/8IKmx4Sbz8fzAPGp0qHI5esYtQ+nGN7c1olkS2OXK/XoTq3isPkmu/tX9T2B/Y2 +KcjdR3pB3Cx5dTzUq8IkPJIg+Tx3RJ5q1lXxnCnEynN4Y9xCQaa0rhH+fzoUjXxiwdK 2MiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=jVpmDAqKxQ/sn4lpMw47fV7HcMyJcxjw7jbklh3qbPU=; b=n/Ddhi9sm+3xG2buqdp1Rk8NcGPYdQ3TB9mXuxPAwBaohio3ijZxBs3UBztRxZ8XSo 759WPr0FCgtAlvBaSVBebtrPCETGr2Uh4TanIynl1DovaxmLosQ0GvUIEZafUVu9CfcA 3oo2z6V/JUfGx/z9zMQUJNciMN2V/OfTjHIUki4DKDnumHIy5CoT/wlCN0gaup3N+llO IQe1qlKX34MrWnLftamu6kU8ivr6lftEpw+Fg56/nN08HManVEmTXuPP1e0Q/fHrSGPg vbyF7stfLWS/Uf8wp9n72e6096cTlCYVGGZ7W1hoyTpPCKbymuQmFBX62BOCXZSFhfz8 HL8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M4fmN2UP; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[81.47.145.58]) by smtp.gmail.com with ESMTPSA id h12sm28878113wma.48.2018.12.17.01.46.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Dec 2018 01:46:48 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, sboyd@kernel.org, will.deacon@arm.com, mturquette@baylibre.com, jassisinghbrar@gmail.com Cc: bjorn.andersson@linaro.org, vkoul@kernel.org, niklas.cassel@linaro.org, sibis@codeaurora.org, georgi.djakov@linaro.org, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 07/13] clk: qcom: hfpll: register as clock provider Date: Mon, 17 Dec 2018 10:46:24 +0100 Message-Id: <1545039990-19984-8-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Make the output of the high frequency pll a clock provider. On the QCS404 this PLL controls cpu frequency scaling. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/hfpll.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Bjorn Andersson diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c index 87b7f46..0ffed0d 100644 --- a/drivers/clk/qcom/hfpll.c +++ b/drivers/clk/qcom/hfpll.c @@ -53,6 +53,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev) struct regmap *regmap; struct clk_hfpll *h; struct clk *pclk; + int ret; struct clk_init_data init = { .parent_names = (const char *[]){ "xo" }, .num_parents = 1, @@ -87,7 +88,14 @@ static int qcom_hfpll_probe(struct platform_device *pdev) h->clkr.hw.init = &init; spin_lock_init(&h->lock); - return devm_clk_register_regmap(&pdev->dev, &h->clkr); + ret = devm_clk_register_regmap(dev, &h->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + return ret; + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &h->clkr.hw); } static struct platform_driver qcom_hfpll_driver = { From patchwork Mon Dec 17 09:46:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 153971 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2266312ljp; Mon, 17 Dec 2018 01:47:26 -0800 (PST) X-Google-Smtp-Source: AFSGD/WJNqeiy96AgbNZFwAaNPNmykq7NqdsYxXTVaiLCePalHscDqFdj/PZyNmwwxVdcFmcU7vf X-Received: by 2002:a62:37c3:: with SMTP id e186mr12544773pfa.251.1545040046339; Mon, 17 Dec 2018 01:47:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545040046; cv=none; d=google.com; s=arc-20160816; b=nrclwU80O8w24/5LktVyIws9OHi82vImhEEge0sQv3HemHv4muEV+HlayJ9Co5cotQ sPxCjRBvK3gy0Ph/GRe7d2YT999Jb61/WB1uOzRHmGioqPHnP7K2A+n6xDz16N/OjJfB x5cNi5IYTKR5AzLI4r84vbK8dbSZDxlkt67Wnc/oYOFOLN5OEljYUVZGgETS1j/xSsXP iEVa0RSrz8V14vHW1LNE2khKJPdqE8wZF9CWmYPsoicT3dUfEYsTzBuhUm+6dKhKXxEg LcX1lR3gijpKtzWXc7qxf3Aw65YqTGLjO/Vq4+WPPMXLuiSibKtHoRQRqTFTZnih4Wdv Ol2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=+HV8Nby8D/Sn6SAvkoxC802zTo0ynRqZ7bbip7gTvlU=; b=C1MMTiNNsoJUNN6oTDCRBtaiTd1Zc3DZV4sM9URBr89N6/Pc61G5Lt5SUPKxiuGmmq fcelfZ64V6P56iAHBkzoNtQyEPHgKlPt+liuT0HejTjiGcHukfUQQj8iE6pY8ZmRE/c7 0mEyVore6m8f6VEr4VRBqLXAKAHXxQ5zFxAhU7vX3iX7rf05Ho1K8eGQ9phD5LHjuez7 CCHirSkpZMeJ47Yvr0XJgy9bOYCtF/XncqvFBEIPHA1qv2M4LV1svmhW5fEjZUFR1Uzx QPNf8sE2QScuVR+DBdVoXRDjmX1ZC6lZ43SndE2JStRKYUH8qtqDm9Fyaq5VE2bAgbpy GVpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EVZfwTtj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[81.47.145.58]) by smtp.gmail.com with ESMTPSA id h12sm28878113wma.48.2018.12.17.01.46.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Dec 2018 01:46:50 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, sboyd@kernel.org, will.deacon@arm.com, mturquette@baylibre.com, jassisinghbrar@gmail.com Cc: bjorn.andersson@linaro.org, vkoul@kernel.org, niklas.cassel@linaro.org, sibis@codeaurora.org, georgi.djakov@linaro.org, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 08/13] clk: qcom: hfpll: CLK_IGNORE_UNUSED Date: Mon, 17 Dec 2018 10:46:25 +0100 Message-Id: <1545039990-19984-9-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and to keep the software model of the clock in line with reality, the framework transverses the clock tree and disables those clocks that were enabled by the firmware but have not been enabled by any device driver. If CPUFREQ is enabled, early during the system boot, it might attempt to change the CPU frequency ("set_rate"). If the HFPLL is selected as a provider, it will then change the rate for this clock. As boot continues, clk_disable_unused_subtree will run. Since it wont find a valid counter (enable_count) for a clock that is actually enabled it will attempt to disable it which will cause the CPU to stop. Notice that in this driver, calls to check whether the clock is enabled are routed via the is_enabled callback which queries the hardware. The following commit, rather than marking the clock critical and forcing the clock to be always enabled, addresses the above scenario making sure the clock is not disabled but it continues to rely on the firmware to enable the clock. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/hfpll.c | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c index 0ffed0d..9d92f5d 100644 --- a/drivers/clk/qcom/hfpll.c +++ b/drivers/clk/qcom/hfpll.c @@ -58,6 +58,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev) .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_ops_hfpll, + .flags = CLK_IGNORE_UNUSED, }; h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL); From patchwork Mon Dec 17 09:46:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 153967 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2265997ljp; Mon, 17 Dec 2018 01:47:04 -0800 (PST) X-Google-Smtp-Source: AFSGD/WJRvIwMhY68RVB3ehclqO/UIEHwemfzYi10WRY3P+jbYp6ivKP5Fy8xiqBjlCthKk+Eks9 X-Received: by 2002:a65:560e:: with SMTP id l14mr8349097pgs.168.1545040023892; Mon, 17 Dec 2018 01:47:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545040023; cv=none; d=google.com; s=arc-20160816; b=SAYjE9/J+D3HnGZ0MBtIQ5FSR24ijUMKxFWrEnxF7I1VlTNlV2xsGcIhX60RH2Tel0 Oej4Tbc5KZm/reDIhPUbCvk+9jFaKzC/Zcj3XJh0rH7Fm/EZZ0SXlgoskWQDn7MjcXwV RSvLj2zBrAQIYTb9LxYf+SF8DQiuIgUjpVQcXOEzzepu8DUL/7hgtKFCVUC5+DD74Qce 50Qksi086GUDItyyxgtysgg/RT320+7wo39hAifbqEVYl+ySCa9ia0/Q43yiWINSlSLL OM0cpAmC6QWuxZ3shnpU21PByOtS5toVpbqT2B31FySMh3KqjSDd0gRSpNQdjGBm1G00 jL7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=trBOZeUZ42tXHraYvTz2rphVlhKTWLVThNKSv6QZHLQ=; b=F+HO0BDRTqRjQ1w8YOP213etGkpmMTsRig8//nki6ETaa9fJTRoTT7+Uyx4T7XXnXK +MW4PXXA5+gtSclDlZb+Ihjcb/ES65dstru7g8U7PyBDdcXSsqVlTsuVyVM7G1XGX4bU 9tDZMIAwvGsVFRlz7jhqk4mL4gV6373dzqtg8lShLNKDp3bM5cpRTufb2L1J6ImUa0Zj DGB9mtBztEl6SX61sXJhxgaYXCQJ+CBVMhHqbVBpfeHEKJXLzsjU2jfp/68TTIF9n4UG l5U7vwRKnAfbpHKr7INIgjWC6+8l6tsCHWgc3U8T7WJ5xxtgDwQtJT5BqknQm34Z23I5 7FwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FoJRxte5; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w12si10115947ply.404.2018.12.17.01.47.03; Mon, 17 Dec 2018 01:47:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FoJRxte5; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732242AbeLQJrB (ORCPT + 6 others); Mon, 17 Dec 2018 04:47:01 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:41063 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732225AbeLQJrB (ORCPT ); Mon, 17 Dec 2018 04:47:01 -0500 Received: by mail-wr1-f65.google.com with SMTP id x10so11529170wrs.8 for ; Mon, 17 Dec 2018 01:46:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=trBOZeUZ42tXHraYvTz2rphVlhKTWLVThNKSv6QZHLQ=; b=FoJRxte5GxIjPmcVqIEkGM+x/BCDOU1h6ZYf63+VJDb0xLs7ryQZiUSVsBlpThKX4v PfyLuqhwQ6UN1N4rbF/rM5NLdCLQ6rat3x8M7claAyBkDAxKuY9R6FhHE2KAhflZaF1D 6sPl5ernAuDWw9WtWPeZVPzpwnpQ/nYk27+hQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=trBOZeUZ42tXHraYvTz2rphVlhKTWLVThNKSv6QZHLQ=; b=ezdReM4FFkxGffyQQjm3JOgB+/WyZxqbjN8eBU8ZrnTZWufoARDm+kWzhhYfG9fjbf SxOIRH9D9E3pUkyy2KYZoLDDklivIFgu/FUB5nLjIMfD0PoJ0in/7GWh4Xml6b4U3WRd mCR7gcsHFtGYUhlJSujVBgNsmFPfzpMachz/EOoXgYaTaxGdEFymciu6oNDcmfcstpcz 0ixFjG4iScyNmMie6jjwR4rVBel75xgBo1epUW4Gt5CMYtOqsTElFpgoyAQw3E0Cp1M0 2EoyUuvKpsTYScAIGs5G1emzmYanqJZQPlsGHXlbH47KrC2CNmspyox2sk6qN0bID5u9 Ma4g== X-Gm-Message-State: AA+aEWbfT9EmWPBFUq/AMCJfbQMBzz4uV1ynbsXyv9gTNnxzJwoM+GHo lI1k614+Cgola1TOHeBs0znP0w== X-Received: by 2002:a5d:488f:: with SMTP id g15mr9993063wrq.15.1545040019026; Mon, 17 Dec 2018 01:46:59 -0800 (PST) Received: from localhost.localdomain (58.red-81-47-145.staticip.rima-tde.net. [81.47.145.58]) by smtp.gmail.com with ESMTPSA id h12sm28878113wma.48.2018.12.17.01.46.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Dec 2018 01:46:58 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, sboyd@kernel.org, will.deacon@arm.com, mturquette@baylibre.com, jassisinghbrar@gmail.com Cc: bjorn.andersson@linaro.org, vkoul@kernel.org, niklas.cassel@linaro.org, sibis@codeaurora.org, georgi.djakov@linaro.org, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 12/13] arm64: dts: qcom: qcs404: Add cpufreq support Date: Mon, 17 Dec 2018 10:46:29 +0100 Message-Id: <1545039990-19984-13-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Support CPU frequency scaling on qcs404. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.7.4 Reviewed-by: Bjorn Andersson diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 2d9e70e..5a14887 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -30,6 +30,8 @@ reg = <0x100>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; }; CPU1: cpu@101 { @@ -38,6 +40,8 @@ reg = <0x101>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; }; CPU2: cpu@102 { @@ -46,6 +50,8 @@ reg = <0x102>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; }; CPU3: cpu@103 { @@ -54,6 +60,8 @@ reg = <0x103>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; }; L2_0: l2-cache {