From patchwork Thu Apr 21 18:27:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 565471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73A42C433EF for ; Thu, 21 Apr 2022 18:28:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1389167AbiDUSbL (ORCPT ); Thu, 21 Apr 2022 14:31:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1391324AbiDUSbK (ORCPT ); Thu, 21 Apr 2022 14:31:10 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01FE8FD1A; Thu, 21 Apr 2022 11:28:19 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id x191so5344525pgd.4; Thu, 21 Apr 2022 11:28:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WoeAeHW5+pgaqDzt+MQVIH8ZiTqwseT46QF5bHnKTlY=; b=qXLuFnoGfr2jkk+KCzjgqPXHHV4meayjHWJhhlSGh7uLIcIv7gOYM8FfxmcUwvX3fx jZ3/ViCTj5cneAUoM9EGbFf/ZNW5Fd+ycgDRM9k5XZzTey28EE/4qDK6QPbXX1ZYoTdJ acN+Xo8jEj9vfFJKg3EHQXnSF9FryTHr3t5XNQHRNQp7N572xCTvahqniwftriKI66/3 PyhQXRG2ZiR81w0c7YSFJgOsDVP+YC3MR9ESA4eZUSmiY7sZH78oJKbtjYkHyg+PK6V8 VRthEQlXzPyfzSEiTEONs99ctVvNr9KuvK/FjDWTqWJEr2Xg6wM+Gka/O5AMoy1Oaaci XSbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WoeAeHW5+pgaqDzt+MQVIH8ZiTqwseT46QF5bHnKTlY=; b=o7OX0kLHBLY/LuDv+qbl4zuIgSKbsZGkcA009n3WxTleWDgORjEkwWfvNBaJ+HWFQ/ 6hWoqfH+AYOT6c570G6J4KO8xD4pkEQM0XZ97H6FivoSFsx4Aam1/lgce2YWnsqQfxk8 n1cR0E1Le5oG+lTlOhRYUH/XGuE8m6Ce/F2qOjZvQoZI2VmQGrl09bMCmMRvbNamb4cn duiG+9ZdUVFZsSD0YyZ5AyGFKNS5+ta6z1A2Ih0WVUmZf7gSpz5IxdXJd575TpsuxJMQ ZRu74ENiqz3eJh34z3SDTQNIH6sPc30fyWvSRQ1wNAccZ42l9fCN4G15Hximy4f11Ndd Npnw== X-Gm-Message-State: AOAM530opdb727UbimXc4L+4K0SfKqyoOP/ld8kno4I8TnRiZVIV6TnO TLnBAyTVBxGD4QB2cIsNPmo= X-Google-Smtp-Source: ABdhPJxFDwn3JFhdVvifutf6KZ4J30lL9zq4foVLQ7EpaOZfJo/wQ030Mfch0S+M3IeJarLqaJzr0w== X-Received: by 2002:a63:5a20:0:b0:3aa:2fd0:9e94 with SMTP id o32-20020a635a20000000b003aa2fd09e94mr637635pgb.602.1650565699397; Thu, 21 Apr 2022 11:28:19 -0700 (PDT) Received: from mail.broadcom.net ([192.19.11.250]) by smtp.gmail.com with ESMTPSA id s62-20020a635e41000000b003a9eb7f65absm6509333pgb.85.2022.04.21.11.28.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 11:28:19 -0700 (PDT) From: Kamal Dasu To: ulf.hansson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, alcooperx@gmail.com Cc: f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kamal Dasu Subject: [PATCH 1/5] mmc: sdhci-brcmstb: "mmc1: Internal clock never stabilised." seen on 72113 Date: Thu, 21 Apr 2022 14:27:59 -0400 Message-Id: <20220421182803.6495-2-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220421182803.6495-1-kdasu.kdev@gmail.com> References: <20220421182803.6495-1-kdasu.kdev@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Al Cooper The problem is in the .shutdown callback that was added to the sdhci-iproc and sdhci-brcmstb drivers to save power in S5. The shutdown callback will just call the sdhci_pltfm_suspend() function to suspend the lower level driver and then stop the sdhci system clock. The problem is that in some cases there can be a worker thread in the "system_freezable_wq" work queue that is scanning for a device every second. In normal system suspend, this queue is suspended before the driver suspend is called. In shutdown the queue is not suspended and the thread my run after we stop the sdhci clock in the shutdown callback which will cause the "clock never stabilised" error. The solution will be to have the shutdown callback cancel the worker thread before calling suspend (and stopping the sdhci clock). NOTE: This is only happening on systems with the Legacy RPi SDIO core because that's the only controller that doesn't have the presence signal and needs to use a worker thread to do a 1 second poll loop. Fixes: 5b191dcba719 ("mmc: sdhci-brcmstb: Fix mmc timeout errors on S5 suspend") Signed-off-by: Al Cooper Signed-off-by: Kamal Dasu --- drivers/mmc/host/sdhci-brcmstb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index f24623aac2db..11037cd14cfa 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -313,6 +313,10 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) static void sdhci_brcmstb_shutdown(struct platform_device *pdev) { + struct sdhci_host *host = platform_get_drvdata(pdev); + + /* Cancel possible rescan worker thread */ + cancel_delayed_work_sync(&host->mmc->detect); sdhci_pltfm_suspend(&pdev->dev); } From patchwork Thu Apr 21 18:28:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 564697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A96E5C433FE for ; Thu, 21 Apr 2022 18:28:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1391324AbiDUSbR (ORCPT ); Thu, 21 Apr 2022 14:31:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1391321AbiDUSbR (ORCPT ); Thu, 21 Apr 2022 14:31:17 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 241AEDFAE; Thu, 21 Apr 2022 11:28:27 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id s137so5342462pgs.5; Thu, 21 Apr 2022 11:28:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CPKL6PLS2hyZUn/37pC34jEUL96YEezJ4fK6yAcdz3U=; b=cGu4y6MRjciJ6naClINARIrx1X6zxQzq3dzW52WNR/jIO2DdeoPq1k7LZvqqXwV823 jmaB57elHt0VHSI+g+zUgiJpc57J0wE9TkVlO5OQIQtZK+1/Lmi/qQKAKFwqRCSwrF8S q765lMNfqmh4hM+COy+yzpMqwSsbVIa+qoXEjtfJ81weTbyESIUFvIvKj28rDJlgDH+S Tx9ZFENSZ5nl6IeZGNgwVGX2VW4N2bCpgW4kO9zjEPpQhlBOSdVCnUetpVGxQPijHB3E LRCnGv+1lWM7Rm08VUR0zIztC14IBbAW3Wp6QBqI4y/Wzc1xryjp8+tQu4CjRIdLyndW k1NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CPKL6PLS2hyZUn/37pC34jEUL96YEezJ4fK6yAcdz3U=; b=V4OxQi/UYflLLFl4K17VkO0mPNwjOhro+f5l0r5KvJIy2GXwbCU7iYQO6AW7UapTmV Xf+04DZlz9ddfi9Bavqp1a9H1+fiPfRRiyaPIYPmWphRouWYunbx1lWmvI4JmPh2L9Vv jZEdK21Vqdf5f+iUET7ktckiqpWs/ztZZfjmRerrMTU7hSzSVa5GW2iAxzYwY1a2s9tb qHFV/tdY6jh1NIXGz5HMDb/0+tiQ5Vpx5a25Ry22cvHDooTCRE1BEK6LQ7C6i82QkrtX 25DkZjpwIWRB+5tEFuinxhySlC6x/GwP+1Lc7XCFZvExfBJUfZ4lW2dedZ7Pcsfsbdwx 3Omg== X-Gm-Message-State: AOAM532t2bT65cCAkaPZHayuC31IttYvZFDptvaq+H1Sf9cyMC/7PtIi RhNmgNDG8WK/t3TuMyYuH7k= X-Google-Smtp-Source: ABdhPJwHtpFLhF3JV7jb9ZgaqCrRrg4VaK87LgaEVhBuj9pyzUfRaR01TvE4rjLhQobLXHL/JoV60Q== X-Received: by 2002:a65:5c48:0:b0:382:2c7:28e9 with SMTP id v8-20020a655c48000000b0038202c728e9mr646700pgr.472.1650565706727; Thu, 21 Apr 2022 11:28:26 -0700 (PDT) Received: from mail.broadcom.net ([192.19.11.250]) by smtp.gmail.com with ESMTPSA id s62-20020a635e41000000b003a9eb7f65absm6509333pgb.85.2022.04.21.11.28.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 11:28:26 -0700 (PDT) From: Kamal Dasu To: ulf.hansson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, alcooperx@gmail.com Cc: f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kamal Dasu Subject: [PATCH 2/5] mmc: sdhci-brcmstb: Re-organize flags Date: Thu, 21 Apr 2022 14:28:00 -0400 Message-Id: <20220421182803.6495-3-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220421182803.6495-1-kdasu.kdev@gmail.com> References: <20220421182803.6495-1-kdasu.kdev@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Al Cooper Re-organize the flags by basing the bit names on the flag that they apply to. Also change the "flags" member in the "brcmstb_match_priv" struct to const. Signed-off-by: Al Cooper Signed-off-by: Kamal Dasu Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index 11037cd14cfa..f32aa045c26d 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -18,20 +18,22 @@ #define SDHCI_VENDOR 0x78 #define SDHCI_VENDOR_ENHANCED_STRB 0x1 -#define BRCMSTB_PRIV_FLAGS_NO_64BIT BIT(0) -#define BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT BIT(1) +#define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) +#define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) + +#define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 struct sdhci_brcmstb_priv { void __iomem *cfg_regs; - bool has_cqe; + unsigned int flags; }; struct brcmstb_match_priv { void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); struct sdhci_ops *ops; - unsigned int flags; + const unsigned int flags; }; static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) @@ -134,13 +136,13 @@ static struct sdhci_ops sdhci_brcmstb_ops_7216 = { }; static struct brcmstb_match_priv match_priv_7425 = { - .flags = BRCMSTB_PRIV_FLAGS_NO_64BIT | - BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, + .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | + BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, .ops = &sdhci_brcmstb_ops, }; static struct brcmstb_match_priv match_priv_7445 = { - .flags = BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, + .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, .ops = &sdhci_brcmstb_ops, }; @@ -176,7 +178,7 @@ static int sdhci_brcmstb_add_host(struct sdhci_host *host, bool dma64; int ret; - if (!priv->has_cqe) + if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0) return sdhci_add_host(host); dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); @@ -225,7 +227,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) struct sdhci_brcmstb_priv *priv; struct sdhci_host *host; struct resource *iomem; - bool has_cqe = false; struct clk *clk; int res; @@ -244,10 +245,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) return res; memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); - if (device_property_read_bool(&pdev->dev, "supports-cqe")) { - has_cqe = true; - match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; - } brcmstb_pdata.ops = match_priv->ops; host = sdhci_pltfm_init(pdev, &brcmstb_pdata, sizeof(struct sdhci_brcmstb_priv)); @@ -258,7 +255,10 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); priv = sdhci_pltfm_priv(pltfm_host); - priv->has_cqe = has_cqe; + if (device_property_read_bool(&pdev->dev, "supports-cqe")) { + priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; + match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; + } /* Map in the non-standard CFG registers */ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); @@ -287,14 +287,14 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) * properties through mmc_of_parse(). */ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); - if (match_priv->flags & BRCMSTB_PRIV_FLAGS_NO_64BIT) + if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT) host->caps &= ~SDHCI_CAN_64BIT; host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_DDR50); host->quirks |= SDHCI_QUIRK_MISSING_CAPS; - if (match_priv->flags & BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT) + if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; res = sdhci_brcmstb_add_host(host, priv); From patchwork Thu Apr 21 18:28:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 565470 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 281F1C433FE for ; Thu, 21 Apr 2022 18:28:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1391345AbiDUSbX (ORCPT ); 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Thu, 21 Apr 2022 11:28:30 -0700 (PDT) From: Kamal Dasu To: ulf.hansson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, alcooperx@gmail.com Cc: f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kamal Dasu Subject: [PATCH 3/5] mmc: sdhci-brcmstb: Enable Clock Gating to save power Date: Thu, 21 Apr 2022 14:28:01 -0400 Message-Id: <20220421182803.6495-4-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220421182803.6495-1-kdasu.kdev@gmail.com> References: <20220421182803.6495-1-kdasu.kdev@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Al Cooper Enabling this feature will allow the controller to stop the bus clock when the bus is idle. The feature is not part of the standard and is unique to newer Arasan cores and is enabled with a bit in a vendor specific register. This feature will only be enabled for non-removable devices because they don't switch the voltage and clock gating breaks SD Card volatge switching. Signed-off-by: Al Cooper Signed-off-by: Kamal Dasu Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 35 +++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index f32aa045c26d..d5cb3e8978b2 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -17,11 +17,14 @@ #define SDHCI_VENDOR 0x78 #define SDHCI_VENDOR_ENHANCED_STRB 0x1 +#define SDHCI_VENDOR_GATE_SDCLK_EN 0x2 #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) +#define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2) #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) +#define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1) #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 @@ -36,6 +39,27 @@ struct brcmstb_match_priv { const unsigned int flags; }; +static inline void enable_clock_gating(struct sdhci_host *host) +{ + u32 reg; + + reg = sdhci_readl(host, SDHCI_VENDOR); + reg |= SDHCI_VENDOR_GATE_SDCLK_EN; + sdhci_writel(host, reg, SDHCI_VENDOR); +} + +void brcmstb_reset(struct sdhci_host *host, u8 mask) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); + + sdhci_reset(host, mask); + + /* Reset will clear this, so re-enable it */ + if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK) + enable_clock_gating(host); +} + static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) { struct sdhci_host *host = mmc_priv(mmc); @@ -131,7 +155,7 @@ static struct sdhci_ops sdhci_brcmstb_ops = { static struct sdhci_ops sdhci_brcmstb_ops_7216 = { .set_clock = sdhci_brcmstb_set_clock, .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_reset, + .reset = brcmstb_reset, .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, }; @@ -147,6 +171,7 @@ static struct brcmstb_match_priv match_priv_7445 = { }; static const struct brcmstb_match_priv match_priv_7216 = { + .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, .hs400es = sdhci_brcmstb_hs400es, .ops = &sdhci_brcmstb_ops_7216, }; @@ -273,6 +298,14 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) if (res) goto err; + /* + * Automatic clock gating does not work for SD cards that may + * voltage switch so only enable it for non-removable devices. + */ + if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) && + (host->mmc->caps & MMC_CAP_NONREMOVABLE)) + priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK; + /* * If the chip has enhanced strobe and it's enabled, add * callback From patchwork Thu Apr 21 18:28:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 564696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA9F8C433F5 for ; Thu, 21 Apr 2022 18:28:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1391350AbiDUSbZ (ORCPT ); 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Thu, 21 Apr 2022 11:28:33 -0700 (PDT) From: Kamal Dasu To: ulf.hansson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, alcooperx@gmail.com Cc: f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kamal Dasu Subject: [PATCH 4/5] dt-bindings: mmc: Add Broadcom optional sdio_freq clock Date: Thu, 21 Apr 2022 14:28:02 -0400 Message-Id: <20220421182803.6495-5-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220421182803.6495-1-kdasu.kdev@gmail.com> References: <20220421182803.6495-1-kdasu.kdev@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The 72116B0 has improved SDIO controllers that allow the max clock rate to be increased from a max of 100MHz to a max of 150MHz. Optional "sdio_freq" clock is used to drive the bus clock if present optional property "clock-frequency" specifies a base clock frequency in Hz that overrides the base clock frequency in the CAPS registers. Signed-off-by: Kamal Dasu --- .../bindings/mmc/brcm,sdhci-brcmstb.yaml | 29 +++++++++++++++---- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index dccd5ad96981..1b45a918400a 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -10,8 +10,6 @@ maintainers: - Al Cooper - Florian Fainelli -allOf: - - $ref: mmc-controller.yaml# properties: compatible: @@ -42,23 +40,44 @@ properties: maxItems: 1 clocks: - maxItems: 1 - description: - handle to core clock for the sdhci controller. + minItems: 1 + items: + - description: handle to core clock for the sdhci controller + - description: improved 150Mhz clock for sdhci controller (Optional clock) clock-names: + minItems: 1 items: - const: sw_sdio + - const: sdio_freq # Optional clock + + clock-frequency: + description: Should be the frequency (in Hz) of the base controller clock + minimum: 400000 + maximum: 150000000 sdhci,auto-cmd12: type: boolean description: Specifies that controller should use auto CMD12 +allOf: + - $ref: mmc-controller.yaml# + - if: + properties: + clock-names: + contains: + const: sdio_freq + + - then: + required: + - clock-frequency + required: - compatible - reg - interrupts - clocks + - clock-names unevaluatedProperties: false From patchwork Thu Apr 21 18:28:03 2022 Content-Type: text/plain; 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Thu, 21 Apr 2022 11:28:37 -0700 (PDT) Received: from mail.broadcom.net ([192.19.11.250]) by smtp.gmail.com with ESMTPSA id s62-20020a635e41000000b003a9eb7f65absm6509333pgb.85.2022.04.21.11.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 11:28:36 -0700 (PDT) From: Kamal Dasu To: ulf.hansson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, alcooperx@gmail.com Cc: f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kamal Dasu Subject: [PATCH 5/5] mmc: sdhci-brcmstb: Add ability to increase max clock rate for 72116b0 Date: Thu, 21 Apr 2022 14:28:03 -0400 Message-Id: <20220421182803.6495-6-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220421182803.6495-1-kdasu.kdev@gmail.com> References: <20220421182803.6495-1-kdasu.kdev@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Al Cooper The 72116B0 has improved SDIO controllers that allow the max clock rate to be increased from a max of 100MHz to a max of 150MHz. The driver will need to get the clock and increase it's default rate and override the caps register, that still indicates a max of 100MHz. The new clock will be named "sdio_freq" in the DT node's "clock-names" list. The driver will use a DT property, "clock-frequency", to enable this functionality and will get the actual rate in MHz from the property to allow various speeds to be requested. Signed-off-by: Al Cooper Signed-off-by: Kamal Dasu --- drivers/mmc/host/sdhci-brcmstb.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index d5cb3e8978b2..4f3629a8e70a 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -250,6 +250,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) struct sdhci_pltfm_host *pltfm_host; const struct of_device_id *match; struct sdhci_brcmstb_priv *priv; + uint32_t base_clock_hz = 0; struct sdhci_host *host; struct resource *iomem; struct clk *clk; @@ -330,6 +331,30 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; + /* Change the base clock frequency if the DT property exists */ + if (device_property_read_u32(&pdev->dev, "clock-frequency", + &base_clock_hz) == 0) { + struct clk *master_clk; + u32 actual_clock_mhz; + + master_clk = devm_clk_get(&pdev->dev, "sdio_freq"); + if (IS_ERR(master_clk)) { + dev_warn(&pdev->dev, + "Clock for \"sdio_freq\" was not found\n"); + } else { + clk_set_rate(master_clk, base_clock_hz); + actual_clock_mhz = clk_get_rate(master_clk) / 1000000; + + host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; + host->caps |= + (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); + /* Disable presets because they are now incorrect */ + host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; + dev_dbg(&pdev->dev, + "Base Clock Frequency changed to %dMHz\n", + actual_clock_mhz); + } + } res = sdhci_brcmstb_add_host(host, priv); if (res) goto err;