From patchwork Thu Apr 21 09:53:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 564741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9EE6C43217 for ; Thu, 21 Apr 2022 09:53:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387929AbiDUJ4Y (ORCPT ); Thu, 21 Apr 2022 05:56:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383735AbiDUJ4W (ORCPT ); Thu, 21 Apr 2022 05:56:22 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CB0C25593; Thu, 21 Apr 2022 02:53:32 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 1F4181BF217; Thu, 21 Apr 2022 09:53:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1650534810; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fH8vPkT4dWPPGb/8XoLObFxHw6R65IrJ2LRqxUIBB1A=; b=jQAVCmtmSsMdiF2mg10x1jOb9WtnnLtXaK9eYbhNSfKrfyMgR1mMpKOW/pPXraZReKvINv ePxeZQOnWoEGeWGazDeezKqkyXncqQusEaN23wvVE1ea+BV9cWmP8dbo28aWDy1jzBAQYS dVX23YVtAFuXrdJumN133qWYZKZXYz/9Mn1vSOhD+sjs4SIvByNZBmbT7rWzApgcCYnJ66 HUiK1GDxf5qMQOTDAt9Xx1NoIkyVhIS4C8HSUfKLiVwY/sszw0YVTjsq+AW6QdyBd6CwYN mWd86cerovW5yXoq1lfGxTcdbQEYG5anQRKiZ9PM5VdW5sEfXT9ef+CrgBGAXg== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Ilpo Jarvinen , Emil Renner Berthing Subject: [PATCH v6 02/12] serial: 8250: dw: Create a generic platform data structure Date: Thu, 21 Apr 2022 11:53:13 +0200 Message-Id: <20220421095323.101811-3-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220421095323.101811-1-miquel.raynal@bootlin.com> References: <20220421095323.101811-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Emil Renner Berthing Use device tree match data rather than multiple calls to of_device_is_compatible() by introducing a platform data structure and adding a quirks mask. Provide a stub to the compatibles without quirks to simplify the handling of the upcoming changes. Signed-off-by: Emil Renner Berthing [ Reviewed-by: Geert Uytterhoeven Reviewed-by: Andy Shevchenko --- drivers/tty/serial/8250/8250_dw.c | 42 ++++++++++++++++++++++------ drivers/tty/serial/8250/8250_dwlib.h | 5 ++++ 2 files changed, 39 insertions(+), 8 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index dcbe54ccd16b..7fdb2683f534 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -37,6 +38,11 @@ /* DesignWare specific register fields */ #define DW_UART_MCR_SIRE BIT(6) +/* Quirks */ +#define DW_UART_QUIRK_OCTEON BIT(0) +#define DW_UART_QUIRK_ARMADA_38X BIT(1) +#define DW_UART_QUIRK_SKIP_SET_RATE BIT(2) + static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb) { return container_of(nb, struct dw8250_data, clk_notifier); @@ -366,6 +372,7 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param) static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) { struct device_node *np = p->dev->of_node; + unsigned int quirks = data->pdata->quirks; if (np) { int id; @@ -375,7 +382,7 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) if (id >= 0) p->line = id; #ifdef CONFIG_64BIT - if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { + if (quirks & DW_UART_QUIRK_OCTEON) { p->serial_in = dw8250_serial_inq; p->serial_out = dw8250_serial_outq; p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; @@ -391,9 +398,9 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) p->serial_out = dw8250_serial_out32be; } - if (of_device_is_compatible(np, "marvell,armada-38x-uart")) + if (quirks & DW_UART_QUIRK_ARMADA_38X) p->serial_out = dw8250_serial_out38x; - if (of_device_is_compatible(np, "starfive,jh7100-uart")) + if (quirks & DW_UART_QUIRK_SKIP_SET_RATE) p->set_termios = dw8250_do_set_termios; } else if (acpi_dev_present("APMC0D08", NULL, -1)) { @@ -456,6 +463,7 @@ static int dw8250_probe(struct platform_device *pdev) data->data.dma.fn = dw8250_fallback_dma_filter; data->usr_reg = DW_UART_USR; + data->pdata = device_get_match_data(p->dev); p->private_data = &data->data; data->uart_16550_compatible = device_property_read_bool(dev, @@ -672,12 +680,30 @@ static const struct dev_pm_ops dw8250_pm_ops = { SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) }; +static const struct dw8250_platform_data dw8250_dw_apb = { +}; + +static const struct dw8250_platform_data dw8250_octeon_3860_data = { + .quirks = DW_UART_QUIRK_OCTEON, +}; + +static const struct dw8250_platform_data dw8250_armada_38x_data = { + .quirks = DW_UART_QUIRK_ARMADA_38X, +}; + +static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { +}; + +static const struct dw8250_platform_data dw8250_starfive_jh7100_data = { + .quirks = DW_UART_QUIRK_SKIP_SET_RATE, +}; + static const struct of_device_id dw8250_of_match[] = { - { .compatible = "snps,dw-apb-uart" }, - { .compatible = "cavium,octeon-3860-uart" }, - { .compatible = "marvell,armada-38x-uart" }, - { .compatible = "renesas,rzn1-uart" }, - { .compatible = "starfive,jh7100-uart" }, + { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, + { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, + { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, + { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, + { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, dw8250_of_match); diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h index 72e7dbcccad0..68bb81bee660 100644 --- a/drivers/tty/serial/8250/8250_dwlib.h +++ b/drivers/tty/serial/8250/8250_dwlib.h @@ -21,8 +21,13 @@ struct dw8250_port_data { u8 dlf_size; }; +struct dw8250_platform_data { + unsigned int quirks; +}; + struct dw8250_data { struct dw8250_port_data data; + const struct dw8250_platform_data *pdata; u8 usr_reg; int msr_mask_on; From patchwork Thu Apr 21 09:53:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 564740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76402C433F5 for ; Thu, 21 Apr 2022 09:53:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387933AbiDUJ42 (ORCPT ); Thu, 21 Apr 2022 05:56:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387930AbiDUJ4Z (ORCPT ); Thu, 21 Apr 2022 05:56:25 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD30125581; Thu, 21 Apr 2022 02:53:35 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id DAB1C1BF219; Thu, 21 Apr 2022 09:53:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1650534814; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GW04PeL3gt042YVBAD6j+Utxak9HjtBATEu5WEj2ZLE=; b=VQguWJjSv/xFavkJKy5G87rKbxdVXG7RuMEGSR911rHwAFniAL8MSFcHYubvA3Ns0lCFzT A0a1WEDjOMd2Jo6d0CPPf/i15wAb7yjHZlvgrKzajbN93t4s0c1NRsQ+DApdzqLQoONGRq N+EBcCb0PLyXiwG/Qkt3zjnsDzIckYXPPjZ584SjITi/0N912kZkuU3k/nzBGshvlKdYO5 dsERmMWkYK12uGcupXkWKNX5+9dlb/nUiFzWNaAzB42QFLpYr3jLL0r1feNZgnT22qMt8G LnkLogs2WF5JdfWC7r3sT0Cy9Yggj/JZxhwcrp3/pRKxeF2xACcMZrv4Nk634g== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Ilpo Jarvinen , Phil Edworthy Subject: [PATCH v6 04/12] serial: 8250: dw: Allow to use a fallback CPR value if not synthesized Date: Thu, 21 Apr 2022 11:53:15 +0200 Message-Id: <20220421095323.101811-5-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220421095323.101811-1-miquel.raynal@bootlin.com> References: <20220421095323.101811-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org DW UART controllers can be synthesized without the CPR register. In this case, allow to the platform information to provide a CPR value. Co-developed-by: Phil Edworthy Signed-off-by: Phil Edworthy Signed-off-by: Miquel Raynal Reviewed-by: Andy Shevchenko --- drivers/tty/serial/8250/8250_dwlib.c | 10 +++++++--- drivers/tty/serial/8250/8250_dwlib.h | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c index 622d3b0d89e7..f1fb20353612 100644 --- a/drivers/tty/serial/8250/8250_dwlib.c +++ b/drivers/tty/serial/8250/8250_dwlib.c @@ -89,6 +89,8 @@ EXPORT_SYMBOL_GPL(dw8250_do_set_termios); void dw8250_setup_port(struct uart_port *p) { + struct dw8250_port_data *pd = p->private_data; + struct dw8250_data *data = to_dw8250_data(pd); struct uart_8250_port *up = up_to_u8250p(p); u32 reg; @@ -108,14 +110,16 @@ void dw8250_setup_port(struct uart_port *p) dw8250_writel_ext(p, DW_UART_DLF, 0); if (reg) { - struct dw8250_port_data *d = p->private_data; - - d->dlf_size = fls(reg); + pd->dlf_size = fls(reg); p->get_divisor = dw8250_get_divisor; p->set_divisor = dw8250_set_divisor; } reg = dw8250_readl_ext(p, DW_UART_CPR); + if (!reg) { + reg = data->pdata->cpr_val; + dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg); + } if (!reg) return; diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h index 0df6baa6eaee..36a839ef5d9a 100644 --- a/drivers/tty/serial/8250/8250_dwlib.h +++ b/drivers/tty/serial/8250/8250_dwlib.h @@ -23,6 +23,7 @@ struct dw8250_port_data { struct dw8250_platform_data { u8 usr_reg; + u32 cpr_val; unsigned int quirks; }; From patchwork Thu Apr 21 09:53:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 564739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97E40C4332F for ; Thu, 21 Apr 2022 09:53:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387942AbiDUJ4g (ORCPT ); Thu, 21 Apr 2022 05:56:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387934AbiDUJ43 (ORCPT ); Thu, 21 Apr 2022 05:56:29 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38C1225581; Thu, 21 Apr 2022 02:53:39 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 79A831BF20E; Thu, 21 Apr 2022 09:53:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1650534818; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1o9gHj8wxamYjHVCuaoFpSvvDAO8QSz0Ljq85N7Dk7I=; b=nVaj+B69IukC3pSCpy3N042jySgDALJQEBk9rxoSI+2ayU10fKj+GX/lIe7mKNT6IEgf3h 35Zsp0/056N3zi1OrCSv+kk5LMo5wTWfI3SYaXQeenQyaKuM8kECYn8r1DKklvbV5yqSW7 U1dxFztd93k/Iz+OgiVf3fedVbtABax5jRAo2GNxACoXEB4j1nttNd/kw0Qt0Ale53ITrd HTQWHnimbGjRNt3w+87zuaSi4dCzD6AW9K6r5H/Wj8ev3mXV0URpOlptW+JSEfc4DRizqg d9CvCwZTZWqZVZ+HczAfpxXdID4ASvfnUcn7aK/Z+i4FXVrCXsb5hm/qs4IGdQ== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Ilpo Jarvinen Subject: [PATCH v6 06/12] serial: 8250: dw: Introduce an rx_timeout variable in the IRQ path Date: Thu, 21 Apr 2022 11:53:17 +0200 Message-Id: <20220421095323.101811-7-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220421095323.101811-1-miquel.raynal@bootlin.com> References: <20220421095323.101811-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org In a next change we are going to need the same Rx timeout condition as we already have in the IRQ handling code. Let's just create a boolean to clarify what this operation does before reusing it. There is no functional change. Signed-off-by: Miquel Raynal Reviewed-by: Andy Shevchenko --- drivers/tty/serial/8250/8250_dw.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index b34edc88af3d..ef3f05c82ad6 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -225,6 +225,7 @@ static int dw8250_handle_irq(struct uart_port *p) struct uart_8250_port *up = up_to_u8250p(p); struct dw8250_data *d = to_dw8250_data(p->private_data); unsigned int iir = p->serial_in(p, UART_IIR); + bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT; unsigned int status; unsigned long flags; @@ -238,7 +239,7 @@ static int dw8250_handle_irq(struct uart_port *p) * This problem has only been observed so far when not in DMA mode * so we limit the workaround only to non-DMA mode. */ - if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { + if (!up->dma && rx_timeout) { spin_lock_irqsave(&p->lock, flags); status = p->serial_in(p, UART_LSR); From patchwork Thu Apr 21 09:53:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 564738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9DD1C43219 for ; Thu, 21 Apr 2022 09:53:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387936AbiDUJ4n (ORCPT ); Thu, 21 Apr 2022 05:56:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387937AbiDUJ4e (ORCPT ); Thu, 21 Apr 2022 05:56:34 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BFF5275E5; Thu, 21 Apr 2022 02:53:42 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 05EAD1BF215; Thu, 21 Apr 2022 09:53:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1650534821; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=22QNVg6uSLAoA0tE56JQu0CNN8Oej1eCBOWwcucJ1cc=; b=EfLu5ZafJ9OVDHF4iTz5UkKREGE1ET6dwW18HT1+oh9b0kYQYrVa+KzXbbXFaJ7MIgwwaa rPa0Y71lUCNV965nqYMEYy3cIkZm5w6BDIY6DewTmXa3iL6bvje8vIt9a6l7xDLd6bXzeu kItUCixbJl28hHarAzktAShW/s77KsGgwAVEPVkKFQ9B8B0XvjwbhCbU4enl9n1NE3j77p jBvfEk2bzjvGjD4529DTvqVrGTA2oEGJ2vbdpM6Bifp93Dp9MMRcFdJxan8BhX2Cf5eILe Ow6bYRlWLpeSMgs/Btab7W+wUSkSwEh9eDDzJj7bSmSLcE+ncMjhHa2KtImq7A== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Ilpo Jarvinen , Phil Edworthy Subject: [PATCH v6 08/12] serial: 8250: dw: Add support for DMA flow controlling devices Date: Thu, 21 Apr 2022 11:53:19 +0200 Message-Id: <20220421095323.101811-9-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220421095323.101811-1-miquel.raynal@bootlin.com> References: <20220421095323.101811-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Phil Edworthy DW based controllers like the one on Renesas RZ/N1 must be programmed as flow controllers when using DMA. * Table 11.45 of the system manual, "Flow Control Combinations", states that using UART with DMA requires setting the DMA in the peripheral flow controller mode regardless of the direction. * Chapter 11.6.1.3 of the system manual, "Basic Interface Definitions", explains that the burst size in the above case must be configured in the peripheral's register DEST/SRC_BURST_SIZE. Experiments shown that upon Rx timeout, the DMA transaction needed to be manually cleared as well. Signed-off-by: Phil Edworthy Co-developed-by: Miquel Raynal Signed-off-by: Miquel Raynal Reviewed-by: Andy Shevchenko --- drivers/tty/serial/8250/8250_dw.c | 64 +++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index ef3f05c82ad6..90e64c8bd4bf 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -34,16 +34,28 @@ /* Offsets for the DesignWare specific registers */ #define DW_UART_USR 0x1f /* UART Status Register */ +#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ #define OCTEON_UART_USR 0x27 /* UART Status Register */ +#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ +#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ + /* DesignWare specific register fields */ #define DW_UART_MCR_SIRE BIT(6) +/* Renesas specific register fields */ +#define RZN1_UART_xDMACR_DMA_EN BIT(0) +#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1) +#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1) +#define RZN1_UART_xDMACR_8_WORD_BURST (3 << 1) +#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3) + /* Quirks */ #define DW_UART_QUIRK_OCTEON BIT(0) #define DW_UART_QUIRK_ARMADA_38X BIT(1) #define DW_UART_QUIRK_SKIP_SET_RATE BIT(2) +#define DW_UART_QUIRK_IS_DMA_FC BIT(3) static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb) { @@ -226,6 +238,7 @@ static int dw8250_handle_irq(struct uart_port *p) struct dw8250_data *d = to_dw8250_data(p->private_data); unsigned int iir = p->serial_in(p, UART_IIR); bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT; + unsigned int quirks = d->pdata->quirks; unsigned int status; unsigned long flags; @@ -249,6 +262,15 @@ static int dw8250_handle_irq(struct uart_port *p) spin_unlock_irqrestore(&p->lock, flags); } + /* Manually stop the Rx DMA transfer when acting as flow controller */ + if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) { + status = p->serial_in(p, UART_LSR); + if (status & (UART_LSR_DR | UART_LSR_BI)) { + dw8250_writel_ext(p, RZN1_UART_RDMACR, 0); + dw8250_writel_ext(p, DW_UART_DMASA, 1); + } + } + if (serial8250_handle_irq(p, iir)) return 1; @@ -372,6 +394,42 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param) return param == chan->device->dev; } +static u32 dw8250_rzn1_get_dmacr_burst(int max_burst) +{ + if (max_burst >= 8) + return RZN1_UART_xDMACR_8_WORD_BURST; + else if (max_burst >= 4) + return RZN1_UART_xDMACR_4_WORD_BURST; + else + return RZN1_UART_xDMACR_1_WORD_BURST; +} + +static void dw8250_prepare_tx_dma(struct uart_8250_port *p) +{ + struct uart_port *up = &p->port; + struct uart_8250_dma *dma = p->dma; + u32 val; + + dw8250_writel_ext(up, RZN1_UART_TDMACR, 0); + val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) | + RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) | + RZN1_UART_xDMACR_DMA_EN; + dw8250_writel_ext(up, RZN1_UART_TDMACR, val); +} + +static void dw8250_prepare_rx_dma(struct uart_8250_port *p) +{ + struct uart_port *up = &p->port; + struct uart_8250_dma *dma = p->dma; + u32 val; + + dw8250_writel_ext(up, RZN1_UART_RDMACR, 0); + val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) | + RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) | + RZN1_UART_xDMACR_DMA_EN; + dw8250_writel_ext(up, RZN1_UART_RDMACR, val); +} + static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) { struct device_node *np = p->dev->of_node; @@ -404,6 +462,12 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) p->serial_out = dw8250_serial_out38x; if (quirks & DW_UART_QUIRK_SKIP_SET_RATE) p->set_termios = dw8250_do_set_termios; + if (quirks & DW_UART_QUIRK_IS_DMA_FC) { + data->data.dma.txconf.device_fc = 1; + data->data.dma.rxconf.device_fc = 1; + data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma; + data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma; + } } else if (acpi_dev_present("APMC0D08", NULL, -1)) { p->iotype = UPIO_MEM32; From patchwork Thu Apr 21 09:53:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 564737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 517FEC4321E for ; Thu, 21 Apr 2022 09:53:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387951AbiDUJ4p (ORCPT ); Thu, 21 Apr 2022 05:56:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387941AbiDUJ4g (ORCPT ); Thu, 21 Apr 2022 05:56:36 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5456F25593; Thu, 21 Apr 2022 02:53:46 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 8F0F71BF208; Thu, 21 Apr 2022 09:53:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1650534825; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/nh7f6/HuLMWiH/LM1IrO4PPA0OM/mrddN4VWrPik6E=; b=hhtwiZMcUMV+xNCN/aF+mPbIlVdCARFdxPe0hTjVETDlpPKpK7gC/wwhPE2AvdrOFKLf1Y J9CeU3mbUC+pzstGswA0YSQTnf1Y+dRWNXnGOaowHGsJy9HJwNvkiHH4TVztc5QBaGeFiz H0FLPMirOsLHmeq9UyVnLO90zOMZNYjq/HmzNXna50dnYi4yqkNReKIbA7dxMF7/U04vOG XhS4DyiDLxaaWq17Q2eV1SZZo5UNQL5kvH+9LvwaE0kbzvAqXx0fMbxhjmuyaO/tmbe3eQ c4WXmlIUdph+7vyUPxi5zVPDHZPJN9j9HY4WwaA0CEgHo98YFzYGAU9WiXCJDQ== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Ilpo Jarvinen Subject: [PATCH v6 10/12] ARM: dts: r9a06g032: Fill the UART DMA properties Date: Thu, 21 Apr 2022 11:53:21 +0200 Message-Id: <20220421095323.101811-11-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220421095323.101811-1-miquel.raynal@bootlin.com> References: <20220421095323.101811-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org UART 0 to 2 do not have DMA support, while UART 3 to 7 do. Fill the "dmas" and "dma-names" properties for each of these nodes. Please mind that these nodes go through the dmamux node which will redirect the requests to the right DMA controller. The first 4 cells of the "dmas" properties will be transferred as-is to the DMA controllers. The last 2 cells are consumed by the dmamux. Which means cell 0 and 4 are almost redundant, one giving the controller request ID and the other the dmamux channel which is a 1:1 translation of the request IDs, shifted by 16 when pointing to the second DMA controller. Signed-off-by: Miquel Raynal --- arch/arm/boot/dts/r9a06g032.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index c854aa4cfa77..4288b935fcea 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -144,6 +144,9 @@ uart3: serial@50000000 { reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 0 0 0 0 0 1>, + <&dmamux 1 0 0 0 1 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -155,6 +158,9 @@ uart4: serial@50001000 { reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 2 0 0 0 2 1>, + <&dmamux 3 0 0 0 3 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -166,6 +172,9 @@ uart5: serial@50002000 { reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 4 0 0 0 4 1>, + <&dmamux 5 0 0 0 5 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -177,6 +186,9 @@ uart6: serial@50003000 { reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 6 0 0 0 6 1>, + <&dmamux 7 0 0 0 7 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -188,6 +200,9 @@ uart7: serial@50004000 { reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 4 0 0 0 20 1>, + <&dmamux 5 0 0 0 21 1>; + dma-names = "rx", "tx"; status = "disabled"; }; From patchwork Thu Apr 21 09:53:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 564736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E973EC433F5 for ; Thu, 21 Apr 2022 09:54:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387960AbiDUJ4r (ORCPT ); Thu, 21 Apr 2022 05:56:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387943AbiDUJ4h (ORCPT ); Thu, 21 Apr 2022 05:56:37 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FD7025581; Thu, 21 Apr 2022 02:53:47 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 3E0FD1BF210; Thu, 21 Apr 2022 09:53:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1650534826; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OkvzJztRthVaGIL1bz3XTVaBBeEF3F6WAHdml+C/P4M=; b=CeuMlaXHaxnLLUOSPSMnw1pelWNWBfKMNPABDz13we9vGFEx9jhhsv6OTeawoddlCGkxx3 GSXsvWW/gzPdSUDZpbMK51z1IH0zZCbMxLoku5NYNy0IvR7SucgbCAMZqo1xqrDMOaUizF PG1S4K2wdNhcS50rD8yzhZgaIbMjtpArRh5VNPZXjKZqyCbHrhAkQen2AvznPH+YCxr63u lsFszQ84MPuGfXixzp1bBhp8gPGBM+M/rbeTm0/TCcKchl8bR1kAXBDERqoOpy5H/VOlrA iY1DhrU8dc44MQ/azRU2xkOuAVioHBdx06Y3S5uNTB7UexBdX6iqWCf0PR4gJg== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Ilpo Jarvinen Subject: [PATCH v6 11/12] bestla: Enable DMA, UART3 and UART4 Date: Thu, 21 Apr 2022 11:53:22 +0200 Message-Id: <20220421095323.101811-12-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220421095323.101811-1-miquel.raynal@bootlin.com> References: <20220421095323.101811-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Signed-off-by: Miquel Raynal --- .../boot/dts/r9a06g032-rzn1d400-bestla.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-bestla.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-bestla.dts index f42a3ba70541..70aa026bd292 100644 --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-bestla.dts +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-bestla.dts @@ -22,6 +22,8 @@ chosen { aliases { serial0 = &uart0; + serial3 = &uart3; + }; }; @@ -31,6 +33,22 @@ &uart0 { status = "okay"; }; +&uart3 { + pinctrl-0 = <&pins_uart3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&pins_uart4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + &nand_controller { pinctrl-0 = <&pins_nand>; pinctrl-names = "default"; @@ -82,4 +100,21 @@ RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ >; bias-disable; }; + + pins_uart3: pins_uart3 { + pinmux = < + RZN1_PINMUX(123, RZN1_FUNC_UART3) /* UART3_TXD */ + RZN1_PINMUX(124, RZN1_FUNC_UART3) /* UART3_RXD */ + RZN1_PINMUX(125, RZN1_FUNC_UART3) /* UART3_RTS_N */ + >; + bias-disable; + }; + + pins_uart4: pins_uart4 { + pinmux = < + RZN1_PINMUX(109, RZN1_FUNC_UART4) /* UART4_TXD */ + RZN1_PINMUX(110, RZN1_FUNC_UART4) /* UART4_RXD */ + >; + bias-disable; + }; };