From patchwork Sat Apr 23 13:39:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 565621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04D4BC4321E for ; Sat, 23 Apr 2022 13:40:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235820AbiDWNnV (ORCPT ); Sat, 23 Apr 2022 09:43:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235826AbiDWNmn (ORCPT ); Sat, 23 Apr 2022 09:42:43 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6C531759F8 for ; Sat, 23 Apr 2022 06:39:44 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id y32so18815926lfa.6 for ; Sat, 23 Apr 2022 06:39:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CDwkASM9CJ+e3T14sU+DD4Z2q62VFhOP6cklNoMqPXY=; b=GdtxHObKgFjXdkmJ669X/Zn3OY+Z3NvjzQfWa5z50ScsnI34oRT4FHYQJVr34X/kAd ogX5n+k/Kev/nUKSFyq7LjNekVwN6DOoheude2lGZWi0Nc9fvHRopKntmSmrpcHA59np 6bnVTwp6A1XlEwVieIsMU5e5IsxYZzWAbZV2Tjd9SFFNulw43nQBHvxj49FiKerheOt7 +vqqsWbE/GYJZkjtntdQyJKSsiUQRpnzy/7L3Ao3x5Jz4T6FdIr8/fBbZUZNF5og8wJI jd5m9wzXOjL7OOh1YLNRA/t02tMT6y5x2witdCpZWOD8uK6fuVDdnPb49bIN+3LAhPMu Jk5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CDwkASM9CJ+e3T14sU+DD4Z2q62VFhOP6cklNoMqPXY=; b=l+0fwLo5kIaAC4Ki47wyz8yqtN9Pg/F/Yh7zAR5i19rdBqrGx76PRxPel04XHz4s9m jRWGZF6v19u+teNA3IccQT3z138DcNlKKvhnXkSsszKtKOrC2yxzN3EWJCRYjJJivU+v MAgy2HRG2iTeKw2MTWNlFG10XaKaJ6G1aD2MrMYzvKuAaoPSSyokMbI+YYETLRqPsvxb Eftw2zNW4VXcxm9893f6qQ1wfl/hDoRY4qikmTxCT/luBHLKCoTc9mrLk34y3LB4nsST YDZ+ifK4xUnTIi0abS5pRP0vzykWK0xIIhrWeC0sHzCnzQhn7z1aHk90nMKV1vfLRRmM Iokw== X-Gm-Message-State: AOAM531AjbmEP4i9pUUnmIR5P28xS2bzGXW4xRAjMbrFmF9qqOWsWxMz rOgdC80siWWK805A1DGOWt6FzQ== X-Google-Smtp-Source: ABdhPJz2KMIFxWRPSfMMPl806Mhi/I5x/Mmi9JwT4IZ6B4llV51mJHpKAY/WiXFWLfSTZ13qPaSSuQ== X-Received: by 2002:ac2:48a4:0:b0:471:fc7f:b54d with SMTP id u4-20020ac248a4000000b00471fc7fb54dmr535057lfg.538.1650721183144; Sat, 23 Apr 2022 06:39:43 -0700 (PDT) Received: from eriador.lumag.spb.ru ([94.25.228.223]) by smtp.gmail.com with ESMTPSA id c21-20020a2ea795000000b0024ee0f8ef92sm544535ljf.36.2022.04.23.06.39.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Apr 2022 06:39:42 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/5] PCI: dwc: Convert msi_irq to the array Date: Sat, 23 Apr 2022 16:39:35 +0300 Message-Id: <20220423133939.2123449-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> References: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm version of DWC PCIe controller supports more than 32 MSI interrupts, but they are routed to separate interrupts in groups of 32 vectors. To support such configuration, change the msi_irq field into an array. Let the DWC core handle all interrupts that were set in this array. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-exynos.c | 2 +- .../pci/controller/dwc/pcie-designware-host.c | 30 +++++++++++-------- drivers/pci/controller/dwc/pcie-designware.h | 2 +- drivers/pci/controller/dwc/pcie-keembay.c | 2 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 7 files changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index dfcdeb432dc8..0919c96dcdbd 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -483,7 +483,7 @@ static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, return pp->irq; /* MSI IRQ is muxed */ - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = dra7xx_pcie_init_irq_domain(pp); if (ret < 0) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c index 467c8d1cd7e4..4f2010bd9cd7 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -292,7 +292,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep, } pp->ops = &exynos_pcie_host_ops; - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = dw_pcie_host_init(pp); if (ret) { diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2fa86f32d964..5d90009a0f73 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -257,8 +257,11 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) static void dw_pcie_free_msi(struct pcie_port *pp) { - if (pp->msi_irq) - irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); + u32 ctrl; + + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) + if (pp->msi_irq[ctrl]) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL); irq_domain_remove(pp->msi_domain); irq_domain_remove(pp->irq_domain); @@ -368,13 +371,15 @@ int dw_pcie_host_init(struct pcie_port *pp) for (ctrl = 0; ctrl < num_ctrls; ctrl++) pp->irq_mask[ctrl] = ~0; - if (!pp->msi_irq) { - pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi"); - if (pp->msi_irq < 0) { - pp->msi_irq = platform_get_irq(pdev, 0); - if (pp->msi_irq < 0) - return pp->msi_irq; + if (!pp->msi_irq[0]) { + int irq = platform_get_irq_byname_optional(pdev, "msi"); + + if (irq < 0) { + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; } + pp->msi_irq[0] = irq; } pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; @@ -383,10 +388,11 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret) return ret; - if (pp->msi_irq > 0) - irq_set_chained_handler_and_data(pp->msi_irq, - dw_chained_msi_isr, - pp); + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + if (pp->msi_irq[ctrl] > 0) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], + dw_chained_msi_isr, + pp); ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 7d6e9b7576be..9c1a38b0a6b3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -187,7 +187,7 @@ struct pcie_port { u32 io_size; int irq; const struct dw_pcie_host_ops *ops; - int msi_irq; + int msi_irq[MAX_MSI_CTRLS]; struct irq_domain *irq_domain; struct irq_domain *msi_domain; u16 msi_msg; diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c index 1ac29a6eef22..297e6e926c00 100644 --- a/drivers/pci/controller/dwc/pcie-keembay.c +++ b/drivers/pci/controller/dwc/pcie-keembay.c @@ -338,7 +338,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie, int ret; pp->ops = &keembay_pcie_host_ops; - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = keembay_pcie_setup_msi_irq(pcie); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c index 1569e82b5568..cc7776833810 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -172,7 +172,7 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie, } pp->ops = &spear13xx_pcie_host_ops; - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = dw_pcie_host_init(pp); if (ret) { diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index b1b5f836a806..e75712db85b0 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2271,7 +2271,7 @@ static void tegra194_pcie_shutdown(struct platform_device *pdev) disable_irq(pcie->pci.pp.irq); if (IS_ENABLED(CONFIG_PCI_MSI)) - disable_irq(pcie->pci.pp.msi_irq); + disable_irq(pcie->pci.pp.msi_irq[0]); tegra194_pcie_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); From patchwork Sat Apr 23 13:39:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 565371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A09D7C433FE for ; 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Sat, 23 Apr 2022 06:39:44 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/5] PCI: dwc: Teach dwc core to parse additional MSI interrupts Date: Sat, 23 Apr 2022 16:39:36 +0300 Message-Id: <20220423133939.2123449-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> References: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DWC driver parses a single "msi" interrupt which gets fired when the EP sends an MSI interrupt, however for some devices (Qualcomm) devies MSI vectors are handled in groups of 32 vectors. Add support for parsing "split" MSI interrupts. In addition to the "msi" interrupt, the code will lookup the "msi2", "msi3", etc. IRQs and use them for the MSI group interrupts. For backwards compatibility with existing DTS files, the code will not error out if any of these interrupts is missing. Instead it will limit itself to the amount of MSI group IRQs declared in the DT file. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 23 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 5d90009a0f73..ce7071095006 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -382,6 +382,29 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->msi_irq[0] = irq; } + if (pp->has_split_msi_irq) { + char irq_name[] = "msiXXX"; + int irq; + + for (ctrl = 1; ctrl < num_ctrls; ctrl++) { + if (pp->msi_irq[ctrl]) + continue; + + snprintf(irq_name, sizeof(irq_name), "msi%d", ctrl + 1); + irq = platform_get_irq_byname_optional(pdev, irq_name); + if (irq == -ENXIO) { + num_ctrls = ctrl; + pp->num_vectors = num_ctrls * MAX_MSI_IRQS_PER_CTRL; + dev_warn(dev, "Limiting amount of MSI irqs to %d\n", pp->num_vectors); + break; + } + if (irq < 0) + return irq; + + pp->msi_irq[ctrl] = irq; + } + } + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; ret = dw_pcie_allocate_domains(pp); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9c1a38b0a6b3..3aa840a5b19c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -179,6 +179,7 @@ struct dw_pcie_host_ops { struct pcie_port { bool has_msi_ctrl:1; + bool has_split_msi_irq:1; u64 cfg0_base; void __iomem *va_cfg0_base; u32 cfg0_size; From patchwork Sat Apr 23 13:39:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 565620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D271DC43219 for ; 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Sat, 23 Apr 2022 06:39:45 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/5] PCI: qcom: Handle MSI IRQs properly Date: Sat, 23 Apr 2022 16:39:37 +0300 Message-Id: <20220423133939.2123449-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> References: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Thus to receive higher MSI vectors properly, enable has_split_msi_irq support. Note, that if DT doesn't list extra MSI interrupts, DWC core will limit the amount of supported MSI vectors accordingly (to 32). Fixes: 20f1bfb8dd62 ("PCI: qcom: Add support for handling MSIs from 8 endpoints") Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 45631c0aa468..78c4e2bcf38a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1587,6 +1587,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) pci->ops = &dw_pcie_ops; pp = &pci->pp; pp->num_vectors = MAX_MSI_IRQS; + pp->has_split_msi_irq = true; pcie->pci = pci; From patchwork Sat Apr 23 13:39:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 565370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35A32C4167D for ; Sat, 23 Apr 2022 13:40:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235933AbiDWNnW (ORCPT ); Sat, 23 Apr 2022 09:43:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235845AbiDWNmp (ORCPT ); Sat, 23 Apr 2022 09:42:45 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3ABE1759EE for ; Sat, 23 Apr 2022 06:39:48 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id f5so12700695ljp.8 for ; Sat, 23 Apr 2022 06:39:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X6WBUYEt3xorbdlyz+i4pBQ2N1Cgz5kH2giSC34i0K0=; b=GD3RuJRFAyipHDGx8MCln2dfVYp5XATckWhUNcOO1I6qc7HTcYDRkOPShQG/TgvkRP q/QokGDOwmTJzJw4tNFBQnsr16thEiHi8GQlyabk50Iq7CASxadEl6rLpdXtNzPTI641 viZ9sHfLux2VZ1sBTQlgmOfF37+5fbR+944WODwW0pDULbInAE8651Ig48t6XSnQ3vj3 6OvB6CZNtgG7IVn+cUVDFTMCIrhe/qaBU8gV6iJa9FjbT7IZgdReyXlLOJB8qo/ozd+t tYP0srh3bj+Z0RXEpGOu8I5TPNkuCcOnc9i44zs3sQAzIDvpCyeE6yz0GBUJ4WVxGo56 4rjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X6WBUYEt3xorbdlyz+i4pBQ2N1Cgz5kH2giSC34i0K0=; b=zFaYox46fN4EW27O9/yBxsbZ7FKBAA4yV5dA9MoA13K54pYpa7/RMJW9HvVhz8bbYD UhMFULGUH6vVlRtioSEeHPSNYpvRGUSRkLLhltS0acJ7U5rbPthvLgWakoblFka/4Zmw dRXtiFnVbgQDL5hkU7lTWGhdgBc0XIGHdRMQtSt1cVnLO4/vOi6IRlPSWtvHKpkB6ULE 8t+cC/+2ihfRXwft+KQ/WUsPFi85n8OO2WaIqasHUth7q1b77fmE9/0Jl/PkEsu8uAFX g8c3XyvL20Od5dNahbqkEgAcuy1TFNf6AEvd9kg0usgSWRg/NoJnVHxmRqb2gKlhwPKy IMiQ== X-Gm-Message-State: AOAM532F1Px3Zq0/2j/yE73Mc6f7kVTpaxRhj8+8JalxqAtKG/dfUz/K xap03vH3/eWYlr0UPXX/SJvAeg== X-Google-Smtp-Source: ABdhPJyfZE0L1IBdWglmpGHK1PZNMYwsLWTSMikeg9MrlIACpOflG+7binSEuM55Z81mYI3WNhi9LA== X-Received: by 2002:a2e:bf1b:0:b0:247:d88b:2b05 with SMTP id c27-20020a2ebf1b000000b00247d88b2b05mr5625928ljr.515.1650721187213; Sat, 23 Apr 2022 06:39:47 -0700 (PDT) Received: from eriador.lumag.spb.ru ([94.25.228.223]) by smtp.gmail.com with ESMTPSA id c21-20020a2ea795000000b0024ee0f8ef92sm544535ljf.36.2022.04.23.06.39.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Apr 2022 06:39:46 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/5] dt-bindings: pci/qcom,pcie: support additional MSI interrupts Date: Sat, 23 Apr 2022 16:39:38 +0300 Message-Id: <20220423133939.2123449-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> References: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie.yaml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 04fda2a4bb60..71b3be5570dd 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -49,11 +49,21 @@ properties: - atu # ATU address space (optional) interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: + minItems: 1 + maxItems: 8 items: - - const: "msi" + - const: msi + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: msi8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. From patchwork Sat Apr 23 13:39:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 565369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1B83C43217 for ; Sat, 23 Apr 2022 13:41:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235941AbiDWNnY (ORCPT ); Sat, 23 Apr 2022 09:43:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235861AbiDWNmr (ORCPT ); Sat, 23 Apr 2022 09:42:47 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31EC61759F8 for ; Sat, 23 Apr 2022 06:39:50 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id y19so1448322ljd.4 for ; Sat, 23 Apr 2022 06:39:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ga1FXFUoff60uV1gZjfSxxZrosbrRhkS2aF6jySEeu8=; b=lAfcX7bWhAiM9qF8UplivEufLN8b5gpEwGkIaQWc+/TyMXGXB54X7qbZ0xf5ad1imo aW9vy+TvbUSWyn2SxkKuslAcVJL77BwkVE26NILN7lifOMfx+nSzBn6o80FmMa9YL/RX CCaRkd7KirFN1ilEQGnJBgt+CTtCVQJ6sSlSOG0xFntNGeiE5jcrN2EzxaYuf8AvsYDf AFFuVW9IfH29zQM6SUzM6Cj2iWF51BdJCj5VDzC52JBrfrkYwj9lVkzqsc3NlTlvLip2 b1Yi4nxEwS3b6cCcgUXA+RxKGOdRZUKND3dp+199b6dfMJWCXRi5AkuVTP2QK8dn2Ola hkVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ga1FXFUoff60uV1gZjfSxxZrosbrRhkS2aF6jySEeu8=; b=g/YPF8Pb6v2aYcNeEXVtOFAHW9OYeBN/5/I9yAHr/FetF4V8RMTYhW81OOk6NsmBfr j+BJTSeNlOEVSg6/WcQabb2jsTky/YpI500Tin5EKIhPxTcxbSrKy1nwNdl12NFgtTAc 5ZS1CPL6lPNVQvIGJNwSNGTN2kSm/oxIffbgUIdOkxwJ31YqMMMBHlWJXX/PhEM01b5w o4aVNVmMj1Bed2ymKYdkVR9hUTVZaS77dFAoqqHwTIl9FFxWJAGBSIo/Y2WNagJu4S0i MnK9xh3frA4dN6Nqe34RaaKokWcvWXPYZwGodxkakRdhcJWjvJe9FonhB/uEsS5cToVw kwSg== X-Gm-Message-State: AOAM531rlaMdbnpGNSkur5aS3RGPTQvLu3EIeWLE14zXg2LnjzaVHW0O PYAnrVIoYIRcmJ3qPuH4uI8SWA== X-Google-Smtp-Source: ABdhPJxNLdvhSGNd5ayRrc8CDk6a9IOgwYlVvuxyvZvzA5HmPMaFuVsPiXoPE3vLcgTwlI5tWirfXw== X-Received: by 2002:a2e:a4b4:0:b0:246:2930:53d7 with SMTP id g20-20020a2ea4b4000000b00246293053d7mr5715097ljm.74.1650721188494; Sat, 23 Apr 2022 06:39:48 -0700 (PDT) Received: from eriador.lumag.spb.ru ([94.25.228.223]) by smtp.gmail.com with ESMTPSA id c21-20020a2ea795000000b0024ee0f8ef92sm544535ljf.36.2022.04.23.06.39.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Apr 2022 06:39:48 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 5/5] arm64: dts: qcom: sm8250: provide additional MSI interrupts Date: Sat, 23 Apr 2022 16:39:39 +0300 Message-Id: <20220423133939.2123449-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> References: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SM8250 each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe0 host. Tested on Qualcomm RB5 platform with first group of MSI interrupts being used by the PME and attached ath11k WiFi chip using second group of MSI interrupts. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 410272a1e19b..0659ac45c651 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1807,8 +1807,15 @@ pcie0: pci@1c00000 { ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */