From patchwork Mon Apr 25 18:22:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 565745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F42FC433FE for ; Mon, 25 Apr 2022 18:22:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238938AbiDYS0A (ORCPT ); Mon, 25 Apr 2022 14:26:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229668AbiDYSZ7 (ORCPT ); Mon, 25 Apr 2022 14:25:59 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11FC08930A; Mon, 25 Apr 2022 11:22:55 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id r13so31291419ejd.5; Mon, 25 Apr 2022 11:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qzYBm1Mg5ELnZ9VCZbiqSgNhv5b4M2fdTVMavRogM9Y=; b=dKbii47PzYUtTzXl3x34dyKNQhk2j/2D511n/Jbfg7hyiROT1AuEBZRi4jpwz4PR4g MVXSElIxfONshrRoSxxd5DjXj9glhaelxc17GEqqNwMNLKQerD9XoqBky+Mh5SsRy9Xz w+k2037LBcZGFrM5rYjiHf/CV6tlnYzcDIlMAaIwgYGYM6HJQTZVC0AMPWO+A4tPn64E oNPAsXIcAzoknRgdGnZXLgpGpkQ4Y0z3tBZ2CvXDtrbHkmvvM1kSGrsxKUDQ/EfmR2Nm h/EyRMJvrx8hG2vToTAING6dY5rTi+Qj/bz5ewm7qyLiUfTxI/3FwbwX7ikKoI38VzLX ggNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qzYBm1Mg5ELnZ9VCZbiqSgNhv5b4M2fdTVMavRogM9Y=; b=oi4xwJD09qehLw9CweMh6GrW8NnzY54pu48P+RR01HhHYN3NDIqREwYp42By05ac/O oWSUTrf3qAxxhklZ+50/fWz9y6iZPoI67aEPfHasw9p4PMMc3Nh8JUkcaFaZHI73L1Kk /xnIAdxMjMnRr9tXgxsoXzVbNLJB4swaHyy3tR3RVdDykWdm6M0g3wIQjAMxhgO97eCd b24Bxnc1MtxVwuRhrARtUHkHjHzIQSIiGNpFa+GM2lFxRliquqzj/YWT2hSa8/XPTNod RYxr3vWdC6EzcwOLdvkJn4pCuckA/AaC7nWL/SvXZuwk0mzh2i231TPUeaZ3fX8OqeHx bpNg== X-Gm-Message-State: AOAM5332EdaC7ffk7puLQGFmfwxuElNCdgvdb13Ant+AB09A5ycaNQQ4 OPFE9vWO2t1rBEKgTrQnbw4= X-Google-Smtp-Source: ABdhPJzqf8TDkVAWYyl2awXpsYE0dqc0V5iR3CO442aW5Dsip2FxjVztqZ4xH+J9d4V4TIWlWmi1eg== X-Received: by 2002:a17:906:8685:b0:6f3:9575:e352 with SMTP id g5-20020a170906868500b006f39575e352mr6059784ejx.622.1650910973455; Mon, 25 Apr 2022 11:22:53 -0700 (PDT) Received: from fedora.robimarko.hr (cpe-94-253-165-91.zg.cable.xnet.hr. [94.253.165.91]) by smtp.googlemail.com with ESMTPSA id h13-20020a170906590d00b006f39021e683sm1677210ejq.12.2022.04.25.11.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 11:22:52 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH 1/7] clk: qcom: ipq8074: fix NSS core PLL-s Date: Mon, 25 Apr 2022 20:22:43 +0200 Message-Id: <20220425182249.2753690-1-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration to work. So, obtain the regmap that is required for the Alpha PLL configuration and thus utilize the qcom_cc_really_probe() as we already have the regmap. Then utilize the Alpha PLL configs from the downstream QCA 5.4 based kernel to configure them. This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index e79c3329febd..2ebd1462db78 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4371,6 +4371,33 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static const struct alpha_pll_config ubi32_pll_config = { + .l = 0x4e, + .config_ctl_val = 0x200d4aa8, + .config_ctl_hi_val = 0x3c2, + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .pre_div_val = 0x0, + .pre_div_mask = BIT(12), + .post_div_val = 0x0, + .post_div_mask = GENMASK(9, 8), +}; + +static const struct alpha_pll_config nss_crypto_pll_config = { + .l = 0x3e, + .alpha = 0x0, + .alpha_hi = 0x80, + .config_ctl_val = 0x4001055b, + .main_output_mask = BIT(0), + .pre_div_val = 0x0, + .pre_div_mask = GENMASK(14, 12), + .post_div_val = 0x1 << 8, + .post_div_mask = GENMASK(11, 8), + .vco_mask = GENMASK(21, 20), + .vco_val = 0x0, + .alpha_en_mask = BIT(24), +}; + static struct clk_hw *gcc_ipq8074_hws[] = { &gpll0_out_main_div2.hw, &gpll6_out_main_div2.hw, @@ -4773,7 +4800,17 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { static int gcc_ipq8074_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &gcc_ipq8074_desc); + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); + + return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap); } static struct platform_driver gcc_ipq8074_driver = { From patchwork Mon Apr 25 18:22:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 567306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA92DC433F5 for ; Mon, 25 Apr 2022 18:22:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244323AbiDYS0C (ORCPT ); Mon, 25 Apr 2022 14:26:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244320AbiDYS0B (ORCPT ); Mon, 25 Apr 2022 14:26:01 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A45B8930A; Mon, 25 Apr 2022 11:22:56 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id u15so31204202ejf.11; Mon, 25 Apr 2022 11:22:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hzcS/ticocMB6pY40bBOU+jgqAFHJfeM6b9Rf1dfoWQ=; b=bEWbEo3Wln9xY4+Za34RvJ9WPedwk3r4AP/ks43UsvAY9ZdBU37Q9k4QbsYOX+JUo8 SKwBXZY8ONZbG8XAHMotKCJMMja/LUdOaVR7tMOkhPdKQQC1RZKMD5KSC0Y3S+GPHuKX bonxF24UziHb6ateQwmuS2dfveV4eBe8+YGxEvIocRmlKxC95YVuBGjsNZSDlczD8X5U hkQppSTsR8l5eD/cGVVA7YNsxl/nq8Hhel7JAU2588e7FfUxf6cbNm3Aed23XGrzQXAK QRh2M37pGW3BaFy7Uq06u/t3A/TBQoLkEDWTmoiVwFT3r9/7FE10yWkTzEJeVEJdydkX g4+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hzcS/ticocMB6pY40bBOU+jgqAFHJfeM6b9Rf1dfoWQ=; b=CkJyzFK6V4Dr5rVSEio0JOjWEOW4SLNfprfuJ95/pIbrWLCEQqIWQXoft8JJjx12Fs EnF1wTG4eWiyr0rKUujVbR+tJy02CVdiGX0jVdjDugkpXt6l3l2bO/FqkbwHKwgojP8a tyU9r8fz7oFnQLu+2AjVeypsfC8f0ofSi0Ak67nWTzTMkAJtS+VOb2hk4RBuOF2wAxS0 J1B7gQCJlYRo0Qbn5sR0/2lgya8y+OpQMv2XtHMI301fO92JmSGhoi2qL5MOloLu4eBv H5pfl0qMCFwyTmq34ZxHXhiwRnPtDDwTQBDN1khVPE92tuyOgfHcbx5DNNkzdywMToLp RTMQ== X-Gm-Message-State: AOAM531eA2oihajuowLgDL4vG+EqqsTs2Kkkm3UhMksXbEQ3IX7W1z3b KaRe9SeoksSr/pIQSNy0E98= X-Google-Smtp-Source: ABdhPJwXjKGZ10uS32h9MBla/5CxN3QS63VWvBPegOM1xH6Vx8RXzZt1t0a2kLribNr2mj9s86BynQ== X-Received: by 2002:a17:907:3f9c:b0:6f0:28d1:3ad6 with SMTP id hr28-20020a1709073f9c00b006f028d13ad6mr17702887ejc.365.1650910975072; Mon, 25 Apr 2022 11:22:55 -0700 (PDT) Received: from fedora.robimarko.hr (cpe-94-253-165-91.zg.cable.xnet.hr. [94.253.165.91]) by smtp.googlemail.com with ESMTPSA id h13-20020a170906590d00b006f39021e683sm1677210ejq.12.2022.04.25.11.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 11:22:54 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH 2/7] clk: qcom: ipq8074: disable USB GDSC-s SW_COLLAPSE Date: Mon, 25 Apr 2022 20:22:44 +0200 Message-Id: <20220425182249.2753690-2-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220425182249.2753690-1-robimarko@gmail.com> References: <20220425182249.2753690-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Like in IPQ6018 Qualcomm intentionally disables the SW_COLLAPSE on the USB GDSC-s in the downstream 5.4 kernel. This could potentially be better handled by utilizing the GDSC driver, but I am not familiar with it nor do I have datasheets. Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 2ebd1462db78..65249a03a672 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4806,6 +4806,11 @@ static int gcc_ipq8074_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + /* Disable SW_COLLAPSE for USB0 GDSCR */ + regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0); + /* Disable SW_COLLAPSE for USB1 GDSCR */ + regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, &nss_crypto_pll_config); From patchwork Mon Apr 25 18:22:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 565744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D275C433FE for ; Mon, 25 Apr 2022 18:23:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244334AbiDYS0F (ORCPT ); Mon, 25 Apr 2022 14:26:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244326AbiDYS0C (ORCPT ); Mon, 25 Apr 2022 14:26:02 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CC4F10783E; Mon, 25 Apr 2022 11:22:58 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id w16so10011664ejb.13; Mon, 25 Apr 2022 11:22:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m75BJZOFGksV9K5FuSEkA6hGYRiIrsUjCZWLuFWYFqk=; b=qFrO0EWvRwIyGjXnApcILNFr2JFmt5cXEsAaqpq1MDdv+jxQiZ9QTSTZTfDHBSCHI2 Pv14kztnSHyTAq79UPvVQvTxxEyOI3em3eblVE17X2FFd+k1q4BPSP2eafBR3z7L+vyN E127xGnzRT5TsPzwfEqWvsxketn9v1NF8ItO0Ubj9wSACVvskSydpnRGKwdjY4+PbvvR Ij+AhlXPI0q5fSAknFKjZZlslGkuj51wDWdQBcoBSZcvHHrjYc54Q8YLci3ALUpx4wmT 5uqHfTkgem7fCLD/5zqApqUNyTln5SmbQr9qZ04eNLcwN718lCVAJMRAthfQlfKH2E5N 65jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m75BJZOFGksV9K5FuSEkA6hGYRiIrsUjCZWLuFWYFqk=; b=dzzF3XAD3zJFtT1Pm2a2uNROUAT+fNJ43g/QDU7gdt6vNAM2gZqlSx4OGumDZjlHbw P9YROG1aKOSuncNuAOlDLrZyqMKr+nUhzkCrryKujRfef46uC0+YNqZ2e2fBOIs3POz3 b+oGrqOUbAzg/pI4eM9W+JOEcnbTByZryOQwNEb/23Kdai8RAd2Xym7X+BWPvs+HSTdR SIYXBGH5gLALK6IKO+D62mvfsgnc0q7glzQKgPWGSQBOZUspJ32DuAy/oAwoT4B6VZyV C+oKcpN4Q1Pe9oHPPVZ/vczGr2ZFRSYCVhS0o3PFV/2oz3+RFK0VPKlYLub2e4JIusjY R9qg== X-Gm-Message-State: AOAM530YypPvaWGhy4EPfshMnzQf9FfbIKFaIPtgAAhpJPn4+MRh2QuL LDkXNavQvqqR3vezQNMWlpQQ5j3x7LkTDQ== X-Google-Smtp-Source: ABdhPJzV/gEuu3H4IayAtKfQQpkAZpcN57oPHNKk3i+oLNAWHoY1ikvihU7vHVtiKtv40tq2LLvsYw== X-Received: by 2002:a17:906:3289:b0:6ef:ebf3:388 with SMTP id 9-20020a170906328900b006efebf30388mr17419668ejw.202.1650910976686; Mon, 25 Apr 2022 11:22:56 -0700 (PDT) Received: from fedora.robimarko.hr (cpe-94-253-165-91.zg.cable.xnet.hr. [94.253.165.91]) by smtp.googlemail.com with ESMTPSA id h13-20020a170906590d00b006f39021e683sm1677210ejq.12.2022.04.25.11.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 11:22:56 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH 3/7] clk: qcom: ipq8074: SW workaround for UBI32 PLL lock Date: Mon, 25 Apr 2022 20:22:45 +0200 Message-Id: <20220425182249.2753690-3-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220425182249.2753690-1-robimarko@gmail.com> References: <20220425182249.2753690-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it will cause the wait_for_pll() to timeout and thus return the error indicating that the PLL failed to lock. This is bug in Huayra PLL HW for which SW workaround is to set bit 26 of TEST_CTL register. This is ported from the QCA 5.4 based downstream kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 65249a03a672..969b38d4ba08 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4811,6 +4811,9 @@ static int gcc_ipq8074_probe(struct platform_device *pdev) /* Disable SW_COLLAPSE for USB1 GDSCR */ regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); + /* SW Workaround for UBI32 Huayra PLL */ + regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, &nss_crypto_pll_config); From patchwork Mon Apr 25 18:22:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 565742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E7F6C4167D for ; Mon, 25 Apr 2022 18:23:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244372AbiDYS0W (ORCPT ); Mon, 25 Apr 2022 14:26:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243733AbiDYS0E (ORCPT ); Mon, 25 Apr 2022 14:26:04 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5F76111CB4; Mon, 25 Apr 2022 11:22:59 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id w16so10011781ejb.13; Mon, 25 Apr 2022 11:22:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gvu98N+OnM/luhCQReYWbF6uR2tYpArXdOPWVpsiRFE=; b=NCfMAGpyr61KewdUdbjWyMKju/GFaW1uLf0R5mbdIzKkrnjW/iySxCT0jLufknsz6m WMa0rxN3gY0PRUE6wq9FJgJY6gY1hzzgsvjiCm4l2HImfkBtpbgB5dZkri+HqoXpphAc Zu84I2CTWl4pIsltG9rVZUUn7swSf3SN2ipyU4wIhlVPKPJjryqD/69jUF4JZQjBDTaR QlBQRFO3XFSfMBFK3MVwKiHqIqujBYq66JK7Ybu1vmeKvP+zhwQqiWdZYKuCMMxkXceb OYA37jHbQuXidZeqbyEA72LmccSSVwdpThdVCTJzTMNMmA1+bJr//QJl7xwjgeXZrpxM rVdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gvu98N+OnM/luhCQReYWbF6uR2tYpArXdOPWVpsiRFE=; b=Nb4w68aR+fExecOomBiWGvrKGjYMZ48gN3SQt+wlwUz4ayZ3nN71O3AmHulgaNkTPy CaEB3HHl8IxMq0cJzJndPonKY52V3+IZSybFrhombV4PcjLAEpmo3TmkuM64MzNppP+C JmN2030jV/sLXuHIO/u7yM0R2tlZ2XXiGxjzOF79e61YOw8M8ALSfcPQYF4zx9AcgCZj KR9UxtfkKfBqL+pgm84KkYkNIT0yAWkZwnpskEPFFCG4Vq1rOB2fnE7NqcN7CKWqEYTH Y1jVLHM/eCQ8FJ0ypI0OpQ/jz2LLNs/tfq2CMW7whtnS67uTi0d6kSfywUC81SK+oAmo RG5w== X-Gm-Message-State: AOAM533ifLPv9mDBmNeX7XTGDdd5mcX2SvbsBDflaPuACoFzvxFfoEtJ w0wvXMpIE/DKxlDBMm7b35I= X-Google-Smtp-Source: ABdhPJxYeRdgw7s6UWLZspqRmHYG9DJMH7dAXUm9Tk3Tt7gyDGSAf5mgdfnntKNs12BqzpDn+zUiYg== X-Received: by 2002:a17:907:1686:b0:6f0:c0f:2773 with SMTP id hc6-20020a170907168600b006f00c0f2773mr17640149ejc.445.1650910978204; Mon, 25 Apr 2022 11:22:58 -0700 (PDT) Received: from fedora.robimarko.hr (cpe-94-253-165-91.zg.cable.xnet.hr. [94.253.165.91]) by smtp.googlemail.com with ESMTPSA id h13-20020a170906590d00b006f39021e683sm1677210ejq.12.2022.04.25.11.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 11:22:57 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH 4/7] clk: qcom: ipq8074: fix NSS port frequency tables Date: Mon, 25 Apr 2022 20:22:46 +0200 Message-Id: <20220425182249.2753690-4-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220425182249.2753690-1-robimarko@gmail.com> References: <20220425182249.2753690-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org NSS port 5 and 6 frequency tables are currently broken and are causing a wide ranges of issue like 1G not working at all on port 6 or port 5 being clocked with 312 instead of 125 MHz as UNIPHY1 gets selected. So, update the frequency tables with the ones from the downstream QCA 5.4 based kernel which has already fixed this. Fixes: 7117a51ed303 ("clk: qcom: ipq8074: add NSS ethernet port clocks") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 969b38d4ba08..37af41d8b192 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -1788,8 +1788,10 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = { static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(25000000, P_UNIPHY1_RX, 12.5, 0, 0), + F(25000000, P_UNIPHY0_RX, 5, 0, 0), F(78125000, P_UNIPHY1_RX, 4, 0, 0), F(125000000, P_UNIPHY1_RX, 2.5, 0, 0), + F(125000000, P_UNIPHY0_RX, 1, 0, 0), F(156250000, P_UNIPHY1_RX, 2, 0, 0), F(312500000, P_UNIPHY1_RX, 1, 0, 0), { } @@ -1828,8 +1830,10 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = { static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), + F(25000000, P_UNIPHY0_TX, 5, 0, 0), F(78125000, P_UNIPHY1_TX, 4, 0, 0), F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), + F(125000000, P_UNIPHY0_TX, 1, 0, 0), F(156250000, P_UNIPHY1_TX, 2, 0, 0), F(312500000, P_UNIPHY1_TX, 1, 0, 0), { } @@ -1867,8 +1871,10 @@ static struct clk_regmap_div nss_port5_tx_div_clk_src = { static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY2_RX, 5, 0, 0), F(25000000, P_UNIPHY2_RX, 12.5, 0, 0), F(78125000, P_UNIPHY2_RX, 4, 0, 0), + F(125000000, P_UNIPHY2_RX, 1, 0, 0), F(125000000, P_UNIPHY2_RX, 2.5, 0, 0), F(156250000, P_UNIPHY2_RX, 2, 0, 0), F(312500000, P_UNIPHY2_RX, 1, 0, 0), @@ -1907,8 +1913,10 @@ static struct clk_regmap_div nss_port6_rx_div_clk_src = { static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY2_TX, 5, 0, 0), F(25000000, P_UNIPHY2_TX, 12.5, 0, 0), F(78125000, P_UNIPHY2_TX, 4, 0, 0), + F(125000000, P_UNIPHY2_TX, 1, 0, 0), F(125000000, P_UNIPHY2_TX, 2.5, 0, 0), F(156250000, P_UNIPHY2_TX, 2, 0, 0), F(312500000, P_UNIPHY2_TX, 1, 0, 0), From patchwork Mon Apr 25 18:22:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 567304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DB81C43219 for ; Mon, 25 Apr 2022 18:23:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244329AbiDYS0V (ORCPT ); Mon, 25 Apr 2022 14:26:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244345AbiDYS0L (ORCPT ); Mon, 25 Apr 2022 14:26:11 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FD9C8930A; Mon, 25 Apr 2022 11:23:01 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id y3so10901158ejo.12; Mon, 25 Apr 2022 11:23:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sy9YYlqoJiTojSfiEVFCuiM/Ui3tj6aKx8yzbCiNSKs=; b=gWJUKBpSNwQFr5FQCSopcOkFGCSxYO3JlAbeOsu7x1AJ/1kgbLtOit+EL5oX5DYcy+ yWAH3TZfoNrhUhWEeNahXRJFVDxeaZdPJ7N60qTt4EPNaF/NviRRjU8RxFcMXSHnStO+ nFrHoZ3XKbFdlQtwQ6PHTJ3a2YRnSPlX5IYjeNIOB6O71ypz2zNzPh8S2iYgYvdFyDx2 N8MWLfpyWU8qYxN8NwvGfSuxcd0r2mU32pAg9e0WnJCktAQRu1PrMMAUtuv5abhq4wKQ kXbJSZ4MaXf3eyNMUSOJj4cM48BpKqZDaMT9CSaIUogNMpIB1vXWWD0fJH4+LSMl0YJE AWRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sy9YYlqoJiTojSfiEVFCuiM/Ui3tj6aKx8yzbCiNSKs=; b=5quaRHLe9z3i5gcqChriCo8JbFYW1haje4xMl4iELiQOQZeH1IBb+WOIS24E1sKIgQ Z69LmoaFgOaLThWwU6lZaryY672lo3h7caaU13zums8/YZReVMTvD5XNUA15FmRxdCQ7 jC/Kc+an8o1nJVe67FjG080dzoCTlEV9HzvRnMt1EgRDJrU+Ae9q/mrQohm7WjcjXsiR El53BS1o5mFTxMuzZz5KQq2XPMJtgKJ3phuvcjvoNExg/eAoRkVmdf92iudk6H4YS1w5 /7OkXD+fGWTkwLo1+cZKHsoruy8h12Rtm0eA1Dy28qD5ZMN2cnq2FW82FlT+zllZopSh 3ZAQ== X-Gm-Message-State: AOAM531PDlqhLhJctSQcQKOVqArlMOHr9DDTvT2l0/dGDlDtK3BN7WRY mkdAEw3Ro8yroNp8trIVh+E= X-Google-Smtp-Source: ABdhPJwTJ8vN7QbZjR6I7kkhlLs864ySN5/U5PHeZeg8Vr/EZIRGA3WvQ+7FlD8PpWlxTuiA5NRUyA== X-Received: by 2002:a17:907:1c92:b0:6f0:f17:14a with SMTP id nb18-20020a1709071c9200b006f00f17014amr17007620ejc.475.1650910979850; Mon, 25 Apr 2022 11:22:59 -0700 (PDT) Received: from fedora.robimarko.hr (cpe-94-253-165-91.zg.cable.xnet.hr. [94.253.165.91]) by smtp.googlemail.com with ESMTPSA id h13-20020a170906590d00b006f39021e683sm1677210ejq.12.2022.04.25.11.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 11:22:59 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH 5/7] clk: qcom: ipq8074: add PPE crypto clock Date: Mon, 25 Apr 2022 20:22:47 +0200 Message-Id: <20220425182249.2753690-5-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220425182249.2753690-1-robimarko@gmail.com> References: <20220425182249.2753690-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The built-in PPE engine has a dedicated clock for the EIP-197 crypto engine. So, since the required clock currently missing add support for it. Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 37af41d8b192..e6625b9fab35 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3182,6 +3182,24 @@ static struct clk_branch gcc_nss_ptp_ref_clk = { }, }; +static struct clk_branch gcc_crypto_ppe_clk = { + .halt_reg = 0x68310, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x68310, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_ppe_clk", + .parent_names = (const char *[]){ + "nss_ppe_clk_src" + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nssnoc_ce_apb_clk = { .halt_reg = 0x6830c, .clkr = { @@ -4644,6 +4662,7 @@ static struct clk_regmap *gcc_ipq8074_clks[] = { [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, }; static const struct qcom_reset_map gcc_ipq8074_resets[] = { From patchwork Mon Apr 25 18:22:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 565743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEC8EC433EF for ; Mon, 25 Apr 2022 18:23:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244365AbiDYS0U (ORCPT ); Mon, 25 Apr 2022 14:26:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244352AbiDYS0M (ORCPT ); Mon, 25 Apr 2022 14:26:12 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E7B8112449; Mon, 25 Apr 2022 11:23:03 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id z19so6217755edx.9; Mon, 25 Apr 2022 11:23:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cqD7UOhZCtWdKNLvjvzBP8sV3y6BYgIA/pnNxZjz8oc=; b=gPvnxTLlvLR8cTTUXmjcl1R9wSZiNpgICF2IyBg6eezIoDI/QZb9sNe02E2peEg6Zl B4OZrlq5PScSUaMoLo74jDHXFO9P5DSsM0rXvHmCXzKnIYQsTv0pQj84XuNuknGd8O9E vuABKLEr52M7GWYi/eGoe6zcGsmOjazA/oQaoxhnJ3P703O/x4t+XERyO07eV2GMggNS amCewNSoN8rPp+57j7lQnAvqHrm74i2OvpxuaDnz+hWkRhQ/I1qmF9/cK5mHTqeYFHc9 v6hJzKbQNaej4wMOR62pNNTCEL8582/iTpNUzZ4AiWU4nS7SXPo3tTTHHJkrT7jVb80a ymwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cqD7UOhZCtWdKNLvjvzBP8sV3y6BYgIA/pnNxZjz8oc=; b=AhI19RttwrQgOsKXEn2oRwO1d0PcxsQ/FmW+obNfSwaxhQSHZ1Kl4SA/ME9RfQ2H0l JiuwIyE9SfGlsenz15iBUe/EC5PyuzlNeYGRHHci6+5xanykEBM8qALmGR5QUsOontZf 1JhTQtTHw0JBB4phzGhfAXJgnWmkn6qD6oKX9OwlOAAs5go16SvZqbcpSIeS0PO3Gg3T o+n6fIEMOngQUc//VxQ5YvCdZMcDPbZhN6vuFD5xkO+FMkPVsYdys/r4JHjANjkVjI4q LOV9p17QCeZQJZuXsTULf82RLEth2Zk1xleyd4ASpuxI8j1RG1rMa3cpRimlaxAnYmS8 fUHg== X-Gm-Message-State: AOAM5308vpq9kn1mNsFbLc3QVzdfy7x70b6eHtrwOcKr/8GshXYohtwZ VFXL6JGLRevqft9Woehrtg/dSgH0/Rl21A== X-Google-Smtp-Source: ABdhPJzVLO9S/2ivLHgLiR+ZbsKq/+AUaDHJSmuxinNEjlWRlLnYSk+IYmvc6LtVVr6jL/Du+x1tdw== X-Received: by 2002:a05:6402:26c9:b0:423:d545:9d49 with SMTP id x9-20020a05640226c900b00423d5459d49mr20466407edd.242.1650910981728; Mon, 25 Apr 2022 11:23:01 -0700 (PDT) Received: from fedora.robimarko.hr (cpe-94-253-165-91.zg.cable.xnet.hr. [94.253.165.91]) by smtp.googlemail.com with ESMTPSA id h13-20020a170906590d00b006f39021e683sm1677210ejq.12.2022.04.25.11.23.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 11:23:01 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH 6/7] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock Date: Mon, 25 Apr 2022 20:22:48 +0200 Message-Id: <20220425182249.2753690-6-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220425182249.2753690-1-robimarko@gmail.com> References: <20220425182249.2753690-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add binding for the PPE crypto clock in IPQ8074. Signed-off-by: Robert Marko --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 9b1c42bc430c..2197185cb1a2 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -233,6 +233,7 @@ #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 #define GCC_PCIE0_RCHNG_CLK_SRC 225 #define GCC_PCIE0_RCHNG_CLK 226 +#define GCC_CRYPTO_PPE_CLK 227 #define GCC_BLSP1_BCR 0 #define GCC_BLSP1_QUP1_BCR 1 From patchwork Mon Apr 25 18:22:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 567305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24F05C433FE for ; Mon, 25 Apr 2022 18:23:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244353AbiDYS0O (ORCPT ); Mon, 25 Apr 2022 14:26:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244361AbiDYS0N (ORCPT ); Mon, 25 Apr 2022 14:26:13 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34519112D86; Mon, 25 Apr 2022 11:23:05 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id g20so19487696edw.6; Mon, 25 Apr 2022 11:23:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=skFtK8ncz5bLZC06oqy32h7OgmhSsmfTgt/itwzobJE=; b=dwRQLvdu6XNrpRRZMbEGioslLD2l3FZDjYQUVE6jvecnieVuQ/DBGDTQ1mnBuAkmCX ci1z0BpH9hSRLYWoLG6OxQGaJWx6Aj5OcezkTVpR/kAEWtx9OSgpvOl/iZ6B7MZb9pWz EDVp1s1DbbZnAUVGS/hNccs3xUjeXOOZKPBZ4v1kkxCUB52HGNid31eyeHq1DSBKdL11 N38m3Frn0OJTMsp6LTxjt+yFmiHfKRaPTAKOTnzki1To8McjxmI3AvDGslKJLunuBCDY 09G/a7YBiNE6f/seRgVhIRKiMWKr1XLLrPpL0T31bs7WeRzUuqafnyC4Z12N7nWgZle6 /tAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=skFtK8ncz5bLZC06oqy32h7OgmhSsmfTgt/itwzobJE=; b=2S9kYFK0rLBQtkKpt+FnGeIdWl+NFykSPHY27MPPtYF6fhBTf6Ztl8b3bguEXF7pEW euX9POwk6eqmMy8g2LLFMMjStPkexbH+99858uovtOgkLWCjnERVaXW4PBJHOUDfKcPc kaEP5OOI2IwCqkmxNY9GCZa3bsDTkqMhGcnoswJXnEK5ZyIYLbACWX00pOw/s73s96TZ RiQJsOIS6YsYUOGe73tkCdm/ysvnImxTSM3L3Jz6a53NFj4y9MQwwWcjwKeyq2vPTLBE XuaPPnaWHuTqMvnI9dpHXvMneVyuxc/T4zlWwi+r+md6+vMd0djsB4UoRXe7I9TF7lSM fWsw== X-Gm-Message-State: AOAM530LF+jmFHsgHcIT5lbjnjYZc8O8WMIGgCOyMPlUk8psUZV1CfWe F2xq6a6Tm+vxMJtg/RqnGSg= X-Google-Smtp-Source: ABdhPJxaljTXaNgBN3bYcRjbPSiSTMx4+U+v5Egsu66uRc/+ybXlZidl56pqtndCU45GhBwlMyXlrw== X-Received: by 2002:a05:6402:3593:b0:425:dfd4:2947 with SMTP id y19-20020a056402359300b00425dfd42947mr9098632edc.137.1650910983810; Mon, 25 Apr 2022 11:23:03 -0700 (PDT) Received: from fedora.robimarko.hr (cpe-94-253-165-91.zg.cable.xnet.hr. [94.253.165.91]) by smtp.googlemail.com with ESMTPSA id h13-20020a170906590d00b006f39021e683sm1677210ejq.12.2022.04.25.11.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 11:23:03 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH 7/7] clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks Date: Mon, 25 Apr 2022 20:22:49 +0200 Message-Id: <20220425182249.2753690-7-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220425182249.2753690-1-robimarko@gmail.com> References: <20220425182249.2753690-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently, attempting to enable the UBI clocks will cause the stuck at off warning to be printed and clk_enable will fail. [ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off' Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY flag on UBI clocks, so lets do the same. Fixes: 5736294aef83 ("clk: qcom: ipq8074: add NSS clocks") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index e6625b9fab35..54f292ab1f0d 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3372,6 +3372,7 @@ static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi0_ahb_clk = { .halt_reg = 0x6820c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6820c, .enable_mask = BIT(0), @@ -3389,6 +3390,7 @@ static struct clk_branch gcc_ubi0_ahb_clk = { static struct clk_branch gcc_ubi0_axi_clk = { .halt_reg = 0x68200, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68200, .enable_mask = BIT(0), @@ -3406,6 +3408,7 @@ static struct clk_branch gcc_ubi0_axi_clk = { static struct clk_branch gcc_ubi0_nc_axi_clk = { .halt_reg = 0x68204, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68204, .enable_mask = BIT(0), @@ -3423,6 +3426,7 @@ static struct clk_branch gcc_ubi0_nc_axi_clk = { static struct clk_branch gcc_ubi0_core_clk = { .halt_reg = 0x68210, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68210, .enable_mask = BIT(0), @@ -3440,6 +3444,7 @@ static struct clk_branch gcc_ubi0_core_clk = { static struct clk_branch gcc_ubi0_mpt_clk = { .halt_reg = 0x68208, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68208, .enable_mask = BIT(0), @@ -3457,6 +3462,7 @@ static struct clk_branch gcc_ubi0_mpt_clk = { static struct clk_branch gcc_ubi1_ahb_clk = { .halt_reg = 0x6822c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6822c, .enable_mask = BIT(0), @@ -3474,6 +3480,7 @@ static struct clk_branch gcc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi1_axi_clk = { .halt_reg = 0x68220, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68220, .enable_mask = BIT(0), @@ -3491,6 +3498,7 @@ static struct clk_branch gcc_ubi1_axi_clk = { static struct clk_branch gcc_ubi1_nc_axi_clk = { .halt_reg = 0x68224, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68224, .enable_mask = BIT(0), @@ -3508,6 +3516,7 @@ static struct clk_branch gcc_ubi1_nc_axi_clk = { static struct clk_branch gcc_ubi1_core_clk = { .halt_reg = 0x68230, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68230, .enable_mask = BIT(0), @@ -3525,6 +3534,7 @@ static struct clk_branch gcc_ubi1_core_clk = { static struct clk_branch gcc_ubi1_mpt_clk = { .halt_reg = 0x68228, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68228, .enable_mask = BIT(0),