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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id o3si16514684pll.201.2018.12.19.12.40.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 12:40:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=k3dTF434; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5AB5B211A2D84; Wed, 19 Dec 2018 12:40:39 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::343; helo=mail-wm1-x343.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 50B29211A2099 for ; Wed, 19 Dec 2018 12:40:36 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id a62so7385654wmh.4 for ; Wed, 19 Dec 2018 12:40:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w4K3qfvI+jUTnTQSAKtVMlbhWvEpnmcmuOSsW7x4jYM=; b=k3dTF434q+/2c6ZpZrthKHnZ58xa2dyV+qyZiUobsXswtZ4zOZo9HewPhuwxk7TOTF gotHdtL1PqQvu0Gq+K5mbti+phJGMcNG9Owl7mu+o+WC6znWUE++WWR3+12wAX0lNV3i Dq37HQBtBlI3sIHnKkzm1HaqqHw1e8cTofv/E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w4K3qfvI+jUTnTQSAKtVMlbhWvEpnmcmuOSsW7x4jYM=; b=bldH+Ob8Gel+pm2/a3gcvXghRQGi1bY7DK+9CWVZNUgOciOWR5qTrVu1nGjuQ7cj9X 1zjHve04DYd7I5587FrFL2gEbVzKcJVXeexmSp3kI8lPioZ5Xw2CTP4pV486u+gx7uB3 YXq1frV9GQpShpW7aidiE+VyKQpN/GJdBL5VMxg88tj72z2YNWpsr+o+7DGwYSwIlx/a krtj02ETHr2TwLbUJrTf7uO2vDxoZuYETHGFSRRuGzhovynBjMg9YmEfqcikgNLm/4WT ZFT5kriUiMW92bg2DrDSNdlmNvK9nH8DFCjyp5a3CxOoU2wpBYJa4Or/ZfkeEKI1KdRf LJRw== X-Gm-Message-State: AA+aEWZQviZnAYVypGjLhx8n1vYkY/lW0SxASLqTnt0t3MIXh2P5lGUj Lu3gz+4pQXBOm7WR8Du/WQBVOJ8+15cUjw== X-Received: by 2002:a1c:dc02:: with SMTP id t2mr8334448wmg.78.1545252034265; Wed, 19 Dec 2018 12:40:34 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:e5c9:6e00:25cb:e32e]) by smtp.gmail.com with ESMTPSA id h16sm13738439wrb.62.2018.12.19.12.40.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 12:40:33 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 19 Dec 2018 21:40:20 +0100 Message-Id: <20181219204023.6317-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181219204023.6317-1-ard.biesheuvel@linaro.org> References: <20181219204023.6317-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH v2 1/4] ArmPlatformPkg/SP805WatchdogDxe: cosmetic cleanup X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Before fixing the SP805 driver, let's clean it up a bit. No functional changes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf | 11 +-- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c | 97 ++++++++++---------- 2 files changed, 52 insertions(+), 56 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf index 37924f2e3cd2..c3971fb035d3 100644 --- a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf +++ b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf @@ -1,6 +1,7 @@ /** @file * * Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -18,35 +19,29 @@ [Defines] FILE_GUID = ebd705fb-fa92-46a7-b32b-7f566d944614 MODULE_TYPE = DXE_DRIVER VERSION_STRING = 1.0 - ENTRY_POINT = SP805Initialize [Sources.common] SP805Watchdog.c [Packages] - MdePkg/MdePkg.dec - EmbeddedPkg/EmbeddedPkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec [LibraryClasses] BaseLib - BaseMemoryLib DebugLib IoLib - PcdLib - UefiLib UefiBootServicesTableLib UefiDriverEntryPoint - UefiRuntimeServicesTableLib [Pcd] gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz [Protocols] - gEfiWatchdogTimerArchProtocolGuid + gEfiWatchdogTimerArchProtocolGuid ## ALWAYS_PRODUCES [Depex] TRUE diff --git a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c index 0a9f64095bf8..12c2f0a1fe49 100644 --- a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c +++ b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c @@ -1,6 +1,7 @@ /** @file * * Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -19,16 +20,13 @@ #include #include #include -#include #include -#include -#include #include #include "SP805Watchdog.h" -EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL; +STATIC EFI_EVENT mEfiExitBootServicesEvent; /** Make sure the SP805 registers are unlocked for writing. @@ -43,8 +41,8 @@ SP805Unlock ( VOID ) { - if( MmioRead32(SP805_WDOG_LOCK_REG) == SP805_WDOG_LOCK_IS_LOCKED ) { - MmioWrite32(SP805_WDOG_LOCK_REG, SP805_WDOG_SPECIAL_UNLOCK_CODE); + if (MmioRead32 (SP805_WDOG_LOCK_REG) == SP805_WDOG_LOCK_IS_LOCKED) { + MmioWrite32 (SP805_WDOG_LOCK_REG, SP805_WDOG_SPECIAL_UNLOCK_CODE); } } @@ -61,9 +59,9 @@ SP805Lock ( VOID ) { - if( MmioRead32(SP805_WDOG_LOCK_REG) == SP805_WDOG_LOCK_IS_UNLOCKED ) { + if (MmioRead32 (SP805_WDOG_LOCK_REG) == SP805_WDOG_LOCK_IS_UNLOCKED) { // To lock it, just write in any number (except the special unlock code). - MmioWrite32(SP805_WDOG_LOCK_REG, SP805_WDOG_LOCK_IS_LOCKED); + MmioWrite32 (SP805_WDOG_LOCK_REG, SP805_WDOG_LOCK_IS_LOCKED); } } @@ -77,8 +75,8 @@ SP805Stop ( ) { // Disable interrupts - if ( (MmioRead32(SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) != 0 ) { - MmioAnd32(SP805_WDOG_CONTROL_REG, ~SP805_WDOG_CTRL_INTEN); + if ((MmioRead32 (SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) != 0) { + MmioAnd32 (SP805_WDOG_CONTROL_REG, ~SP805_WDOG_CTRL_INTEN); } } @@ -94,8 +92,8 @@ SP805Start ( ) { // Enable interrupts - if ( (MmioRead32(SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) == 0 ) { - MmioOr32(SP805_WDOG_CONTROL_REG, SP805_WDOG_CTRL_INTEN); + if ((MmioRead32 (SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) == 0) { + MmioOr32 (SP805_WDOG_CONTROL_REG, SP805_WDOG_CTRL_INTEN); } } @@ -103,6 +101,7 @@ SP805Start ( On exiting boot services we must make sure the SP805 Watchdog Timer is stopped. **/ +STATIC VOID EFIAPI ExitBootServicesEvent ( @@ -110,9 +109,9 @@ ExitBootServicesEvent ( IN VOID *Context ) { - SP805Unlock(); - SP805Stop(); - SP805Lock(); + SP805Unlock (); + SP805Stop (); + SP805Lock (); } /** @@ -142,10 +141,11 @@ ExitBootServicesEvent ( previously registered. **/ +STATIC EFI_STATUS EFIAPI SP805RegisterHandler ( - IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction ) { @@ -182,22 +182,24 @@ SP805RegisterHandler ( @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error. **/ +STATIC EFI_STATUS EFIAPI SP805SetTimerPeriod ( - IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, IN UINT64 TimerPeriod // In 100ns units ) { - EFI_STATUS Status = EFI_SUCCESS; + EFI_STATUS Status; UINT64 Ticks64bit; - SP805Unlock(); + SP805Unlock (); - if( TimerPeriod == 0 ) { + Status = EFI_SUCCESS; + + if (TimerPeriod == 0) { // This is a watchdog stop request - SP805Stop(); - goto EXIT; + SP805Stop (); } else { // Calculate the Watchdog ticks required for a delay of (TimerTicks * 100) nanoseconds // The SP805 will count down to ZERO once, generate an interrupt and @@ -211,10 +213,11 @@ SP805SetTimerPeriod ( // // WatchdogTicks = (TimerPeriod * SP805_CLOCK_FREQUENCY) / 20 MHz ; - Ticks64bit = DivU64x32(MultU64x32(TimerPeriod, (UINTN)PcdGet32(PcdSP805WatchdogClockFrequencyInHz)), 20000000); + Ticks64bit = MultU64x32 (TimerPeriod, PcdGet32 (PcdSP805WatchdogClockFrequencyInHz)); + Ticks64bit = DivU64x32 (Ticks64bit, 20000000); // The registers in the SP805 are only 32 bits - if(Ticks64bit > (UINT64)0xFFFFFFFF) { + if (Ticks64bit > MAX_UINT32) { // We could load the watchdog with the maximum supported value but // if a smaller value was requested, this could have the watchdog // triggering before it was intended. @@ -224,15 +227,15 @@ SP805SetTimerPeriod ( } // Update the watchdog with a 32-bit value. - MmioWrite32(SP805_WDOG_LOAD_REG, (UINT32)Ticks64bit); + MmioWrite32 (SP805_WDOG_LOAD_REG, (UINT32)Ticks64bit); // Start the watchdog - SP805Start(); + SP805Start (); } - EXIT: +EXIT: // Ensure the watchdog is locked before exiting. - SP805Lock(); + SP805Lock (); return Status; } @@ -251,14 +254,14 @@ SP805SetTimerPeriod ( @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. **/ +STATIC EFI_STATUS EFIAPI SP805GetTimerPeriod ( - IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, OUT UINT64 *TimerPeriod ) { - EFI_STATUS Status = EFI_SUCCESS; UINT64 ReturnValue; if (TimerPeriod == NULL) { @@ -266,19 +269,19 @@ SP805GetTimerPeriod ( } // Check if the watchdog is stopped - if ( (MmioRead32(SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) == 0 ) { + if ((MmioRead32 (SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) == 0) { // It is stopped, so return zero. ReturnValue = 0; } else { // Convert the Watchdog ticks into TimerPeriod // Ensure 64bit arithmetic throughout because the Watchdog ticks may already // be at the maximum 32 bit value and we still need to multiply that by 600. - ReturnValue = MultU64x32( MmioRead32(SP805_WDOG_LOAD_REG), 600 ); + ReturnValue = MultU64x32 (MmioRead32 (SP805_WDOG_LOAD_REG), 600); } *TimerPeriod = ReturnValue; - return Status; + return EFI_SUCCESS; } /** @@ -313,10 +316,10 @@ SP805GetTimerPeriod ( Retrieves the period of the timer interrupt in 100 nS units. **/ -EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = { - (EFI_WATCHDOG_TIMER_REGISTER_HANDLER) SP805RegisterHandler, - (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD) SP805SetTimerPeriod, - (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD) SP805GetTimerPeriod +STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = { + SP805RegisterHandler, + SP805SetTimerPeriod, + SP805GetTimerPeriod }; /** @@ -347,12 +350,12 @@ SP805Initialize ( SP805Stop (); // Set the watchdog to reset the board when triggered - if ((MmioRead32(SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_RESEN) == 0) { + if ((MmioRead32 (SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_RESEN) == 0) { MmioOr32 (SP805_WDOG_CONTROL_REG, SP805_WDOG_CTRL_RESEN); } // Prohibit any rogue access to SP805 registers - SP805Lock(); + SP805Lock (); // // Make sure the Watchdog Timer Architectural Protocol has not been installed in the system yet. @@ -361,28 +364,26 @@ SP805Initialize ( ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid); // Register for an ExitBootServicesEvent - Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent); - if (EFI_ERROR(Status)) { + Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, + ExitBootServicesEvent, NULL, &mEfiExitBootServicesEvent); + if (EFI_ERROR (Status)) { Status = EFI_OUT_OF_RESOURCES; goto EXIT; } // Install the Timer Architectural Protocol onto a new handle Handle = NULL; - Status = gBS->InstallMultipleProtocolInterfaces( + Status = gBS->InstallMultipleProtocolInterfaces ( &Handle, - &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer, + &gEfiWatchdogTimerArchProtocolGuid, &mWatchdogTimer, NULL ); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { Status = EFI_OUT_OF_RESOURCES; goto EXIT; } EXIT: - if(EFI_ERROR(Status)) { - // The watchdog failed to initialize - ASSERT(FALSE); - } + ASSERT_EFI_ERROR (Status); return Status; } From patchwork Wed Dec 19 20:40:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 154295 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5369531ljp; Wed, 19 Dec 2018 12:40:42 -0800 (PST) X-Google-Smtp-Source: AFSGD/VBX1fO9nMROFItO9DEsvZoozg/LrlS0jeGHPDNQ7Ad5hojSaV0lHBX56w1UeepPaGFqRps X-Received: by 2002:a17:902:7e44:: with SMTP id a4mr21773978pln.338.1545252042365; Wed, 19 Dec 2018 12:40:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545252042; cv=none; d=google.com; s=arc-20160816; b=H8pAMnGN+DPELTI0Pc3sMWwGg2DcYNGWgPHxTYW9NRz9emM8SLzpmf8rcTiB0RvgCt jfQNmTE2XU6eyfIvWH9stuI1NyS9QfY0eoLPea28QNOO+8hYX2tqXikQJJ2nBe2UFTgF FHeTbMl+MSq1N/bZL46L1/vvJOW4qT510kFgHYjvYMFwB0kFtO1Wk1DWLE+3Sguzolas m9Jzk3/j6SxyGcKREaKTgmekB+3R3FK3vhehQCon/PjEc61zhyD7VPHnTtmHNyEYbDb0 472MPMvVdBU+NKu4w0ayFIyCEpdtoMxAwt7QyMvl4AyyP/eFg1gM4l6ebx4mSsUGDAEO aeNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:delivered-to; bh=nIRbQq5HG5DqY8frNlQ1PfPxHdGfDYwB1x431zD3TL4=; b=mEZO081gOcF+PRDotWTDG+TPgJTOzSgIiW7++WbMABqIDxeAGAb4NFElG8VQyhlCN8 KHHoqmuBWST9o3XFNwgXs+I23ItjtikhYW3EEjy1+730ZT0aHHUnypefvsrun+BO/zOu sgLJBC3c4Qag8tQLhuYgMZl0GvU/GgAK0I1dkJWW3eyN3GMQfLxjFZ+ijcUXbF7yCx2B +4ECneWIAW9TaSuzJwtujfUSI6QogV5ab2TrA0K3uzdnrCLDzs/DI4dDQ+FeqG75Lmds +ZZz/V2Ar36R0dGK+42s03qE35XbJaUadUfgTie2b+05YKsbih6u7h4UwbraL/UWJfIV cpZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=G9zWn12T; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id x191si17294913pfd.220.2018.12.19.12.40.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 12:40:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=G9zWn12T; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 87A182194D3B9; Wed, 19 Dec 2018 12:40:39 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B0B9F2194D3B9 for ; Wed, 19 Dec 2018 12:40:37 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id f81so7805632wmd.4 for ; Wed, 19 Dec 2018 12:40:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iPLkFCM06ALgy3hxrYzfLgIPKECfrKeJQRUz5Z6YizU=; b=G9zWn12TvwGUOiYVn2/tKKf3NnihWwIJraziv3aXRF2yTEQv7Sbig2Mz35Yo9BbzYf yaQs0j1blju9SzE/+ca0HEyzNWCNP3i1TLAQ+2l3AWOkG9C8tO6wtZJYqWvf8zaR09DE SXeGRDI2qBxytGZ8CFzXSmlrNUQwlpv2eum5c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iPLkFCM06ALgy3hxrYzfLgIPKECfrKeJQRUz5Z6YizU=; b=F52bEdHzHJFJ4GE6H6HBrKR07QESyDT2ICZejj6+NxYGfVDrzwnOfknJxL7yaAngNc mKy74J2OMwoesM3/7Uod3E71P3l2anMejsNXeBtAUqmk+9HQ8j59O72yO+41e4lfY/03 7b1PmB5Ro9pWr3yKUxgRmOjR59HnLK/uWnypHvmnDOkXOxy//mY9ZPR/0cVSN71awCr6 m8G5NLHtLT29d8XoiOFox0UxzmiEg/qEfwas1mPltSWfK57giKMsbnCGTFcvrFbxLe8c nT2G/kz1wzLhtC+66WMtmd3Dn5Mx93tcCLcO1GuI9AK469PFJNJCHuaFW++D0+5EiaVr Xn9g== X-Gm-Message-State: AA+aEWb7TXP5kv6lUDDcMMX/N7l+VnWRT3UUOTzQO1R/UVO5PgtGnHpi BxkhBz0b3lGIrKb+d01npPGTgD9Eab1zMA== X-Received: by 2002:a7b:c156:: with SMTP id z22mr8204757wmi.24.1545252035780; Wed, 19 Dec 2018 12:40:35 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:e5c9:6e00:25cb:e32e]) by smtp.gmail.com with ESMTPSA id h16sm13738439wrb.62.2018.12.19.12.40.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 12:40:34 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 19 Dec 2018 21:40:21 +0100 Message-Id: <20181219204023.6317-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181219204023.6317-1-ard.biesheuvel@linaro.org> References: <20181219204023.6317-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH v2 2/4] ArmPlatformPkg/SP805WatchdogDxe: switch to interrupt mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The SP805 watchdog driver doesn't implement the PI watchdog protocol fully, but always simply resets the system if the watchdog time runs out. However, the hardware does support the intended usage model, as long as the SP805 is wired up correctly. So let's implement interrupt based mode involving a handler that is registered by the DXE core and invoked when the watchdog runs out. In the interrupt handler, we invoke the notify function if one was registered, or call the ResetSystem() runtime service otherwise (as per the UEFI spec) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmPlatformPkg.dec | 1 + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf | 6 +- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c | 100 +++++++++++++++----- 3 files changed, 80 insertions(+), 27 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 5f67e7415469..44c00bd0c133 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -70,6 +70,7 @@ [PcdsFixedAtBuild.common] ## SP805 Watchdog gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021 + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogInterrupt|0|UINT32|0x0000002E ## PL011 UART gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F diff --git a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf index c3971fb035d3..0e744deeca8d 100644 --- a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf +++ b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf @@ -27,6 +27,7 @@ [Sources.common] [Packages] ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec [LibraryClasses] @@ -35,13 +36,16 @@ [LibraryClasses] IoLib UefiBootServicesTableLib UefiDriverEntryPoint + UefiRuntimeServicesTableLib [Pcd] gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogInterrupt [Protocols] + gHardwareInterruptProtocolGuid ## ALWAYS_CONSUMES gEfiWatchdogTimerArchProtocolGuid ## ALWAYS_PRODUCES [Depex] - TRUE + gHardwareInterruptProtocolGuid diff --git a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c index 12c2f0a1fe49..5bbb12af6019 100644 --- a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c +++ b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c @@ -21,12 +21,17 @@ #include #include #include +#include +#include #include #include "SP805Watchdog.h" -STATIC EFI_EVENT mEfiExitBootServicesEvent; +STATIC EFI_EVENT mEfiExitBootServicesEvent; +STATIC EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterrupt; +STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify; +STATIC UINT32 mTimerPeriod; /** Make sure the SP805 registers are unlocked for writing. @@ -65,6 +70,33 @@ SP805Lock ( } } +STATIC +VOID +EFIAPI +SP805InterruptHandler ( + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + SP805Unlock (); + MmioWrite32 (SP805_WDOG_INT_CLR_REG, 0); // write of any value clears the irq + SP805Lock (); + + mInterrupt->EndOfInterrupt (mInterrupt, Source); + + // + // The notify function should be called with the elapsed number of ticks + // since the watchdog was armed, which should exceed the timer period. + // We don't actually know the elapsed number of ticks, so let's return + // the timer period plus 1. + // + if (mWatchdogNotify != NULL) { + mWatchdogNotify (mTimerPeriod + 1); + } + + gRT->ResetSystem (EfiResetCold, EFI_TIMEOUT, 0, NULL); +} + /** Stop the SP805 watchdog timer from counting down by disabling interrupts. **/ @@ -149,9 +181,16 @@ SP805RegisterHandler ( IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction ) { - // ERROR: This function is not supported. - // The hardware watchdog will reset the board - return EFI_INVALID_PARAMETER; + if (mWatchdogNotify == NULL && NotifyFunction == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (mWatchdogNotify != NULL && NotifyFunction != NULL) { + return EFI_ALREADY_STARTED; + } + + mWatchdogNotify = NotifyFunction; + return EFI_SUCCESS; } /** @@ -202,19 +241,16 @@ SP805SetTimerPeriod ( SP805Stop (); } else { // Calculate the Watchdog ticks required for a delay of (TimerTicks * 100) nanoseconds - // The SP805 will count down to ZERO once, generate an interrupt and - // then it will again reload the initial value and start again. - // On the second time when it reaches ZERO, it will actually reset the board. - // Therefore, we need to load half the required delay. + // The SP805 will count down to zero and generate an interrupt. // - // WatchdogTicks = ((TimerPeriod * 100 * SP805_CLOCK_FREQUENCY) / 1GHz) / 2 ; + // WatchdogTicks = ((TimerPeriod * 100 * SP805_CLOCK_FREQUENCY) / 1GHz); // // i.e.: // - // WatchdogTicks = (TimerPeriod * SP805_CLOCK_FREQUENCY) / 20 MHz ; + // WatchdogTicks = (TimerPeriod * SP805_CLOCK_FREQUENCY) / 10 MHz ; Ticks64bit = MultU64x32 (TimerPeriod, PcdGet32 (PcdSP805WatchdogClockFrequencyInHz)); - Ticks64bit = DivU64x32 (Ticks64bit, 20000000); + Ticks64bit = DivU64x32 (Ticks64bit, 10 * 1000 * 1000); // The registers in the SP805 are only 32 bits if (Ticks64bit > MAX_UINT32) { @@ -233,9 +269,12 @@ SP805SetTimerPeriod ( SP805Start (); } + mTimerPeriod = TimerPeriod; + EXIT: // Ensure the watchdog is locked before exiting. SP805Lock (); + ASSERT_EFI_ERROR (Status); return Status; } @@ -262,25 +301,11 @@ SP805GetTimerPeriod ( OUT UINT64 *TimerPeriod ) { - UINT64 ReturnValue; - if (TimerPeriod == NULL) { return EFI_INVALID_PARAMETER; } - // Check if the watchdog is stopped - if ((MmioRead32 (SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) == 0) { - // It is stopped, so return zero. - ReturnValue = 0; - } else { - // Convert the Watchdog ticks into TimerPeriod - // Ensure 64bit arithmetic throughout because the Watchdog ticks may already - // be at the maximum 32 bit value and we still need to multiply that by 600. - ReturnValue = MultU64x32 (MmioRead32 (SP805_WDOG_LOAD_REG), 600); - } - - *TimerPeriod = ReturnValue; - + *TimerPeriod = mTimerPeriod; return EFI_SUCCESS; } @@ -343,6 +368,11 @@ SP805Initialize ( EFI_STATUS Status; EFI_HANDLE Handle; + // Find the interrupt controller protocol. ASSERT if not found. + Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, + (VOID **)&mInterrupt); + ASSERT_EFI_ERROR (Status); + // Unlock access to the SP805 registers SP805Unlock (); @@ -350,13 +380,31 @@ SP805Initialize ( SP805Stop (); // Set the watchdog to reset the board when triggered + // This is a last resort in case the interrupt handler fails if ((MmioRead32 (SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_RESEN) == 0) { MmioOr32 (SP805_WDOG_CONTROL_REG, SP805_WDOG_CTRL_RESEN); } + // Clear any pending interrupts + MmioWrite32 (SP805_WDOG_INT_CLR_REG, 0); // write of any value clears the irq + // Prohibit any rogue access to SP805 registers SP805Lock (); + if (PcdGet32 (PcdSP805WatchdogInterrupt) > 0) { + Status = mInterrupt->RegisterInterruptSource (mInterrupt, + PcdGet32 (PcdSP805WatchdogInterrupt), + SP805InterruptHandler); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: failed to register watchdog interrupt - %r\n", + __FUNCTION__, Status)); + return Status; + } + } else { + DEBUG ((DEBUG_WARN, "%a: no interrupt specified, running in RESET mode only\n", + __FUNCTION__)); + } + // // Make sure the Watchdog Timer Architectural Protocol has not been installed in the system yet. // This will avoid conflicts with the universal watchdog From patchwork Wed Dec 19 20:40:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 154296 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5369567ljp; Wed, 19 Dec 2018 12:40:45 -0800 (PST) X-Google-Smtp-Source: AFSGD/UhW/J9Egp7pFLbJOsVxxvSYNXevGC+y/eHfYxmHsiAG9EbiJHzRyWNyP8827HDdaNKa6eM X-Received: by 2002:a17:902:9887:: with SMTP id s7mr21091367plp.199.1545252045374; Wed, 19 Dec 2018 12:40:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545252045; cv=none; d=google.com; s=arc-20160816; b=V39c/keDNKyO4jgI0GsNrt4gF+rXOm8FjxXHX3h84OnfLK45cqI+aohOWqdR9FnNtE UccJr2gHmsEgQ2RsuzwWPIj7X2lUPUKQx8spGPMr91hhvZBpZTjNCNSBqfEYT1iRbLV7 ZNQzN5WsTMbUR9isEY+ysoN1l9xCkhWeLErHUEeQPPPrd7R2UVwar+4oyOt+uqaOsZCM fIA+IeKXLT3dpY3VSjD9nWGXl1oGlUzPmZbVlK2ypAyMLKAPV2UQVM9UM/KPj2ckg/ux fFv+YZY+cX87nHuUmJEm4Zx5mQ9SzxgW5GU3CMdroN3iC2Jk8w7nXg5EJDmP6xurDRFQ M3rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:delivered-to; bh=Q6Au6FBN/MKbqiazPG1uYMgvTHFRCM/5nGKgQzbMjn8=; b=flFu9qx5pb+ef71/jpZeuEmm3Gcoev9J8KklswSQ2WuVNf9/aMxmJJScLMN6hsObnY ivkIV9B2VSelU1RZi6aYubue/r9ph3KxKJd6eGFqp+hFXN1ulcT4JTCouUumxjolTK8y t7YDbbshUgUIFi2xGYKJTgeKb1E+yNw9ZqXsPUdUW5IbPUpaRMgd/2XOwhidedmXtcgF FEXcczj6/ktleeMUbBLtUKnux8qoe/8HItFKBgJK9MmhjLs18uZA4zrnneuVI8zHlGEZ WEyuRs9MKfNLh3rwYlFQ6mmHrRzIY8kfoqb7iLySkUbYKCAqt+Csa8FBg05955NgTPyU Gs4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cz6ugjHK; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id h20si16735468pgm.366.2018.12.19.12.40.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 12:40:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cz6ugjHK; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B64CB211A2D8C; Wed, 19 Dec 2018 12:40:41 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::343; helo=mail-wm1-x343.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EDF6321BADAB3 for ; Wed, 19 Dec 2018 12:40:39 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id b11so7330598wmj.1 for ; Wed, 19 Dec 2018 12:40:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uSkA3HKHt41PYnSH6aPiT28PCDE0wXohPs+7NqtU9uk=; b=cz6ugjHKD8uVgFxHBrHLoY5W7AvB8Tn3NyWZc2X2cwPbE3fIWXCJ7o9UYIVU8AyzmK tIrvNlb3T9oD8QcuG6ikgTUG50X7DAgmN373h0PpZ29pIsDo7BmpRM9fID5N9qVr9x37 q6ZqQESiIRIRX3Buk8GHfYryf9M8oIl3oZP1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uSkA3HKHt41PYnSH6aPiT28PCDE0wXohPs+7NqtU9uk=; b=YyyUrbnFltPljSJTx6Gj+izCqH5BMBCsJkUVhYr7xFFLmV5fmyGMp3ZyPSmNDiLDG6 bTXgOpF0uGfmCEkauXxYejhRzJsFlaT/uJdDvWvFnoukw23r7vHVNoSVlz0LHlOPMq2a YMNWUtiuI/h61+d8KevGiRNIoQa7ehUgM6KFLBiUqKV/nIpDXNrDRp6KAEuOqx3hPlM1 dCoBz5Ag8KwqdfIkrTjOaZgIITysfueqCYeClQJV1XixET5ZsaVliyPhIg/sf0M2HWAo v7Be2LuKSuTV/qZuYFo5B9JeGIJ4elbcMV3gE3WKXEnMHl/VvDbFqgNwZm3Fl+DR9Dxg gsRw== X-Gm-Message-State: AA+aEWbtqq6V3P+32ttVU9+oJUENee46VNjGF+lgl4nXIbs0+VsqsAdJ LRi+nGkbF7PlQOk3GTvtlIt2MXiWnTc2Sw== X-Received: by 2002:a1c:c58d:: with SMTP id v135mr7865270wmf.88.1545252037530; Wed, 19 Dec 2018 12:40:37 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:e5c9:6e00:25cb:e32e]) by smtp.gmail.com with ESMTPSA id h16sm13738439wrb.62.2018.12.19.12.40.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 12:40:36 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 19 Dec 2018 21:40:22 +0100 Message-Id: <20181219204023.6317-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181219204023.6317-1-ard.biesheuvel@linaro.org> References: <20181219204023.6317-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH v2 3/4] ArmPkg/GenericWatchdogDxe: clean up the code X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Clean up the code, by adding missing STATIC modifiers, drop redundant casts, and get rid of the 'success handling' anti pattern in the entry point code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf | 9 +- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 109 +++++++++++--------- 2 files changed, 62 insertions(+), 56 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf index ba0403d7fdc3..171bf5b9e183 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf @@ -16,17 +16,16 @@ [Defines] FILE_GUID = 0619f5c2-4858-4caa-a86a-73a21a18df6b MODULE_TYPE = DXE_DRIVER VERSION_STRING = 1.0 - ENTRY_POINT = GenericWatchdogEntry [Sources.common] GenericWatchdogDxe.c [Packages] - MdePkg/MdePkg.dec - EmbeddedPkg/EmbeddedPkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec [LibraryClasses] ArmGenericTimerCounterLib @@ -46,8 +45,8 @@ [Pcd.common] gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum [Protocols] - gEfiWatchdogTimerArchProtocolGuid - gHardwareInterrupt2ProtocolGuid + gEfiWatchdogTimerArchProtocolGuid ## ALWAYS_PRODUCES + gHardwareInterrupt2ProtocolGuid ## ALWAYS_CONSUMES [Depex] gHardwareInterrupt2ProtocolGuid diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c index 8ccf15366dfa..285727fc0e84 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -34,15 +34,16 @@ #define TIME_UNITS_PER_SECOND 10000000 // Tick frequency of the generic timer basis of the generic watchdog. -UINTN mTimerFrequencyHz = 0; +STATIC UINTN mTimerFrequencyHz = 0; /* In cases where the compare register was set manually, information about how long the watchdog was asked to wait cannot be retrieved from hardware. It is therefore stored here. 0 means the timer is not running. */ -UINT64 mNumTimerTicks = 0; +STATIC UINT64 mNumTimerTicks = 0; -EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol; +STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol; +STATIC VOID WatchdogWriteOffsetRegister ( UINT32 Value @@ -51,6 +52,7 @@ WatchdogWriteOffsetRegister ( MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value); } +STATIC VOID WatchdogWriteCompareRegister ( UINT64 Value @@ -60,6 +62,7 @@ WatchdogWriteCompareRegister ( MmioWrite32 (GENERIC_WDOG_COMPARE_VALUE_REG_HIGH, (Value >> 32) & MAX_UINT32); } +STATIC VOID WatchdogEnable ( VOID @@ -68,6 +71,7 @@ WatchdogEnable ( MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_ENABLED); } +STATIC VOID WatchdogDisable ( VOID @@ -79,6 +83,7 @@ WatchdogDisable ( /** On exiting boot services we must make sure the Watchdog Timer is stopped. **/ +STATIC VOID EFIAPI WatchdogExitBootServicesEvent ( @@ -93,6 +98,7 @@ WatchdogExitBootServicesEvent ( /* This function is called when the watchdog's first signal (WS0) goes high. It uses the ResetSystem Runtime Service to reset the board. */ +STATIC VOID EFIAPI WatchdogInterruptHandler ( @@ -141,10 +147,11 @@ WatchdogInterruptHandler ( @retval EFI_UNSUPPORTED The code does not support NotifyFunction. **/ +STATIC EFI_STATUS EFIAPI WatchdogRegisterHandler ( - IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction ) { @@ -167,10 +174,11 @@ WatchdogRegisterHandler ( in TimerPeriod 100ns units. **/ +STATIC EFI_STATUS EFIAPI WatchdogSetTimerPeriod ( - IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, IN UINT64 TimerPeriod // In 100ns units ) { @@ -222,10 +230,11 @@ WatchdogSetTimerPeriod ( @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. **/ +STATIC EFI_STATUS EFIAPI WatchdogGetTimerPeriod ( - IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, OUT UINT64 *TimerPeriod ) { @@ -270,13 +279,13 @@ WatchdogGetTimerPeriod ( Retrieves the period of the timer interrupt in 100ns units. **/ -EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = { - (EFI_WATCHDOG_TIMER_REGISTER_HANDLER)WatchdogRegisterHandler, - (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD)WatchdogSetTimerPeriod, - (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD)WatchdogGetTimerPeriod +STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = { + WatchdogRegisterHandler, + WatchdogSetTimerPeriod, + WatchdogGetTimerPeriod }; -EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL; +STATIC EFI_EVENT mEfiExitBootServicesEvent; EFI_STATUS EFIAPI @@ -288,6 +297,10 @@ GenericWatchdogEntry ( EFI_STATUS Status; EFI_HANDLE Handle; + Status = gBS->LocateProtocol (&gHardwareInterrupt2ProtocolGuid, NULL, + (VOID **)&mInterruptProtocol); + ASSERT_EFI_ERROR (Status); + /* Make sure the Watchdog Timer Architectural Protocol has not been installed in the system yet. This will avoid conflicts with the universal watchdog */ @@ -296,51 +309,45 @@ GenericWatchdogEntry ( mTimerFrequencyHz = ArmGenericTimerGetTimerFreq (); ASSERT (mTimerFrequencyHz != 0); + // Install interrupt handler + Status = mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol, + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), + WatchdogInterruptHandler); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = mInterruptProtocol->SetTriggerType (mInterruptProtocol, + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), + EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING); + if (EFI_ERROR (Status)) { + goto UnregisterHandler; + } + + // Install the Timer Architectural Protocol onto a new handle + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEfiWatchdogTimerArchProtocolGuid, &mWatchdogTimer, + NULL); + if (EFI_ERROR (Status)) { + goto UnregisterHandler; + } + // Register for an ExitBootServicesEvent - Status = gBS->CreateEvent ( - EVT_SIGNAL_EXIT_BOOT_SERVICES, - TPL_NOTIFY, - WatchdogExitBootServicesEvent, - NULL, - &EfiExitBootServicesEvent - ); - if (!EFI_ERROR (Status)) { - // Install interrupt handler - Status = gBS->LocateProtocol ( - &gHardwareInterrupt2ProtocolGuid, - NULL, - (VOID **)&mInterruptProtocol - ); - if (!EFI_ERROR (Status)) { - Status = mInterruptProtocol->RegisterInterruptSource ( - mInterruptProtocol, - FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), - WatchdogInterruptHandler - ); - if (!EFI_ERROR (Status)) { - Status = mInterruptProtocol->SetTriggerType ( - mInterruptProtocol, - FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), - EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING - ); - if (!EFI_ERROR (Status)) { - // Install the Timer Architectural Protocol onto a new handle - Handle = NULL; - Status = gBS->InstallMultipleProtocolInterfaces ( - &Handle, - &gEfiWatchdogTimerArchProtocolGuid, - &gWatchdogTimer, - NULL - ); - } - } - } - } - + Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, + WatchdogExitBootServicesEvent, NULL, + &mEfiExitBootServicesEvent); ASSERT_EFI_ERROR (Status); mNumTimerTicks = 0; WatchdogDisable (); + return EFI_SUCCESS; + +UnregisterHandler: + // Unregister the handler + mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol, + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), + NULL); return Status; } From patchwork Wed Dec 19 20:40:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 154297 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5369612ljp; Wed, 19 Dec 2018 12:40:49 -0800 (PST) X-Google-Smtp-Source: AFSGD/XkhKqKcAFMOAVZe70Ts5iDLEpCmsssB6NAkvM46qWsF/BH2EFjmyXU1xfaVKn3MZbexuBX X-Received: by 2002:a17:902:f20d:: with SMTP id gn13mr20677240plb.11.1545252048920; Wed, 19 Dec 2018 12:40:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545252048; cv=none; d=google.com; s=arc-20160816; b=EW91n2kjt4BHgX1ADSaqr+WB0wD64P3bkg4fDjsrU7adK7kXlIiJBQHbWhWxqGJEvN l18U2Kbbr4X4Ue6ufUL8d7vNHHiPmshJjce0hIQKNXRSausK2driuCs/5yCQpVj1TJfh jRwhi2IM6SG3WechO5z4gxq+pvuuMmMzMckGrBut4iKJITQLVvIKspNYTR1pnRm+ds/P 79TYdDR7eCAttLQFjpzhEo+1RjQeE7jsl32zslCNol3nOhDyHOfwyI02ZqUtLC1NotBW /PVYWUAGJ0Fm8Sm612xt0UXMn3CrG481ns2a5xFySAmQQ4aeuiZb5rprAnS3LSM9w/1m L8fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:delivered-to; bh=vHfxp4b/4HSSPg/Apy4Xs156/dX+PSaTc8fjb0VGr3M=; b=DmO2ZMJFNOVOQod4s63uvbAdoVeBcNanNf6mRiZAoT4k7fMwwQS7PE4D9heKWUkn++ fwPHA4mXt7kw06vEHkuJ9acCJsWRW3IO2CKYMUAGBhqCgKg19cnUFAx9WMyYODPlA2l0 2ePcY5jIvb4bp+EEuNtesyAhVbPQ4eTxaDkfNUZYgeYOVhGlGk+9owL3e2NviY/jF8f8 eju/VgT4tp1otVLJQajO3QICYIYcRryA9efAH3z+s5KE+WFHYO9s/boKxpRcXc7rmJuN lhGBGGofEPnN0DGOy+IuK2VTYtLd78LI5tPhIRfS2KPtBqWuxp6p/ewvzk2v7fC3e686 mtIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LHf5vKpG; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id o21si15160039pgj.415.2018.12.19.12.40.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 12:40:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LHf5vKpG; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E71DA211A2D8D; Wed, 19 Dec 2018 12:40:42 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::344; helo=mail-wm1-x344.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C2358211A2D8C for ; Wed, 19 Dec 2018 12:40:40 -0800 (PST) Received: by mail-wm1-x344.google.com with SMTP id y139so7330777wmc.5 for ; Wed, 19 Dec 2018 12:40:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=15zem50kbRvhzT/VBjLW0Z4bvtO5RuPdnEB1XBOHkZs=; b=LHf5vKpGaGl5Mn5iS0uzkb0nRaluIFeOKRDxui29EzLGMOsaGXOOKLYot/gE1VP30g 3mPWN+be4CrJOzfHlEdukI4qiOArSxmQbJ00UWHdgdbxNSBOVBjnOurkUTuyxbDWGiey 1bpWEPxpwl/Rv3FPvt/VrSR/LTX0/eOpznIjs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=15zem50kbRvhzT/VBjLW0Z4bvtO5RuPdnEB1XBOHkZs=; b=aDjdeHPp/xgQp8Nn94lcKg/TlYAeByOE5Zo+Utw3kuqAxcR2KqeaLsstvBZ6BXAl0a jtPFoNPd1PiDYI+rtAFUCaqB8ODuJe4HxesKM3LM2k3ezVde0DyQOWbd/0PgjjSYry/3 yKhmhIeguUi/8YdAzfV7cLBCtUDD8SJBnnbBR+upXGrMQ5kDZGi9sLkx9RiiA1Pg9ljd zNqtCk/K0JnYCWXiG9yasahRJBxRUXyKueD+bRx7xol8/YUkpd/NLl4YWDYvTRxcJmBl Ww+P0Vo6EbJik6IXUzaPQTxyjU4ilpWE6XbJNlv3IFsIMRocsnI8rxvsBIDxANv4Afyc XrWQ== X-Gm-Message-State: AA+aEWYaiHCkR7CsIYvjlsw6VVE3DX0XH6svuWqXvqIQQPsSepA2Qpq2 xhloXLRE0t5zh7kckK45a07eJrBWLB/vJw== X-Received: by 2002:a1c:760c:: with SMTP id r12mr7601988wmc.127.1545252038957; Wed, 19 Dec 2018 12:40:38 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:e5c9:6e00:25cb:e32e]) by smtp.gmail.com with ESMTPSA id h16sm13738439wrb.62.2018.12.19.12.40.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 12:40:38 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 19 Dec 2018 21:40:23 +0100 Message-Id: <20181219204023.6317-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181219204023.6317-1-ard.biesheuvel@linaro.org> References: <20181219204023.6317-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH v2 4/4] ArmPkg/GenericWatchdogDxe: implement RegisterHandler() method X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Even though UEFI does not appear to use it, let's implement the complete PI watchdog protocol, including handler registration, which will be invoked instead of the ResetSystem() runtime service when the watchdog timer expires. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 34 ++++++++++++++------ 1 file changed, 25 insertions(+), 9 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c index 285727fc0e84..a1ef0363eb39 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -42,6 +42,7 @@ STATIC UINTN mTimerFrequencyHz = 0; STATIC UINT64 mNumTimerTicks = 0; STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol; +STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify; STATIC VOID @@ -107,17 +108,25 @@ WatchdogInterruptHandler ( ) { STATIC CONST CHAR16 ResetString[]= L"The generic watchdog timer ran out."; + UINT64 TimerPeriod; WatchdogDisable (); mInterruptProtocol->EndOfInterrupt (mInterruptProtocol, Source); - gRT->ResetSystem ( - EfiResetCold, - EFI_TIMEOUT, - StrSize (ResetString), - (VOID *) &ResetString - ); + // + // The notify function should be called with the elapsed number of ticks + // since the watchdog was armed, which should exceed the timer period. + // We don't actually know the elapsed number of ticks, so let's return + // the timer period plus 1. + // + if (mWatchdogNotify != NULL) { + TimerPeriod = ((TIME_UNITS_PER_SECOND / mTimerFrequencyHz) * mNumTimerTicks); + mWatchdogNotify (TimerPeriod + 1); + } + + gRT->ResetSystem (EfiResetCold, EFI_TIMEOUT, StrSize (ResetString), + (CHAR16 *)ResetString); // If we got here then the reset didn't work ASSERT (FALSE); @@ -155,9 +164,16 @@ WatchdogRegisterHandler ( IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction ) { - // ERROR: This function is not supported. - // The watchdog will reset the board - return EFI_UNSUPPORTED; + if (mWatchdogNotify == NULL && NotifyFunction == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (mWatchdogNotify != NULL && NotifyFunction != NULL) { + return EFI_ALREADY_STARTED; + } + + mWatchdogNotify = NotifyFunction; + return EFI_SUCCESS; } /**