From patchwork Wed Apr 27 12:16:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 566816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44882C4332F for ; Wed, 27 Apr 2022 12:17:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233690AbiD0MUL (ORCPT ); Wed, 27 Apr 2022 08:20:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233707AbiD0MUK (ORCPT ); Wed, 27 Apr 2022 08:20:10 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5E8589CD3 for ; Wed, 27 Apr 2022 05:16:58 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id s27so2392430ljd.2 for ; Wed, 27 Apr 2022 05:16:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CDwkASM9CJ+e3T14sU+DD4Z2q62VFhOP6cklNoMqPXY=; b=KVIRDFfLSktU7040Coot+RXVSwwubG2+Pn+rFcEQhUipFAemxw1d3VfshnYEjlXng4 1i5IRcyOGalP0RNAl5pLei00N3+2omfu7YuJmzJlRUdu1iThhIHgK+0hgjhddkYJQfEw ISiRtGhBrgb+e//HhqxN7Irz9h8pdXMmFccvJ06zAqHdP7lLdkhhMqkk10dwRzUBOXid xUxmdzwweqsGjgGWibVP4dsrhhv+NhdN65rM3ZehDFvNFn3Yc0WNqUs5p7o7AkoKo5Ar I//3qtusK7zFGIea1yGuVjqszwQIiiz0WWEJ5KhPkeKuZ/Vqj/ff1dtwPBudutPOWgpf xgIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CDwkASM9CJ+e3T14sU+DD4Z2q62VFhOP6cklNoMqPXY=; b=MxdA6AJKdcEWt9zkmKiRzhkFZSAU15pQ7XN/wLFIAudz9WDdp2cJsMWpbkqjSocHcg 8yjT9LL/wlOMZkjo0vYTWxkAo91HdoFeEVoEL94ggj4kEktKbgo54hdEDHjFVcOPTwCc tDgWbfHU/f8luBv2lhDt6CtIWXNBA+RXgWz4LvIu0KdbnKlYtj4pzt+sYShQtOMCkFvc myE1s9ur/Qqc+6nuEIeLBrcFHMuGX9kLf9m0kpBg1B3TRUNmEaFP2+Zvyi7Z7QtZu1vM YljISe5BxiIEX9LS5hVyEKJiWJWm3zg9yrMbUq7+bk6Io1uXJtgFcXF4G0Ox6YYdgfZr 7nqw== X-Gm-Message-State: AOAM530BbAKXsCj7rHrDjOHdtRS/PSvlwY0OVK7as8gqn7XyDiMXqk+K m8wVSl3aYq5OZY7VulTzC2bV2w== X-Google-Smtp-Source: ABdhPJyycJt5QR0vtMnqMrJS3i3LDRRlGgCa/kL6ZdRFitrf7dD5KGT2aZbPB7vjCEJlXtLZezs0Fw== X-Received: by 2002:a05:651c:332:b0:24f:1312:9add with SMTP id b18-20020a05651c033200b0024f13129addmr9076644ljp.320.1651061816812; Wed, 27 Apr 2022 05:16:56 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y1-20020a0565123f0100b0044584339e5dsm2043388lfa.190.2022.04.27.05.16.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 05:16:56 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 1/5] PCI: dwc: Convert msi_irq to the array Date: Wed, 27 Apr 2022 15:16:49 +0300 Message-Id: <20220427121653.3158569-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427121653.3158569-1-dmitry.baryshkov@linaro.org> References: <20220427121653.3158569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm version of DWC PCIe controller supports more than 32 MSI interrupts, but they are routed to separate interrupts in groups of 32 vectors. To support such configuration, change the msi_irq field into an array. Let the DWC core handle all interrupts that were set in this array. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-exynos.c | 2 +- .../pci/controller/dwc/pcie-designware-host.c | 30 +++++++++++-------- drivers/pci/controller/dwc/pcie-designware.h | 2 +- drivers/pci/controller/dwc/pcie-keembay.c | 2 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 7 files changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index dfcdeb432dc8..0919c96dcdbd 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -483,7 +483,7 @@ static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, return pp->irq; /* MSI IRQ is muxed */ - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = dra7xx_pcie_init_irq_domain(pp); if (ret < 0) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c index 467c8d1cd7e4..4f2010bd9cd7 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -292,7 +292,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep, } pp->ops = &exynos_pcie_host_ops; - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = dw_pcie_host_init(pp); if (ret) { diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2fa86f32d964..5d90009a0f73 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -257,8 +257,11 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) static void dw_pcie_free_msi(struct pcie_port *pp) { - if (pp->msi_irq) - irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); + u32 ctrl; + + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) + if (pp->msi_irq[ctrl]) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL); irq_domain_remove(pp->msi_domain); irq_domain_remove(pp->irq_domain); @@ -368,13 +371,15 @@ int dw_pcie_host_init(struct pcie_port *pp) for (ctrl = 0; ctrl < num_ctrls; ctrl++) pp->irq_mask[ctrl] = ~0; - if (!pp->msi_irq) { - pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi"); - if (pp->msi_irq < 0) { - pp->msi_irq = platform_get_irq(pdev, 0); - if (pp->msi_irq < 0) - return pp->msi_irq; + if (!pp->msi_irq[0]) { + int irq = platform_get_irq_byname_optional(pdev, "msi"); + + if (irq < 0) { + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; } + pp->msi_irq[0] = irq; } pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; @@ -383,10 +388,11 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret) return ret; - if (pp->msi_irq > 0) - irq_set_chained_handler_and_data(pp->msi_irq, - dw_chained_msi_isr, - pp); + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + if (pp->msi_irq[ctrl] > 0) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], + dw_chained_msi_isr, + pp); ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 7d6e9b7576be..9c1a38b0a6b3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -187,7 +187,7 @@ struct pcie_port { u32 io_size; int irq; const struct dw_pcie_host_ops *ops; - int msi_irq; + int msi_irq[MAX_MSI_CTRLS]; struct irq_domain *irq_domain; struct irq_domain *msi_domain; u16 msi_msg; diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c index 1ac29a6eef22..297e6e926c00 100644 --- a/drivers/pci/controller/dwc/pcie-keembay.c +++ b/drivers/pci/controller/dwc/pcie-keembay.c @@ -338,7 +338,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie, int ret; pp->ops = &keembay_pcie_host_ops; - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = keembay_pcie_setup_msi_irq(pcie); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c index 1569e82b5568..cc7776833810 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -172,7 +172,7 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie, } pp->ops = &spear13xx_pcie_host_ops; - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = dw_pcie_host_init(pp); if (ret) { diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index b1b5f836a806..e75712db85b0 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2271,7 +2271,7 @@ static void tegra194_pcie_shutdown(struct platform_device *pdev) disable_irq(pcie->pci.pp.irq); if (IS_ENABLED(CONFIG_PCI_MSI)) - disable_irq(pcie->pci.pp.msi_irq); + disable_irq(pcie->pci.pp.msi_irq[0]); tegra194_pcie_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); From patchwork Wed Apr 27 12:16:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 566815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D0D0C4167D for ; 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Wed, 27 Apr 2022 05:16:57 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 2/5] PCI: dwc: Teach dwc core to parse additional MSI interrupts Date: Wed, 27 Apr 2022 15:16:50 +0300 Message-Id: <20220427121653.3158569-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427121653.3158569-1-dmitry.baryshkov@linaro.org> References: <20220427121653.3158569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DWC driver parses a single "msi" interrupt which gets fired when the EP sends an MSI interrupt, however for some devices (Qualcomm) MSI vectors are handled in groups by 32 vectors in each group. Add support for parsing "split" MSI interrupts. In addition to the "msi" interrupt, the code will lookup the "msi2", "msi3", etc. IRQs and use them for the MSI group interrupts. For backwards compatibility with existing DTS files, the code will not error out if these interrupts are missing. Instead it will limit itself to the number of MSI group IRQs declared in the DT file. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 23 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 5d90009a0f73..ce7071095006 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -382,6 +382,29 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->msi_irq[0] = irq; } + if (pp->has_split_msi_irq) { + char irq_name[] = "msiXXX"; + int irq; + + for (ctrl = 1; ctrl < num_ctrls; ctrl++) { + if (pp->msi_irq[ctrl]) + continue; + + snprintf(irq_name, sizeof(irq_name), "msi%d", ctrl + 1); + irq = platform_get_irq_byname_optional(pdev, irq_name); + if (irq == -ENXIO) { + num_ctrls = ctrl; + pp->num_vectors = num_ctrls * MAX_MSI_IRQS_PER_CTRL; + dev_warn(dev, "Limiting amount of MSI irqs to %d\n", pp->num_vectors); + break; + } + if (irq < 0) + return irq; + + pp->msi_irq[ctrl] = irq; + } + } + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; ret = dw_pcie_allocate_domains(pp); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9c1a38b0a6b3..3aa840a5b19c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -179,6 +179,7 @@ struct dw_pcie_host_ops { struct pcie_port { bool has_msi_ctrl:1; + bool has_split_msi_irq:1; u64 cfg0_base; void __iomem *va_cfg0_base; u32 cfg0_size; From patchwork Wed Apr 27 12:16:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 567268 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E58BC43217 for ; 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Wed, 27 Apr 2022 05:16:57 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 3/5] PCI: qcom: Handle MSI IRQs properly Date: Wed, 27 Apr 2022 15:16:51 +0300 Message-Id: <20220427121653.3158569-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427121653.3158569-1-dmitry.baryshkov@linaro.org> References: <20220427121653.3158569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Thus to receive higher MSI vectors properly, enable has_split_msi_irq support. Note, that if DT doesn't list extra MSI interrupts, DWC core will limit the amount of supported MSI vectors accordingly (to 32). Fixes: 20f1bfb8dd62 ("PCI: qcom: Add support for handling MSIs from 8 endpoints") Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 45631c0aa468..78c4e2bcf38a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1587,6 +1587,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) pci->ops = &dw_pcie_ops; pp = &pci->pp; pp->num_vectors = MAX_MSI_IRQS; + pp->has_split_msi_irq = true; pcie->pci = pci; From patchwork Wed Apr 27 12:16:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 567267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 363D6C433F5 for ; Wed, 27 Apr 2022 12:17:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233713AbiD0MUM (ORCPT ); Wed, 27 Apr 2022 08:20:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233748AbiD0MUL (ORCPT ); Wed, 27 Apr 2022 08:20:11 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A126A4EA1B for ; Wed, 27 Apr 2022 05:17:00 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id y32so2804725lfa.6 for ; Wed, 27 Apr 2022 05:17:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cLYJ0GysdHluMMr2clkUv2N03QTSVxRZN8GILwf5WB4=; b=jnLB1M/Z1nnafctw7GO8Q909Mae3PoL/DfRgh0yP+tVrcbYUoj4tHZ0weWrluv893u k79ZQk4xO/TaL656AFqFg7i2UaO4siI72QG93iio0T1v1ZYpm7rfN69i5+t6KQDc3xtq EA4GDbLJbXPKD5KXmUI4PawbaMWVVyjg2z76IxyxIwkGILLCDnAQpFRUkPIOMUCZc1Mu aVaG5NeQI9H1IemN+1H/izixpqz1jKp3LZTM0bSFAVJRrmghDNsMG2FVYfz6lH5xmUJb seJK9gmf/qNcfXlsORVhsRFUBnLCUhwThWn4MX/5joApCc0OFbLpxbXrmL/KI5cAi3yT Ikbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cLYJ0GysdHluMMr2clkUv2N03QTSVxRZN8GILwf5WB4=; b=yfUp1pvyeBhVofL45tMNKC/35EbkDATi0VPTnCFLuuCBQeBYAWA+8F0mz6V/6FkZJ7 PpNGt1wVxcyjKoGSdpvdoVy/cggJyzv3DSelslNL7c4b6Uje8aT/REIIe6ag6GBjvhp7 YYabWbt65krkIu56+K/aqWWVhEBBWDz3u0GUmJwWHnfHyZQljnbOFfiZp0L/AkoU9FuY FckwA82s68jEOFSYwPCCoLxKumdDPUSajQpO7jzcuAYodP/enHvbBnEQmW6mpJXCdc8a 10QIZlUq1pG0B/U2rafXhNoTd/cbN8wyi6DNGmjjQUjyEDoqq2uP1i//KQJNg+hIoLEQ 8GbQ== X-Gm-Message-State: AOAM531w/TrCDrZbtsbx0Tk/75Eh59g+qKCb9Wkj8kuW5FXssTZcHq3n S1zaGkkfpJh/M1UtOpqk/EQV0g== X-Google-Smtp-Source: ABdhPJw58095SdUUdrJzp7HdEZXP2UF/S+ebEQUHfPVJLoauSNg2gxYOevOxfcP8s5q1QrG0LNoKoQ== X-Received: by 2002:a05:6512:3da1:b0:472:28c9:851b with SMTP id k33-20020a0565123da100b0047228c9851bmr2606638lfv.359.1651061818840; Wed, 27 Apr 2022 05:16:58 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y1-20020a0565123f0100b0044584339e5dsm2043388lfa.190.2022.04.27.05.16.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 05:16:58 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 4/5] dt-bindings: pci/qcom,pcie: support additional MSI interrupts Date: Wed, 27 Apr 2022 15:16:52 +0300 Message-Id: <20220427121653.3158569-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427121653.3158569-1-dmitry.baryshkov@linaro.org> References: <20220427121653.3158569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 48d56b073564..8447076bef97 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -42,11 +42,21 @@ properties: maxItems: 5 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: + minItems: 1 + maxItems: 8 items: - const: msi + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: msi8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. From patchwork Wed Apr 27 12:16:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 567266 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37A1CC3527B for ; Wed, 27 Apr 2022 12:17:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233679AbiD0MUO (ORCPT ); Wed, 27 Apr 2022 08:20:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233748AbiD0MUN (ORCPT ); Wed, 27 Apr 2022 08:20:13 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7631889CD3 for ; Wed, 27 Apr 2022 05:17:01 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id c15so2354820ljr.9 for ; Wed, 27 Apr 2022 05:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ga1FXFUoff60uV1gZjfSxxZrosbrRhkS2aF6jySEeu8=; b=IcljhcOdPTP29vZlW5X6ro/FUMEN8BihPCMjQ4DLD17n66EQMN3ngucpWlHM/1adsk zJOOSqbDVUtln5M8uXceQPT/9IJop7SWDuLHhQgHRXry6Mv52rZvxaj8FcDWjkkFOWIA OwKFt/UkKddYIlAxdNzXZisw3D8MTb4reAK7fdGijT+pOXIqp75xVLzK+XQh4+MMKxk8 SYKMdHh5oDfToYb+vHFJ2QEjWT42q3fAQUUsolFPimdQ107oJfsCMuKz+wH2JBt/hz26 8+83hfCjLp3+d2l4sGxgdll5iV4aTlCfffJXiwIdDdKVtcI9lSXFhxPaEN7n9duq9FkP MWKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ga1FXFUoff60uV1gZjfSxxZrosbrRhkS2aF6jySEeu8=; b=6X/Vdl/dMV+JPWEo4tkTmVGY62gUwbm4/fLBWD5jtkljwm5RWiqS292nxgBKwNx8A8 QQ/5L1EKtcJV7aGNSYKJpyL88Ea/oRQXEVaGonnF1rTMOOn80A+a9JVEK18TtCFIactQ BuCF3DLUCwxWXRrYidU6OHx9lRi92EronQAE1lehd4R8va6p4OHEZCNZ7xQjF5dx3ukM wHOgbjnHs1gvFD5qNNAGA3CeyOhNXcm3KjM11Y7nSIdidjgpdFySIBSj7MxAeRB2u/6/ 6PGhHd5t/LYi4LBUmUago8mC6VljFjp15N6b4cWNAYTYnAVK6uf/U6GDeiiur+jnLuWp Tl4Q== X-Gm-Message-State: AOAM5338ILTQhToio1c3w0WIdRbV4JAtOB53pqny4c0W227do3GaEUOv QOgThhFDaQd+/IPLI0zYceXZTg== X-Google-Smtp-Source: ABdhPJzzpKoE3lHAYhI7agfuzEbxveMnjFO6GHr912Gvl7Gw/JzYOQtHj9siquDy56l3ZF0qn9fusA== X-Received: by 2002:a2e:9e50:0:b0:24f:14e0:6a25 with SMTP id g16-20020a2e9e50000000b0024f14e06a25mr7994316ljk.121.1651061819670; Wed, 27 Apr 2022 05:16:59 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y1-20020a0565123f0100b0044584339e5dsm2043388lfa.190.2022.04.27.05.16.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 05:16:59 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 5/5] arm64: dts: qcom: sm8250: provide additional MSI interrupts Date: Wed, 27 Apr 2022 15:16:53 +0300 Message-Id: <20220427121653.3158569-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427121653.3158569-1-dmitry.baryshkov@linaro.org> References: <20220427121653.3158569-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SM8250 each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe0 host. Tested on Qualcomm RB5 platform with first group of MSI interrupts being used by the PME and attached ath11k WiFi chip using second group of MSI interrupts. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 410272a1e19b..0659ac45c651 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1807,8 +1807,15 @@ pcie0: pci@1c00000 { ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */